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Merge branch 'feat/support_esp32s31_icg_control' into 'master'

Browse Source 
feat(esp_hw_support): support PMU clock ICG management for esp32s31

Closes PM-760

See merge request espressif/esp-idf!48863
This commit is contained in:
Wu Zheng Hui
2026-06-18 16:21:32 +08:00
parent 344edcd13f 61be47b739
commit 7e4773ef38
41 changed files with 215 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_ledc/src/ledc.c
+1 -1
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@@ -1008,7 +1008,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
// 3. keep related module integrated clock gating on during sleep
#if SOC_PM_SUPPORT_PMU_CLK_ICG
esp_sleep_clock_config(ESP_SLEEP_CLOCK_LEDC, ESP_SLEEP_CLOCK_OPTION_UNGATE);
esp_sleep_clock_config(ESP_SLEEP_CLOCK_LEDC0, ESP_SLEEP_CLOCK_OPTION_UNGATE);
esp_sleep_clock_config(ESP_SLEEP_CLOCK_IOMUX, ESP_SLEEP_CLOCK_OPTION_UNGATE);
#endif
}
components/esp_driver_uart/src/uart_wakeup.c
+2 -2
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@@ -83,7 +83,7 @@ esp_err_t uart_wakeup_setup(uart_port_t uart_num, const uart_wakeup_cfg_t *cfg)
#if SOC_PM_SUPPORT_PMU_CLK_ICG
esp_sleep_sub_mode_config(ESP_SLEEP_DIG_USE_XTAL_MODE, true);
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
esp_sleep_clock_config(UART_LL_SLEEP_CLOCK(uart_num), ESP_SLEEP_CLOCK_OPTION_UNGATE);
esp_sleep_clock_config(SLEEP_UART_ICG(uart_num), ESP_SLEEP_CLOCK_OPTION_UNGATE);
esp_sleep_clock_config(ESP_SLEEP_CLOCK_IOMUX, ESP_SLEEP_CLOCK_OPTION_UNGATE);
#endif
#if (SOC_UART_LP_NUM >= 1)
@@ -154,7 +154,7 @@ esp_err_t uart_wakeup_clear(uart_port_t uart_num, uart_wakeup_mode_t wakeup_mode
// When hp uarts are utilized, the main XTAL need to be PU and UARTx & IOMX ICG need to be ungate
if (uart_num < SOC_UART_HP_NUM) {
#if SOC_PM_SUPPORT_PMU_CLK_ICG
esp_sleep_clock_config(UART_LL_SLEEP_CLOCK(uart_num), ESP_SLEEP_CLOCK_OPTION_GATE);
esp_sleep_clock_config(SLEEP_UART_ICG(uart_num), ESP_SLEEP_CLOCK_OPTION_GATE);
esp_sleep_clock_config(ESP_SLEEP_CLOCK_IOMUX, ESP_SLEEP_CLOCK_OPTION_GATE);
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_OFF);
esp_sleep_sub_mode_config(ESP_SLEEP_DIG_USE_XTAL_MODE, false);
components/esp_hal_uart/esp32c5/include/hal/uart_ll.h
-2
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@@ -26,8 +26,6 @@
#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&LP_UART)))
// Get UART sleep clock with giving uart num
#define UART_LL_SLEEP_CLOCK(num) (((num) == UART_NUM_0) ? (ESP_SLEEP_CLOCK_UART0) : (ESP_SLEEP_CLOCK_UART1))
#define UART_LL_REG_FIELD_BIT_SHIFT(hw) (((hw) == &LP_UART) ? 3 : 0)
components/esp_hal_uart/esp32c6/include/hal/uart_ll.h
-2
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@@ -26,8 +26,6 @@
#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&LP_UART)))
// Get UART sleep clock with giving uart num
#define UART_LL_SLEEP_CLOCK(num) (((num) == UART_NUM_0) ? (ESP_SLEEP_CLOCK_UART0) : (ESP_SLEEP_CLOCK_UART1))
#define UART_LL_REG_FIELD_BIT_SHIFT(hw) (((hw) == &LP_UART) ? 3 : 0)
components/esp_hal_uart/esp32c61/include/hal/uart_ll.h
-2
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@@ -24,8 +24,6 @@
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&UART2)))
// Get UART sleep clock with giving uart num
#define UART_LL_SLEEP_CLOCK(num) (((num) == UART_NUM_0) ? (ESP_SLEEP_CLOCK_UART0) : (((num) == UART_NUM_1) ? (ESP_SLEEP_CLOCK_UART1) : (ESP_SLEEP_CLOCK_UART2)))
#define UART_LL_PULSE_TICK_CNT_MAX UART_LOWPULSE_MIN_CNT_V
components/esp_hal_uart/esp32h2/include/hal/uart_ll.h
-2
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@@ -24,8 +24,6 @@
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1))
// Get UART sleep clock with giving uart num
#define UART_LL_SLEEP_CLOCK(num) (((num) == UART_NUM_0) ? (ESP_SLEEP_CLOCK_UART0) : (ESP_SLEEP_CLOCK_UART1))
#define UART_LL_PULSE_TICK_CNT_MAX UART_LOWPULSE_MIN_CNT_V
components/esp_hal_uart/esp32h21/include/hal/uart_ll.h
-2
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@@ -24,8 +24,6 @@
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1))
// Get UART sleep clock with giving uart num
#define UART_LL_SLEEP_CLOCK(num) (((num) == UART_NUM_0) ? (ESP_SLEEP_CLOCK_UART0) : (ESP_SLEEP_CLOCK_UART1))
#define UART_LL_PULSE_TICK_CNT_MAX UART_LOWPULSE_MIN_CNT_V
components/esp_hal_uart/esp32h4/include/hal/uart_ll.h
-2
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@@ -22,8 +22,6 @@
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1))
// Get UART sleep clock with giving uart num
#define UART_LL_SLEEP_CLOCK(num) (((num) == UART_NUM_0) ? (ESP_SLEEP_CLOCK_UART0) : (ESP_SLEEP_CLOCK_UART1))
#define UART_LL_PULSE_TICK_CNT_MAX UART_LOWPULSE_MIN_CNT_V
components/esp_hal_uart/esp32p4/include/hal/uart_ll.h
-8
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@@ -33,14 +33,6 @@
(num) == 2 ? (&UART2) : \
(num) == 3 ? (&UART3) : \
(num) == 4 ? (&UART4) : (&LP_UART))
// Get UART sleep clock with giving uart num
#define UART_LL_SLEEP_CLOCK(num) \
( ((num) == UART_NUM_0) ? (ESP_SLEEP_CLOCK_UART0) \
: ((num) == UART_NUM_1) ? (ESP_SLEEP_CLOCK_UART1) \
: ((num) == UART_NUM_2) ? (ESP_SLEEP_CLOCK_UART2) \
: ((num) == UART_NUM_3) ? (ESP_SLEEP_CLOCK_UART3) \
: ((num) == UART_NUM_4) ? (ESP_SLEEP_CLOCK_UART4) \
: (ESP_SLEEP_CLOCK_MAX))
#define UART_LL_REG_FIELD_BIT_SHIFT(hw) (((hw) == &LP_UART) ? 3 : 0)
components/esp_hw_support/CMakeLists.txt
+1 -1
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@@ -12,7 +12,7 @@ if(${target} STREQUAL "linux")
return()
endif()
set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_regi2c)
set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_regi2c esp_hal_uart)
set(priv_requires efuse # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
spi_flash
bootloader_support
components/esp_hw_support/include/esp_private/esp_pmu.h
+2 -1
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@@ -19,6 +19,7 @@
#include "hal/pmu_hal.h"
#include "pmu_param.h"
#include "pmu_bit_defs.h"
#include "soc/pmu_icg_mapping.h"
#endif
#ifdef __cplusplus
@@ -278,7 +279,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
* @return hardware time overhead in us
*/
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, uint32_t clk_flags, uint32_t adjustment, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, pmu_sleep_clk_icg_flags_t clk_flags, uint32_t adjustment, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
/**
* @brief Prepare the chip to enter sleep mode
components/esp_hw_support/include/esp_private/esp_sleep_internal.h
+5 -1
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@@ -8,6 +8,7 @@
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_sleep.h"
#include "hal/uart_types.h"
#ifdef __cplusplus
extern "C" {
@@ -134,7 +135,7 @@ void esp_sleep_restore_isolated_digital_gpio(void);
*/
typedef enum {
ESP_SLEEP_CLOCK_IOMUX, //!< The clock ICG cell mapping of IOMUX
ESP_SLEEP_CLOCK_LEDC, //!< The clock ICG cell mapping of LEDC
ESP_SLEEP_CLOCK_LEDC0, //!< The clock ICG cell mapping of LEDC0
ESP_SLEEP_CLOCK_UART0, //!< The clock ICG cell mapping of UART0
ESP_SLEEP_CLOCK_UART1, //!< The clock ICG cell mapping of UART1
#if SOC_UART_HP_NUM > 2
@@ -152,6 +153,9 @@ typedef enum {
ESP_SLEEP_CLOCK_MAX //!< Number of ICG cells
} esp_sleep_clock_t;
// Get UART sleep clock with giving uart num (num must be a valid HP UART port)
#define SLEEP_UART_ICG(num) ((esp_sleep_clock_t)(ESP_SLEEP_CLOCK_UART0 + (num)))
/**
* @brief Clock ICG options
*/
components/esp_hw_support/port/esp32c5/pmu_sleep.c
+1 -1
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@@ -234,7 +234,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
+1 -1
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@@ -332,7 +332,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32c6/pmu_sleep.c
+1 -1
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@@ -218,7 +218,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
+1 -1
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@@ -328,7 +328,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32c61/pmu_sleep.c
+1 -1
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@@ -228,7 +228,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
+1 -1
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@@ -328,7 +328,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h2/pmu_sleep.c
+1 -1
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@@ -131,7 +131,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
+1 -1
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@@ -320,7 +320,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h21/pmu_sleep.c
+1 -1
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@@ -144,7 +144,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32h21/private_include/pmu_param.h
+1 -1
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@@ -356,7 +356,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h4/pmu_sleep.c
+1 -1
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@@ -129,7 +129,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32h4/private_include/pmu_param.h
+1 -1
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@@ -360,7 +360,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+1 -1
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@@ -160,7 +160,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32p4/pmu_sleep_clock_icg.c
+1 -1
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@@ -182,7 +182,7 @@ void pmu_sleep_clock_icg_config(void *icg_context, const uint32_t icg_func)
if (icg_func & BIT(PMU_ICG_FUNC_ENA_IOMUX)) {
regdma_link_set_write_wait_content(clock_icg->regdma_desc[28], PERI_CLK_EN(IOMUX), PERI_CLK_MASK(IOMUX));
}
if (icg_func & BIT(PMU_ICG_FUNC_ENA_LEDC)) {
if (icg_func & BIT(PMU_ICG_FUNC_ENA_LEDC0)) {
regdma_link_set_write_wait_content(clock_icg->regdma_desc[24], PERI_CLK_EN(LEDC), PERI_CLK_MASK(LEDC));
}
if (icg_func & BIT(PMU_ICG_FUNC_ENA_UART0)) {
components/esp_hw_support/port/esp32p4/private_include/pmu_icg_mapping.h
+1 -1
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@@ -21,5 +21,5 @@
#define PMU_ICG_FUNC_ENA_UART2 8
#define PMU_ICG_FUNC_ENA_UART3 9
#define PMU_ICG_FUNC_ENA_UART4 10
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_LEDC0 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
+2 -2
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@@ -357,7 +357,7 @@ typedef struct {
.lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = { 0, clk_flags } \
.icg_func = { 0, (uint32_t)(clk_flags) } \
}
#else // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
@@ -373,7 +373,7 @@ typedef struct {
.dig_pad_slp_sel = 0, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = { 0, clk_flags } \
.icg_func = { 0, (uint32_t)(clk_flags) } \
}
#endif
components/esp_hw_support/port/esp32s31/pmu_sleep.c
+6 -2
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@@ -197,7 +197,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
@@ -217,7 +217,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->analog = analog_default;
} else {
// Get light sleep digital_default
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
config->digital = digital_default;
// Get light sleep analog default
@@ -286,6 +286,10 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi
static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig)
{
const bool icg_func_enabled = (dig->icg_func.clock[0] != 0) || (dig->icg_func.clock[1] != 0);
pmu_ll_hp_set_icg_sysclk_enable(ctx->hal->dev, HP(SLEEP), icg_func_enabled);
pmu_ll_hp_set_icg_func(ctx->hal->dev, HP(SLEEP), dig->icg_func.clock[0], dig->icg_func.clock[1]);
pmu_ll_hp_set_icg_apb(ctx->hal->dev, HP(SLEEP), dig->icg_apb.clock[0], dig->icg_apb.clock[1]);
pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel);
pmu_ll_hp_set_hold_all_hp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.hp_pad_hold_all);
pmu_ll_hp_set_hold_all_lp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.lp_pad_hold_all);
components/esp_hw_support/port/esp32s31/private_include/pmu_param.h
+15 -3
View File
@@ -11,6 +11,7 @@
#include <esp_types.h>
#include "soc/pmu_struct.h"
#include "hal/pmu_hal.h"
#include "soc/pmu_icg_mapping.h"
#ifdef __cplusplus
extern "C" {
@@ -324,6 +325,12 @@ typedef struct {
typedef struct {
pmu_hp_sys_cntl_reg_t syscntl;
struct {
uint32_t clock[2];
} icg_func;
struct {
uint32_t clock[2];
} icg_apb;
} pmu_sleep_digital_config_t;
@@ -334,17 +341,22 @@ typedef struct {
.hp_pad_hold_all = 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
.c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \
} \
}, \
.icg_func = { .clock = { 0, 0 } }, \
}
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) { \
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
.syscntl = { \
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.lp_pad_hold_all = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
.hp_pad_hold_all = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
.c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \
} \
}, \
.icg_func = { \
.clock = { PMU_SLEEP_CLK_ICG_FUNC_LO(clk_flags), \
PMU_SLEEP_CLK_ICG_FUNC_HI(clk_flags) } \
}, \
}
typedef struct {
components/esp_hw_support/sleep_modes.c
+39 -26
View File
@@ -155,10 +155,6 @@
#include "hal/mspi_ll.h"
#endif
#if SOC_PM_SUPPORT_PMU_CLK_ICG
#include "soc/pmu_icg_mapping.h"
#endif
#include "hal/rtc_timer_hal.h"
#if SOC_VBAT_SUPPORTED
@@ -287,6 +283,7 @@ typedef struct {
} domain[ESP_PD_DOMAIN_MAX];
#if SOC_PM_SUPPORT_PMU_CLK_ICG
int16_t clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
pmu_sleep_clk_icg_flags_t sleep_clk_icg_flags;
#endif
portMUX_TYPE lock;
uint64_t sleep_duration;
@@ -339,6 +336,7 @@ static sleep_config_t s_config = {
},
#if SOC_PM_SUPPORT_PMU_CLK_ICG
.clock_icg_refs[0 ... ESP_SLEEP_CLOCK_MAX - 1] = 0,
.sleep_clk_icg_flags = 0,
#endif
.lock = portMUX_INITIALIZER_UNLOCKED,
.ccount_ticks_record = 0,
@@ -371,7 +369,9 @@ void esp_sleep_overhead_out_time_refresh(void)
static uint32_t get_power_down_flags(void);
static uint32_t get_sleep_flags(uint32_t pd_flags, bool deepsleep);
static uint32_t get_sleep_clock_icg_flags(void);
#if SOC_PM_SUPPORT_PMU_CLK_ICG
static void sleep_update_clk_icg_flags(void);
#endif
#if CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_SLEEP && SOC_RTC_WDT_SUPPORTED
static uint32_t get_sleep_rtc_wdt_timeout(uint64_t sleep_duration);
static uint32_t calc_sleep_slow_clk_required_cycles(uint32_t timeout, uint32_t rtc_slow_clk_cal_period);
@@ -1000,7 +1000,7 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
return result;
}
static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, uint32_t clk_flags, esp_sleep_mode_t mode, bool allow_sleep_rejection)
static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_t mode, bool allow_sleep_rejection)
{
// Stop UART output so that output is not lost due to APB frequency change.
// For light sleep, suspend UART output — it will resume after wakeup.
@@ -1142,6 +1142,7 @@ static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, uint32_t cl
#endif
pmu_sleep_config_t config;
pmu_sleep_clk_icg_flags_t clk_flags = deep_sleep ? 0 : s_config.sleep_clk_icg_flags;
pmu_sleep_init(pmu_sleep_config_default(&config, sleep_flags, clk_flags, s_config.sleep_time_adjustment,
rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period,
deep_sleep), deep_sleep);
@@ -1324,7 +1325,7 @@ static esp_err_t FORCE_IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection)
uint32_t sleep_flags = get_sleep_flags(force_pd_flags | pd_flags, true);
// Enter sleep
esp_err_t err = ESP_OK;
if (esp_sleep_start(sleep_flags, 0, ESP_SLEEP_MODE_DEEP_SLEEP, allow_sleep_rejection) == ESP_ERR_SLEEP_REJECT) {
if (esp_sleep_start(sleep_flags, ESP_SLEEP_MODE_DEEP_SLEEP, allow_sleep_rejection) == ESP_ERR_SLEEP_REJECT) {
err = ESP_ERR_SLEEP_REJECT;
#if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
/* Cache Resume 2: if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is enabled, cache has been suspended in esp_sleep_start */
@@ -1374,10 +1375,10 @@ esp_err_t FORCE_IRAM_ATTR esp_deep_sleep_try_to_start(void)
* Helper function which handles entry to and exit from light sleep
* Placed into IRAM as flash may need some time to be powered on.
*/
static esp_err_t esp_light_sleep_inner(uint32_t sleep_flags, uint32_t clk_flags,
static esp_err_t esp_light_sleep_inner(uint32_t sleep_flags,
uint32_t flash_enable_time_us) __attribute__((noinline));
static SLEEP_FN_ATTR esp_err_t esp_light_sleep_inner(uint32_t sleep_flags, uint32_t clk_flags,
static SLEEP_FN_ATTR esp_err_t esp_light_sleep_inner(uint32_t sleep_flags,
uint32_t flash_enable_time_us)
{
#if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
@@ -1385,7 +1386,7 @@ static SLEEP_FN_ATTR esp_err_t esp_light_sleep_inner(uint32_t sleep_flags, uint3
#endif
// Enter sleep
esp_err_t reject = esp_sleep_start(sleep_flags, clk_flags, ESP_SLEEP_MODE_LIGHT_SLEEP, true);
esp_err_t reject = esp_sleep_start(sleep_flags, ESP_SLEEP_MODE_LIGHT_SLEEP, true);
#if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
// If VDDSDIO regulator was controlled by RTC registers before sleep,
@@ -1543,8 +1544,10 @@ esp_err_t esp_light_sleep_start(void)
uint32_t pd_flags = get_power_down_flags();
// Append flags to indicate the sleep sub-mode and modify the pd_flags according to sub-mode attributes.
uint32_t sleep_flags = get_sleep_flags(pd_flags, false);
// Decide whicn clock can be ungate during sleep
uint32_t clk_flags = get_sleep_clock_icg_flags();
// Decide which clock can be ungate during sleep
#if SOC_PM_SUPPORT_PMU_CLK_ICG
sleep_update_clk_icg_flags();
#endif
// Re-calibrate the RTC clock
sleep_low_power_clock_calibration(false);
@@ -1695,7 +1698,7 @@ esp_err_t esp_light_sleep_start(void)
#endif
else {
// Enter sleep, then wait for flash to be ready on wakeup
err = esp_light_sleep_inner(sleep_flags, clk_flags, flash_enable_time_us);
err = esp_light_sleep_inner(sleep_flags, flash_enable_time_us);
}
// light sleep wakeup flag only makes sense after a successful light sleep
@@ -3122,26 +3125,36 @@ static SLEEP_FN_ATTR uint32_t get_sleep_flags(uint32_t sleep_flags, bool deepsle
return sleep_flags;
}
static SLEEP_FN_ATTR uint32_t get_sleep_clock_icg_flags(void)
{
uint32_t clk_flags = 0;
#if SOC_PM_SUPPORT_PMU_CLK_ICG
SLEEP_FN_ATTR static void sleep_update_clk_icg_flags(void)
{
pmu_sleep_clk_icg_flags_t clk_flags = 0;
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
clk_flags |= BIT(PMU_ICG_FUNC_ENA_IOMUX);
clk_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
}
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_LEDC] > 0) {
clk_flags |= BIT(PMU_ICG_FUNC_ENA_LEDC);
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
clk_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
}
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
clk_flags |= BIT(PMU_ICG_FUNC_ENA_UART0);
clk_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
}
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
clk_flags |= BIT(PMU_ICG_FUNC_ENA_UART1);
clk_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
}
#if SOC_UART_HP_NUM > 2
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_UART2] > 0) {
clk_flags |= BIT(PMU_ICG_FUNC_ENA_UART2);
clk_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART2);
}
#endif
#if SOC_UART_HP_NUM > 3
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_UART3] > 0) {
clk_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART3);
}
#endif
#if SOC_UART_HP_NUM > 4
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_UART4] > 0) {
clk_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART4);
}
#endif
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
@@ -3150,12 +3163,12 @@ static SLEEP_FN_ATTR uint32_t get_sleep_clock_icg_flags(void)
* As all 32 bits of ICG_FUNC are occupied, the ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK
* has been remapped to PMU_ICG_FUNC_ENA_RETENTION.*/
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK] > 0) {
clk_flags |= BIT(PMU_ICG_FUNC_ENA_RETENTION);
clk_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_RETENTION);
}
#endif
#endif /* SOC_PM_SUPPORT_PMU_CLK_ICG */
return clk_flags;
s_config.sleep_clk_icg_flags = clk_flags;
}
#endif /* SOC_PM_SUPPORT_PMU_CLK_ICG */
#if CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_SLEEP && SOC_RTC_WDT_SUPPORTED
/* TODO: PM-609 */
components/soc/esp32c5/include/soc/pmu_icg_mapping.h
+15 -2
View File
@@ -1,11 +1,13 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_SPI2 2
@@ -61,8 +63,19 @@
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_LEDC0 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_TWAI1 30
#define PMU_ICG_FUNC_ENA_TWAI0 31
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#ifdef __cplusplus
}
#endif
components/soc/esp32c6/include/soc/pmu_icg_mapping.h
+16 -2
View File
@@ -1,11 +1,13 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#ifndef _SOC_ICG_MAP_H_
#define _SOC_ICG_MAP_H_
#include <stdint.h>
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
@@ -39,7 +41,7 @@
#define PMU_ICG_FUNC_ENA_I2S_RX 2
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_LEDC0 27
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_PARL_RX 25
@@ -65,4 +67,16 @@
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_HPCORE 17
#define PMU_ICG_FUNC_ENA_HPBUS 15
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#ifdef __cplusplus
}
#endif
#endif /* _SOC_ICG_MAP_H_ */
components/soc/esp32c61/include/soc/pmu_icg_mapping.h
+15 -2
View File
@@ -1,11 +1,13 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_SPI2 2
@@ -50,6 +52,17 @@
#define PMU_ICG_FUNC_ENA_UART2 22
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_LEDC0 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_I2C 29
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#ifdef __cplusplus
}
#endif
components/soc/esp32h2/include/soc/pmu_icg_mapping.h
+16 -2
View File
@@ -1,10 +1,13 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_SPI2 2
@@ -57,7 +60,18 @@
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_LEDC0 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_TWAI 31
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#ifdef __cplusplus
}
#endif
components/soc/esp32h21/include/soc/pmu_icg_mapping.h
+15 -2
View File
@@ -1,11 +1,13 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_SPI2 2
@@ -59,8 +61,19 @@
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_LEDC0 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_I2C0 29
#define PMU_ICG_FUNC_ENA_I2C1 29
#define PMU_ICG_FUNC_ENA_TWAI0 31
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#ifdef __cplusplus
}
#endif
components/soc/esp32h4/include/soc/pmu_icg_mapping.h
+14 -1
View File
@@ -6,6 +6,8 @@
#pragma once
#include <stdint.h>
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_SPI2 2
@@ -60,8 +62,19 @@
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_LEDC0 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_TWAI1 30
#define PMU_ICG_FUNC_ENA_TWAI0 31
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/include/soc/pmu_icg_mapping.h
+14 -1
View File
@@ -1,11 +1,13 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#define PMU_ICG_APB_ENA_CORE0_CPU 0
#define PMU_ICG_APB_ENA_CORE1_CPU 1
#define PMU_ICG_APB_ENA_CORE0_CLIC 2
@@ -61,3 +63,14 @@
#define PMU_ICG_FUNC_ENA_HP_CLKRST 24
#define PMU_ICG_FUNC_ENA_SYSREG_APB 25
#define PMU_ICG_FUNC_ENA_INTRMTX_APB 26
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#ifdef __cplusplus
}
#endif
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -1491,6 +1491,10 @@ config SOC_PM_SUPPORT_MODEM_CLOCK_DOMAIN_ICG
bool
default y
config SOC_PM_SUPPORT_PMU_CLK_ICG
bool
default y
config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
bool
default y
components/soc/esp32s31/include/soc/pmu_icg_mapping.h
+16 -1
View File
@@ -1,11 +1,13 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#define PMU_ICG_APB_ENA_PWM0 0
#define PMU_ICG_APB_ENA_PWM1 1
#define PMU_ICG_APB_ENA_PWM2 2
@@ -100,3 +102,16 @@
#define PMU_ICG_FUNC_ENA_PSRAM_MON 53
#define PMU_ICG_FUNC_ENA_TCM_MON 54
#define PMU_ICG_FUNC_ENA_REGDMA 55
#ifdef __cplusplus
extern "C" {
#endif
typedef uint64_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_FUNC_LO(f) ((uint32_t)(f))
#define PMU_SLEEP_CLK_ICG_FUNC_HI(f) ((uint32_t)((f) >> 32))
#ifdef __cplusplus
}
#endif
components/soc/esp32s31/include/soc/soc_caps.h
+2
View File
@@ -554,6 +554,8 @@
#define SOC_PM_SUPPORT_MODEM_CLOCK_DOMAIN_ICG (1)
#define SOC_PM_SUPPORT_PMU_CLK_ICG (1)
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
#define SOC_PM_CPU_RETENTION_BY_SW (1)