feat(esp_hw_support): support clock output in esp32h4 mp

components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h

@@ -15,6 +15,7 @@
 #include <stdlib.h>
 #include <stdbool.h>
 #include "soc/soc.h"
+#include "soc/gpio_ext_reg.h"
 #include "soc/gpio_struct.h"
 #include "soc/lp_aon_struct.h"
 #include "soc/pmu_struct.h"
@@ -734,6 +735,19 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num
     IO_MUX.gpio[gpio_num].mcu_oe = 1;
 }
 
+/**
+ * @brief  Control the pin in the IOMUX
+ *
+ * @param  bmap   write mask of control value
+ * @param  val    Control value
+ * @param  shift  write mask shift of control value
+ */
+__attribute__((always_inline))
+static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
+{
+    SET_PERI_REG_BITS(GPIO_EXT_PIN_CTRL_REG, bmap, val, shift);
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c

@@ -138,7 +138,7 @@ TEST_CASE("GPIO output internal clock one-to-many", "[gpio_output_clock][ignore]
 #if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3
     test_clk_out_sig[3] = CLKOUT_SIG_PLL_F80M;
 #else
-    test_clk_out_sig[3] = CLKOUT_SIG_RC_32K;
+    test_clk_out_sig[3] = CLKOUT_SIG_CPU;
 #endif
 
     // Test the excess clock channel request assertion

components/hal/esp32h4/clk_tree_hal.c

@@ -7,6 +7,7 @@
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/assert.h"
+#include "hal/gpio_ll.h"
 
 uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
 {
@@ -64,3 +65,13 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
     HAL_ASSERT(freq == SOC_XTAL_FREQ_32M);
     return freq;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}

components/hal/esp32h4/include/hal/clk_tree_ll.h

@@ -672,6 +672,30 @@ static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_f
     return REG_READ(RTC_FIX_US_LOW_REG) | ((uint64_t)REG_READ(RTC_FIX_US_HIGH_REG) << 32);
 }
 
+/*
+ * Enable/Disable the clock gate for clock output signal source
+*/
+static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
+{
+    switch (clk_src)
+    {
+        case CLKOUT_SIG_MODEM_8M:
+            PCR.ctrl_clk_out_en.clk8_oen = en;
+            break;
+        case CLKOUT_SIG_MODEM_16M:
+            PCR.ctrl_clk_out_en.clk16_oen = en;
+            break;
+        case CLKOUT_SIG_MODEM_32M:
+            PCR.ctrl_clk_out_en.clk32_oen = en;
+            break;
+        case CLKOUT_SIG_XTAL:
+            PCR.ctrl_clk_out_en.clk_xtal_oen = en;
+            break;
+        default:
+            break;
+    }
+}
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c5/include/soc/clk_tree_defs.h

@@ -535,7 +535,6 @@ typedef enum {
 
 //////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
 typedef enum {
-    CLKOUT_SIG_INVALID          = 0,
     CLKOUT_SIG_PLL_F160M        = 1,    /*!< Divided from PLL_F480M */
     CLKOUT_SIG_PLL_F22M         = 2,    /*!< Divided from PLL_F160M */
     CLKOUT_SIG_PLL_F40M         = 3,    /*!< Divided from PLL_F160M */
@@ -550,8 +549,8 @@ typedef enum {
     CLKOUT_SIG_XTAL32K          = 0x15, /*!< External 32kHz crystal clock */
     CLKOUT_SIG_EXT32K           = 0x16, /*!< External slow clock input through XTAL_32K_P */
     CLKOUT_SIG_RC_FAST          = 0x17, /*!< RC fast clock, about 17.5MHz */
-    CLKOUT_SIG_RC_32K           = 0x18, /*!< Internal slow RC oscillator */
     CLKOUT_SIG_RC_SLOW          = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_INVALID          = 0xFF,
 } soc_clkout_sig_id_t;
 
 //////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////

components/soc/esp32c61/include/soc/clk_tree_defs.h

@@ -367,7 +367,6 @@ typedef enum {
 
 //////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
 typedef enum {
-    CLKOUT_SIG_INVALID          = 0,
     CLKOUT_SIG_PLL_F160M        = 1,    /*!< Divided from PLL_F480M */
     CLKOUT_SIG_PLL_F22M         = 2,    /*!< Divided from PLL_F160M */
     CLKOUT_SIG_PLL_F40M         = 3,    /*!< Divided from PLL_F160M */
@@ -383,6 +382,7 @@ typedef enum {
     CLKOUT_SIG_RC_FAST          = 0x17, /*!< RC fast clock, about 17.5MHz */
     CLKOUT_SIG_RC_32K           = 0x18, /*!< Internal slow RC oscillator */
     CLKOUT_SIG_RC_SLOW          = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_INVALID          = 0xFF,
 } soc_clkout_sig_id_t;
 
 //////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -395,6 +395,18 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    bool
+    default y
+
+config SOC_CLOCKOUT_HAS_SOURCE_GATE
+    bool
+    default y
+
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_RTCIO_PIN_COUNT
     int
     default 6

components/soc/esp32h4/include/soc/clk_tree_defs.h

@@ -291,6 +291,27 @@ typedef enum {
     FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as ROM default clock source */
 } soc_periph_flash_clk_src_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+/**
+ * @brief Clock output signal ID
+ */
+typedef enum {
+    CLKOUT_SIG_MODEM_8M         = 0x1,  /*!< 8MHz clock for modem (clk8M) */
+    CLKOUT_SIG_MODEM_16M        = 0x2,  /*!< 16MHz clock for modem (clk16) */
+    CLKOUT_SIG_MODEM_32M        = 0x3,  /*!< 32MHz clock for modem (clk32) */
+    CLKOUT_SIG_XTAL             = 0x5,  /*!< 32MHz main crystal oscillator clock */
+    CLKOUT_SIG_RTC_FAST         = 0x6,  /*!< 16MHz RTC fast clock from LP system */
+    CLKOUT_SIG_TIMERGROUP0      = 0xC,  /*!< 32MHz timergroup0 function clock (default is xtal) */
+    CLKOUT_SIG_I2S_APB          = 0xF,  /*!< 32MHz I2S APB clock */
+    CLKOUT_SIG_CPU              = 0x10, /*!< 32MHz CPU debug mode clock */
+    CLKOUT_SIG_AHB              = 0x11, /*!< 32MHz REGDMA AHB clock */
+    CLKOUT_SIG_XTAL32K          = 0x15, /*!< 32KHz external crystal clock */
+    CLKOUT_SIG_EXT32K           = 0x16, /*!< 32KHz external slow clock input */
+    CLKOUT_SIG_RC_FAST          = 0x17, /*!< 8MHz FOSC clock (RTC fast clock) */
+    CLKOUT_SIG_RC_SLOW          = 0x19, /*!< 600KHz SOSC clock (RTC slow clock) */
+    CLKOUT_SIG_INVALID          = 0xFF,
+} soc_clkout_sig_id_t;
+
 //////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
 /**
  * @brief Clock frequency calculation source selection

components/soc/esp32h4/include/soc/clkout_channel.h

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? GPIO_EXT_CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? GPIO_EXT_CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? GPIO_EXT_CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? GPIO_EXT_CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? GPIO_EXT_CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? GPIO_EXT_CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h4/include/soc/soc_caps.h

@@ -234,7 +234,9 @@
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  1
 
 // The Clock Out signal is route to the pin by GPIO matrix
-// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    1 TODO: [ESP32H4] IDF-12361
+#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX        (1)
+#define SOC_CLOCKOUT_HAS_SOURCE_GATE            (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM           (3)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT                 6

components/soc/esp32h4/register/soc/gpio_ext_reg.h

@@ -14,7 +14,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA_MISC_REG register
  *  MISC Register
  */
-#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_BASE + 0x4)
+#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x4)
 /** GPIO_EXT_SIGMADELTA_CLK_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable the clock for sigma delta modulation.
  *  0: Not enable
@@ -29,7 +29,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA0_REG register
  *  Duty cycle configuration register for SDM channel 0
  */
-#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_BASE + 0x8)
+#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x8)
 /** GPIO_EXT_SD0_IN : R/W; bitpos: [7:0]; default: 0;
  *  Configures the duty cycle of sigma delta modulation output.
  */
@@ -48,7 +48,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA1_REG register
  *  Duty cycle configuration register for SDM channel 1
  */
-#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_BASE + 0xc)
+#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0xc)
 /** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0;
  *  Configures the duty cycle of sigma delta modulation output.
  */
@@ -67,7 +67,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA2_REG register
  *  Duty cycle configuration register for SDM channel 2
  */
-#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_BASE + 0x10)
+#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x10)
 /** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0;
  *  Configures the duty cycle of sigma delta modulation output.
  */
@@ -86,7 +86,7 @@ extern "C" {
 /** GPIO_EXT_SIGMADELTA3_REG register
  *  Duty cycle configuration register for SDM channel 3
  */
-#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_BASE + 0x14)
+#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0x14)
 /** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0;
  *  Configures the duty cycle of sigma delta modulation output.
  */
@@ -105,7 +105,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH0_REG register
  *  Glitch Filter Configure Register of Channel0
  */
-#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_BASE + 0xd8)
+#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0xd8)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable channel 0 of Glitch Filter.
  *  0: Not enable
@@ -151,7 +151,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH1_REG register
  *  Glitch Filter Configure Register of Channel1
  */
-#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_BASE + 0xdc)
+#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0xdc)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable channel 1 of Glitch Filter.
  *  0: Not enable
@@ -197,7 +197,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH2_REG register
  *  Glitch Filter Configure Register of Channel2
  */
-#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_BASE + 0xe0)
+#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0xe0)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable channel 2 of Glitch Filter.
  *  0: Not enable
@@ -243,7 +243,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH3_REG register
  *  Glitch Filter Configure Register of Channel3
  */
-#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_BASE + 0xe4)
+#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0xe4)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable channel 3 of Glitch Filter.
  *  0: Not enable
@@ -289,7 +289,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH4_REG register
  *  Glitch Filter Configure Register of Channel4
  */
-#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_BASE + 0xe8)
+#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0xe8)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable channel 4 of Glitch Filter.
  *  0: Not enable
@@ -335,7 +335,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH5_REG register
  *  Glitch Filter Configure Register of Channel5
  */
-#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_BASE + 0xec)
+#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0xec)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable channel 5 of Glitch Filter.
  *  0: Not enable
@@ -381,7 +381,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH6_REG register
  *  Glitch Filter Configure Register of Channel6
  */
-#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_BASE + 0xf0)
+#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0xf0)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable channel 6 of Glitch Filter.
  *  0: Not enable
@@ -427,7 +427,7 @@ extern "C" {
 /** GPIO_EXT_GLITCH_FILTER_CH7_REG register
  *  Glitch Filter Configure Register of Channel7
  */
-#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_BASE + 0xf4)
+#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0xf4)
 /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
  *  Configures whether or not to enable channel 7 of Glitch Filter.
  *  0: Not enable
@@ -473,7 +473,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register
  *  ETM configuration register for channel 0
  */
-#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_BASE + 0x118)
+#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118)
 /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Configures to select GPIO for ETM event channel.
  *  0: Select GPIO0
@@ -500,7 +500,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register
  *  ETM configuration register for channel 1
  */
-#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_BASE + 0x11c)
+#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c)
 /** GPIO_EXT_ETM_CH1_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Configures to select GPIO for ETM event channel.
  *  0: Select GPIO0
@@ -527,7 +527,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register
  *  ETM configuration register for channel 2
  */
-#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_BASE + 0x120)
+#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120)
 /** GPIO_EXT_ETM_CH2_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Configures to select GPIO for ETM event channel.
  *  0: Select GPIO0
@@ -554,7 +554,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register
  *  ETM configuration register for channel 3
  */
-#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_BASE + 0x124)
+#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124)
 /** GPIO_EXT_ETM_CH3_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Configures to select GPIO for ETM event channel.
  *  0: Select GPIO0
@@ -581,7 +581,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register
  *  ETM configuration register for channel 4
  */
-#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_BASE + 0x128)
+#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128)
 /** GPIO_EXT_ETM_CH4_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Configures to select GPIO for ETM event channel.
  *  0: Select GPIO0
@@ -608,7 +608,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register
  *  ETM configuration register for channel 5
  */
-#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_BASE + 0x12c)
+#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c)
 /** GPIO_EXT_ETM_CH5_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Configures to select GPIO for ETM event channel.
  *  0: Select GPIO0
@@ -635,7 +635,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register
  *  ETM configuration register for channel 6
  */
-#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_BASE + 0x130)
+#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130)
 /** GPIO_EXT_ETM_CH6_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Configures to select GPIO for ETM event channel.
  *  0: Select GPIO0
@@ -662,7 +662,7 @@ extern "C" {
 /** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register
  *  ETM configuration register for channel 7
  */
-#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_BASE + 0x134)
+#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134)
 /** GPIO_EXT_ETM_CH7_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
  *  Configures to select GPIO for ETM event channel.
  *  0: Select GPIO0
@@ -689,7 +689,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P0_CFG_REG register
  *  GPIO selection register 0 for ETM
  */
-#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_BASE + 0x158)
+#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158)
 /** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0;
  *  Configures to select an ETM task channel for GPIO0.
  *  0: Select channel 0
@@ -794,7 +794,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P1_CFG_REG register
  *  GPIO selection register 1 for ETM
  */
-#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
+#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c)
 /** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0;
  *  Configures to select an ETM task channel for GPIO5.
  *  0: Select channel 0
@@ -899,7 +899,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P2_CFG_REG register
  *  GPIO selection register 2 for ETM
  */
-#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_BASE + 0x160)
+#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160)
 /** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0;
  *  Configures to select an ETM task channel for GPIO10.
  *  0: Select channel 0
@@ -1004,7 +1004,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P3_CFG_REG register
  *  GPIO selection register 3 for ETM
  */
-#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_BASE + 0x164)
+#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164)
 /** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0;
  *  Configures to select an ETM task channel for GPIO15.
  *  0: Select channel 0
@@ -1109,7 +1109,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P4_CFG_REG register
  *  GPIO selection register 4 for ETM
  */
-#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_BASE + 0x168)
+#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168)
 /** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0;
  *  Configures to select an ETM task channel for GPIO20.
  *  0: Select channel 0
@@ -1214,7 +1214,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P5_CFG_REG register
  *  GPIO selection register 5 for ETM
  */
-#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
+#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x16c)
 /** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [2:0]; default: 0;
  *  Configures to select an ETM task channel for GPIO25.
  *  0: Select channel 0
@@ -1319,7 +1319,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P6_CFG_REG register
  *  GPIO selection register 6 for ETM
  */
-#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_BASE + 0x170)
+#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x170)
 /** GPIO_EXT_ETM_TASK_GPIO30_SEL : R/W; bitpos: [2:0]; default: 0;
  *  Configures to select an ETM task channel for GPIO30.
  *  0: Select channel 0
@@ -1424,7 +1424,7 @@ extern "C" {
 /** GPIO_EXT_ETM_TASK_P7_CFG_REG register
  *  GPIO selection register 7 for ETM
  */
-#define GPIO_EXT_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_BASE + 0x174)
+#define GPIO_EXT_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x174)
 /** GPIO_EXT_ETM_TASK_GPIO35_SEL : R/W; bitpos: [2:0]; default: 0;
  *  Configures to select an ETM task channel for GPIO35.
  *  0: Select channel 0
@@ -1526,10 +1526,39 @@ extern "C" {
 #define GPIO_EXT_ETM_TASK_GPIO39_EN_V  0x00000001U
 #define GPIO_EXT_ETM_TASK_GPIO39_EN_S  29
 
+/** GPIO_EXT_PIN_CTRL_REG register
+ *  Clock Output Configuration Register
+ */
+ #define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_EXT_BASE + 0x1e0)
+ /** GPIO_EXT_CLK_OUT1 : R/W; bitpos: [4:0]; default: 0;
+  *  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
+  *  CLK_OUT_out1 can be found in peripheral output signals.
+  */
+ #define GPIO_EXT_CLK_OUT1    0x0000001FU
+ #define GPIO_EXT_CLK_OUT1_M  (GPIO_EXT_CLK_OUT1_V << GPIO_EXT_CLK_OUT1_S)
+ #define GPIO_EXT_CLK_OUT1_V  0x0000001FU
+ #define GPIO_EXT_CLK_OUT1_S  0
+ /** GPIO_EXT_CLK_OUT2 : R/W; bitpos: [9:5]; default: 0;
+  *  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
+  *  CLK_OUT_out2 can be found in peripheral output signals.
+  */
+ #define GPIO_EXT_CLK_OUT2    0x0000001FU
+ #define GPIO_EXT_CLK_OUT2_M  (GPIO_EXT_CLK_OUT2_V << GPIO_EXT_CLK_OUT2_S)
+ #define GPIO_EXT_CLK_OUT2_V  0x0000001FU
+ #define GPIO_EXT_CLK_OUT2_S  5
+ /** GPIO_EXT_CLK_OUT3 : R/W; bitpos: [14:10]; default: 0;
+  *  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
+  *  CLK_OUT_out3 can be found in peripheral output signals.
+  */
+ #define GPIO_EXT_CLK_OUT3    0x0000001FU
+ #define GPIO_EXT_CLK_OUT3_M  (GPIO_EXT_CLK_OUT3_V << GPIO_EXT_CLK_OUT3_S)
+ #define GPIO_EXT_CLK_OUT3_V  0x0000001FU
+ #define GPIO_EXT_CLK_OUT3_S  10
+
 /** GPIO_EXT_VERSION_REG register
  *  Version control register
  */
-#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_BASE + 0x1fc)
+#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc)
 /** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37818704;
  *  Version control register.
  */

components/soc/esp32h4/register/soc/gpio_ext_struct.h

@@ -202,6 +202,31 @@ typedef union {
     uint32_t val;
 } gpio_ext_etm_task_pn_cfg_reg_t;
 
+/** Group: Pin Control Register */
+/** Type of pin_ctrl register
+ *  Clock Output Configuration Register
+ */
+ typedef union {
+    struct {
+        /** clk_out1 : R/W; bitpos: [4:0]; default: 0;
+         *  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
+         *  CLK_OUT_out1 can be found in peripheral output signals.
+         */
+        uint32_t clk_out1:5;
+        /** clk_out2 : R/W; bitpos: [9:5]; default: 0;
+         *  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
+         *  CLK_OUT_out2 can be found in peripheral output signals.
+         */
+        uint32_t clk_out2:5;
+        /** clk_out3 : R/W; bitpos: [14:10]; default: 0;
+         *  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
+         *  CLK_OUT_out3 can be found in peripheral output signals.
+         */
+        uint32_t clk_out3:5;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} gpio_ext_pin_ctrl_reg_t;
 
 /** Group: Version Register */
 /** Type of ext_version register
@@ -240,7 +265,8 @@ typedef struct {
     volatile gpio_glitch_filter_dev_t ext_glitch_filter;
     uint32_t reserved_0f8[8];
     volatile gpio_etm_dev_t etm;
-    uint32_t reserved_178[33];
+    uint32_t reserved_178[32];
+    volatile gpio_ext_pin_ctrl_reg_t pin_ctrl;
     volatile gpio_ext_version_reg_t ext_version;
 } gpio_ext_dev_t;