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fix(pmu): update cpll_bbpll_apll_mpll enable config

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This commit is contained in:
hongshuqing
2026-04-27 14:30:19 +08:00
parent 3f3ef6f08e
commit 7c665c106c
2 changed files with 202 additions and 8 deletions
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components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h
+32 -8
View File
@@ -90,7 +90,8 @@ typedef struct {
*/
static inline __attribute__((always_inline)) void clk_ll_cpll_enable(void)
{
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_CPLL);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_XPD_CPLL | PMU_TIE_HIGH_XPD_CPLL_I2C);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_GLOBAL_CPLL_ICG);
SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN);
}
@@ -99,8 +100,29 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_enable(void)
*/
static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void)
{
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_GLOBAL_CPLL_ICG) ;
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_XPD_CPLL | PMU_TIE_LOW_XPD_CPLL_I2C);
CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN);
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_CPLL);
}
/**
* @brief Power up BBPLL circuit
*/
static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
{
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG);
SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN);
}
/**
* @brief Power down BBPLL circuit
*/
static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
{
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG) ;
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_XPD_BBPLL | PMU_TIE_LOW_XPD_BBPLL_I2C);
CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN);
}
/**
@@ -108,7 +130,8 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void)
*/
static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
{
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_APLL);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_XPD_APLL | PMU_TIE_HIGH_XPD_APLL_I2C);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_GLOBAL_APLL_ICG);
SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN);
}
@@ -117,8 +140,9 @@ static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
*/
static inline __attribute__((always_inline)) void clk_ll_apll_disable(void)
{
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_GLOBAL_APLL_ICG) ;
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_XPD_APLL | PMU_TIE_LOW_XPD_APLL_I2C);
CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN);
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_APLL);
}
/**
@@ -126,8 +150,8 @@ static inline __attribute__((always_inline)) void clk_ll_apll_disable(void)
*/
static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void)
{
REG_SET_BIT(PMU_PSRAM_CFG_REG, PMU_PSRAM_XPD);
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_MPLL);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_GLOBAL_MPLL_ICG) ;
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_XPD_MPLL | PMU_TIE_HIGH_XPD_MPLL_I2C);
SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN);
}
@@ -136,9 +160,9 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void)
*/
static inline __attribute__((always_inline)) void clk_ll_mpll_disable(void)
{
REG_CLR_BIT(PMU_PSRAM_CFG_REG, PMU_PSRAM_XPD);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_GLOBAL_MPLL_ICG) ;
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_XPD_MPLL | PMU_TIE_LOW_XPD_MPLL_I2C);
CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN);
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_MPLL);
}
/**
components/soc/esp32s31/register/soc/pmu_reg.h
+170
View File
@@ -1877,6 +1877,176 @@ extern "C" {
#define PMU_TIE_HIGH_XPD_PLL_M (PMU_TIE_HIGH_XPD_PLL_V << PMU_TIE_HIGH_XPD_PLL_S)
#define PMU_TIE_HIGH_XPD_PLL_V 0x0000000FU
#define PMU_TIE_HIGH_XPD_PLL_S 27
/** PMU_TIE_LOW_XPD_CPLL_I2C : WT; bitpos: [0]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_CPLL_I2C (BIT(0))
#define PMU_TIE_LOW_XPD_CPLL_I2C_M (PMU_TIE_LOW_XPD_CPLL_I2C_V << PMU_TIE_LOW_XPD_CPLL_I2C_S)
#define PMU_TIE_LOW_XPD_CPLL_I2C_V 0x00000001U
#define PMU_TIE_LOW_XPD_CPLL_I2C_S 0
/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [1]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(1))
#define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S)
#define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U
#define PMU_TIE_LOW_XPD_BBPLL_I2C_S 1
/** PMU_TIE_LOW_XPD_APLL_I2C : WT; bitpos: [2]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_APLL_I2C (BIT(2))
#define PMU_TIE_LOW_XPD_APLL_I2C_M (PMU_TIE_LOW_XPD_APLL_I2C_V << PMU_TIE_LOW_XPD_APLL_I2C_S)
#define PMU_TIE_LOW_XPD_APLL_I2C_V 0x00000001U
#define PMU_TIE_LOW_XPD_APLL_I2C_S 2
/** PMU_TIE_LOW_XPD_MPLL_I2C : WT; bitpos: [3]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_MPLL_I2C (BIT(3))
#define PMU_TIE_LOW_XPD_MPLL_I2C_M (PMU_TIE_LOW_XPD_MPLL_I2C_V << PMU_TIE_LOW_XPD_MPLL_I2C_S)
#define PMU_TIE_LOW_XPD_MPLL_I2C_V 0x00000001U
#define PMU_TIE_LOW_XPD_MPLL_I2C_S 3
/** PMU_TIE_LOW_XPD_CPLL : WT; bitpos: [4]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_CPLL (BIT(4))
#define PMU_TIE_LOW_XPD_CPLL_M (PMU_TIE_LOW_XPD_CPLL_V << PMU_TIE_LOW_XPD_CPLL_S)
#define PMU_TIE_LOW_XPD_CPLL_V 0x00000001U
#define PMU_TIE_LOW_XPD_CPLL_S 4
/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_BBPLL (BIT(5))
#define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S)
#define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U
#define PMU_TIE_LOW_XPD_BBPLL_S 5
/** PMU_TIE_LOW_XPD_APLL : WT; bitpos: [6]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_APLL (BIT(6))
#define PMU_TIE_LOW_XPD_APLL_M (PMU_TIE_LOW_XPD_APLL_V << PMU_TIE_LOW_XPD_APLL_S)
#define PMU_TIE_LOW_XPD_APLL_V 0x00000001U
#define PMU_TIE_LOW_XPD_APLL_S 6
/** PMU_TIE_LOW_XPD_MPLL : WT; bitpos: [7]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_XPD_MPLL (BIT(7))
#define PMU_TIE_LOW_XPD_MPLL_M (PMU_TIE_LOW_XPD_MPLL_V << PMU_TIE_LOW_XPD_MPLL_S)
#define PMU_TIE_LOW_XPD_MPLL_V 0x00000001U
#define PMU_TIE_LOW_XPD_MPLL_S 7
/** PMU_TIE_LOW_GLOBAL_CPLL_ICG : WT; bitpos: [8]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG (BIT(8))
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_M (PMU_TIE_LOW_GLOBAL_CPLL_ICG_V << PMU_TIE_LOW_GLOBAL_CPLL_ICG_S)
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_V 0x00000001U
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_S 8
/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [9]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(9))
#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S)
#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U
#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 9
/** PMU_TIE_LOW_GLOBAL_APLL_ICG : WT; bitpos: [10]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_APLL_ICG (BIT(10))
#define PMU_TIE_LOW_GLOBAL_APLL_ICG_M (PMU_TIE_LOW_GLOBAL_APLL_ICG_V << PMU_TIE_LOW_GLOBAL_APLL_ICG_S)
#define PMU_TIE_LOW_GLOBAL_APLL_ICG_V 0x00000001U
#define PMU_TIE_LOW_GLOBAL_APLL_ICG_S 10
/** PMU_TIE_LOW_GLOBAL_MPLL_ICG : WT; bitpos: [11]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_MPLL_ICG (BIT(11))
#define PMU_TIE_LOW_GLOBAL_MPLL_ICG_M (PMU_TIE_LOW_GLOBAL_MPLL_ICG_V << PMU_TIE_LOW_GLOBAL_MPLL_ICG_S)
#define PMU_TIE_LOW_GLOBAL_MPLL_ICG_V 0x00000001U
#define PMU_TIE_LOW_GLOBAL_MPLL_ICG_S 11
/** PMU_TIE_HIGH_GLOBAL_CPLL_ICG : R/W; bitpos: [19]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG (BIT(19))
#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_CPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_CPLL_ICG_S)
#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_V 0x00000001U
#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_S 19
/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : R/W; bitpos: [20]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(20))
#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S)
#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U
#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 20
/** PMU_TIE_HIGH_GLOBAL_APLL_ICG : R/W; bitpos: [21]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_GLOBAL_APLL_ICG (BIT(21))
#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_M (PMU_TIE_HIGH_GLOBAL_APLL_ICG_V << PMU_TIE_HIGH_GLOBAL_APLL_ICG_S)
#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_V 0x00000001U
#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_S 21
/** PMU_TIE_HIGH_GLOBAL_MPLL_ICG : R/W; bitpos: [22]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_GLOBAL_MPLL_ICG (BIT(22))
#define PMU_TIE_HIGH_GLOBAL_MPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_MPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_MPLL_ICG_S)
#define PMU_TIE_HIGH_GLOBAL_MPLL_ICG_V 0x00000001U
#define PMU_TIE_HIGH_GLOBAL_MPLL_ICG_S 22
/** PMU_TIE_HIGH_XPD_CPLL_I2C : WT; bitpos: [23]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_CPLL_I2C (BIT(23))
#define PMU_TIE_HIGH_XPD_CPLL_I2C_M (PMU_TIE_HIGH_XPD_CPLL_I2C_V << PMU_TIE_HIGH_XPD_CPLL_I2C_S)
#define PMU_TIE_HIGH_XPD_CPLL_I2C_V 0x00000001U
#define PMU_TIE_HIGH_XPD_CPLL_I2C_S 23
/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [24]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(24))
#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S)
#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U
#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 24
/** PMU_TIE_HIGH_XPD_APLL_I2C : WT; bitpos: [25]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_APLL_I2C (BIT(25))
#define PMU_TIE_HIGH_XPD_APLL_I2C_M (PMU_TIE_HIGH_XPD_APLL_I2C_V << PMU_TIE_HIGH_XPD_APLL_I2C_S)
#define PMU_TIE_HIGH_XPD_APLL_I2C_V 0x00000001U
#define PMU_TIE_HIGH_XPD_APLL_I2C_S 25
/** PMU_TIE_HIGH_XPD_MPLL_I2C : WT; bitpos: [26]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_MPLL_I2C (BIT(26))
#define PMU_TIE_HIGH_XPD_MPLL_I2C_M (PMU_TIE_HIGH_XPD_MPLL_I2C_V << PMU_TIE_HIGH_XPD_MPLL_I2C_S)
#define PMU_TIE_HIGH_XPD_MPLL_I2C_V 0x00000001U
#define PMU_TIE_HIGH_XPD_MPLL_I2C_S 26
/** PMU_TIE_HIGH_XPD_CPLL : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_CPLL (BIT(27))
#define PMU_TIE_HIGH_XPD_CPLL_M (PMU_HP_ACTIVE_XPD_CPLL_V << PMU_HP_ACTIVE_XPD_CPLL_S)
#define PMU_TIE_HIGH_XPD_CPLL_V 0x00000001U
#define PMU_TIE_HIGH_XPD_CPLL_S 27
/** PMU_TIE_HIGH_XPD_BBPLL : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_BBPLL (BIT(28))
#define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S)
#define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U
#define PMU_TIE_HIGH_XPD_BBPLL_S 28
/** PMU_TIE_HIGH_XPD_APLL : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_APLL (BIT(29))
#define PMU_TIE_HIGH_XPD_APLL_M (PMU_HP_ACTIVE_XPD_APLL_V << PMU_HP_ACTIVE_XPD_APLL_S)
#define PMU_TIE_HIGH_XPD_APLL_V 0x00000001U
#define PMU_TIE_HIGH_XPD_APLL_S 29
/** PMU_TIE_HIGH_XPD_MPLL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define PMU_TIE_HIGH_XPD_MPLL (BIT(30))
#define PMU_TIE_HIGH_XPD_MPLL_M (PMU_HP_ACTIVE_XPD_MPLL_V << PMU_HP_ACTIVE_XPD_MPLL_S)
#define PMU_TIE_HIGH_XPD_MPLL_V 0x00000001U
#define PMU_TIE_HIGH_XPD_MPLL_S 30
/** PMU_IMM_SLEEP_SYSCLK_REG register
* need_des