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fix(driver_spi): fixed esp32p4 gpspi with dma potential crash or stuck
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@@ -23,6 +23,8 @@ extern "C"
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{
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{
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#endif
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#endif
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#define SPI_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
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//NOTE!! If both A and B are not defined, '#if (A==B)' is true, because GCC use 0 stand for undefined symbol
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//NOTE!! If both A and B are not defined, '#if (A==B)' is true, because GCC use 0 stand for undefined symbol
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#if SOC_GPSPI_SUPPORTED && defined(SOC_GDMA_BUS_AXI) && (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI)
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#if SOC_GPSPI_SUPPORTED && defined(SOC_GDMA_BUS_AXI) && (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI)
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#define DMA_DESC_MEM_ALIGN_SIZE 8
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#define DMA_DESC_MEM_ALIGN_SIZE 8
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@@ -379,6 +379,14 @@ esp_err_t spicommon_dma_desc_alloc(spi_host_device_t host_id, int cfg_max_sz, in
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}
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}
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return ESP_ERR_NO_MEM;
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return ESP_ERR_NO_MEM;
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}
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}
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// cache sync using align_up length thanks to heap alloc already consider the cache alignment requirement
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uint8_t aligned_len = SPI_ALIGN_UP(sizeof(spi_dma_desc_t) * dma_desc_ct, bus_ctx[host_id]->bus_attr.cache_align_int);
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// write back and then invalidate the cache, because later we will read/write the link list items by non-cached address
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esp_err_t ret = esp_cache_msync(dma_ctx->dmadesc_tx, aligned_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
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ESP_RETURN_ON_FALSE_ISR((ret == ESP_OK) || (ret == ESP_ERR_NOT_SUPPORTED), ESP_ERR_INVALID_ARG, SPI_TAG, "dma desc sync failed");
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ret = esp_cache_msync(dma_ctx->dmadesc_rx, aligned_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
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ESP_RETURN_ON_FALSE_ISR((ret == ESP_OK) || (ret == ESP_ERR_NOT_SUPPORTED), ESP_ERR_INVALID_ARG, SPI_TAG, "dma desc sync failed");
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dma_ctx->dma_desc_num = dma_desc_ct;
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dma_ctx->dma_desc_num = dma_desc_ct;
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*actual_max_sz = dma_desc_ct * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
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*actual_max_sz = dma_desc_ct * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
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return ESP_OK;
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return ESP_OK;
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