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fix(esp32p4): fix efuse, encryption and other rev_min usage

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Xiao Xufeng
2026-01-28 21:46:00 +08:00
parent 29587bb50a
commit 79f7427729
14 changed files with 47 additions and 32 deletions
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components/esp_hw_support/port/esp32p4/Kconfig.hw_support
+2 -1
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@@ -12,7 +12,8 @@ config ESP32P4_SELECTS_REV_LESS_V3
choice ESP32P4_REV_MIN
prompt "Minimum Supported ESP32-P4 Revision"
default ESP32P4_REV_MIN_1
default ESP32P4_REV_MIN_300 if IDF_CI_BUILD
default ESP32P4_REV_MIN_301
help
Required minimum chip revision. ESP-IDF will check for it and
reject to boot if the chip revision fails the check.
components/esp_hw_support/port/esp32p4/pmu_init.c
+2 -2
View File
@@ -177,7 +177,7 @@ static void pmu_hp_system_init_default(pmu_context_t *ctx)
pmu_hp_system_param_default(mode, &param);
pmu_hp_system_init(ctx, mode, &param);
}
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
lp_sys_ll_set_hp_mem_lowpower_mode(MEM_AUX_DEEPSLEEP);
#endif
}
@@ -196,7 +196,7 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
pmu_lp_system_param_default(mode, &param);
pmu_lp_system_init(ctx, mode, &param);
}
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
lp_sys_ll_set_lp_mem_lowpower_mode(MEM_AUX_DEEPSLEEP);
#endif
}
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+6 -2
View File
@@ -423,7 +423,9 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
}
} else {
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
if (efuse_hal_chip_revision() == 300) {
lp_clkrst_ll_boot_from_lp_ram(true);
}
#endif
}
@@ -454,8 +456,10 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
ldo_ll_enable(LDO_ID2UNIT(CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN), true);
#endif
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
// Set reset vector back to HP ROM after deepsleep request rejected
lp_clkrst_ll_boot_from_lp_ram(false);
if (efuse_hal_chip_revision() == 300) {
// Set reset vector back to HP ROM after deepsleep request rejected
lp_clkrst_ll_boot_from_lp_ram(false);
}
#endif
}
components/esp_hw_support/port/esp32p4/rtc_clk_init.c
+3 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -67,7 +67,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
hp_dcmvset = pvt_hp_dcmvset;
}
// Switch to DCDC
#if CONFIG_ESP32P4_REV_MIN_301
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
unsigned chip_version = efuse_hal_chip_revision();
if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
@@ -78,7 +78,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset);
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
esp_rom_delay_us(1000);
#if CONFIG_ESP32P4_REV_MIN_301
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg
CLEAR_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);