feat(parlio): support parlio on s31

components/soc/esp32s31/include/soc/Kconfig.soc_caps.in

@@ -91,6 +91,14 @@ config SOC_ETM_SUPPORTED
     bool
     default y
 
+config SOC_PARLIO_SUPPORTED
+    bool
+    default y
+
+config SOC_PARLIO_LCD_SUPPORTED
+    bool
+    default y
+
 config SOC_ASYNC_MEMCPY_SUPPORTED
     bool
     default y
@@ -871,6 +879,34 @@ config SOC_TWAI_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
+config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
+    int
+    default 16
+
+config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
+    int
+    default 16
+
+config SOC_PARLIO_TX_CLK_SUPPORT_GATING
+    bool
+    default y
+
+config SOC_PARLIO_RX_CLK_SUPPORT_GATING
+    bool
+    default y
+
+config SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
+    bool
+    default y
+
+config SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
+config SOC_PARLIO_SUPPORT_I80_LCD
+    bool
+    default y
+
 config SOC_AES_GDMA
     bool
     default y

components/soc/esp32s31/include/soc/clk_tree_defs.h

@@ -530,6 +530,24 @@ typedef enum {
     I2S_CLK_SRC_EXTERNAL = -1,                          /*!< Select external clock as source clock */
 } soc_periph_i2s_clk_src_t;
 
+//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of PARLIO
+ */
+#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F160M}
+
+/**
+ * @brief PARLIO clock source
+ */
+typedef enum {
+    PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
+    PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
+    PARLIO_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    PARLIO_CLK_SRC_EXTERNAL = -1,                     /*!< Select EXTERNAL clock as the source clock */
+    PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,   /*!< Select PLL_F160M as the default clock choice */
+} soc_periph_parlio_clk_src_t;
+
 //////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
 typedef enum {
     CLKOUT_SIG_MPLL_500M         = 0,   /*!< MPLL output at 500MHz */

components/soc/esp32s31/include/soc/soc_caps.h

@@ -45,7 +45,8 @@
 #define SOC_TWAI_SUPPORTED              1
 #define SOC_TWAI_FD_SUPPORTED           1
 #define SOC_ETM_SUPPORTED               1
-// #define SOC_PARLIO_SUPPORTED            1      // TODO: [ESP32S31] IDF-14711
+#define SOC_PARLIO_SUPPORTED            1
+#define SOC_PARLIO_LCD_SUPPORTED        1
 #define SOC_ASYNC_MEMCPY_SUPPORTED      1
 #define SOC_USB_OTG_SUPPORTED           1
 // #define SOC_USB_SERIAL_JTAG_SUPPORTED   1      // TODO: [ESP32S31] IDF-14788
@@ -343,6 +344,15 @@
 #define SOC_TWAI_RANGE_FILTER_NUM           1U
 #define SOC_TWAI_SUPPORT_SLEEP_RETENTION    1
 
+/*-------------------------- PARLIO CAPS --------------------------------------*/
+#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH      16 /*!< Number of data lines of the TX unit */
+#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH      16 /*!< Number of data lines of the RX unit */
+#define SOC_PARLIO_TX_CLK_SUPPORT_GATING       1  /*!< Support gating TX clock */
+#define SOC_PARLIO_RX_CLK_SUPPORT_GATING       1  /*!< Support gating RX clock */
+#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission */
+#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION     1  /*!< Support back up registers before sleep */
+#define SOC_PARLIO_SUPPORT_I80_LCD             1  /*!< Support to drive I80 interfaced LCD */
+
 /*-------------------------- AES CAPS ----------------------------------------*/
 #define SOC_AES_GDMA                            (1)
 #define SOC_AES_SUPPORT_DMA                     (1)

components/soc/esp32s31/register/soc/parl_io_reg.h

@@ -83,6 +83,7 @@ extern "C" {
  *  1: bus width is 2.
  *  2: bus width is 4.
  *  3: bus width is 8.
+ *  4: bus width is 16.
  */
 #define PARL_IO_RX_BUS_WID_SEL    0x00000007U
 #define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
@@ -159,6 +160,7 @@ extern "C" {
  *  1: bus width is 2.
  *  2: bus width is 4.
  *  3: bus width is 8.
+ *  4: bus width is 16.
  */
 #define PARL_IO_TX_BUS_WID_SEL    0x00000007U
 #define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)

components/soc/esp32s31/register/soc/parl_io_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -72,6 +72,7 @@ typedef union {
          *  1: bus width is 2.
          *  2: bus width is 4.
          *  3: bus width is 8.
+         *  4: bus width is 16.
          */
         uint32_t rx_bus_wid_sel:3;
     };
@@ -146,6 +147,7 @@ typedef union {
          *  1: bus width is 2.
          *  2: bus width is 4.
          *  3: bus width is 8.
+         *  4: bus width is 16.
          */
         uint32_t tx_bus_wid_sel:3;
     };
@@ -487,7 +489,7 @@ typedef union {
 } parl_io_version_reg_t;
 
 
-typedef struct {
+typedef struct parl_io_dev_t {
     volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
     volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
     volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
@@ -514,6 +516,8 @@ typedef struct {
     volatile parl_io_version_reg_t version;
 } parl_io_dev_t;
 
+extern parl_io_dev_t PARL_IO;
+
 
 #ifndef __cplusplus
 _Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");