From 4c86e76b8eac9fd513f6b7ef35feec6d6258ce80 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Fri, 15 May 2026 16:47:47 +0800 Subject: [PATCH] fix(parlio): fix max valid delay value --- components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h | 2 +- components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h | 2 +- components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h b/components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h index 67d15be0858..625682370ce 100644 --- a/components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h +++ b/components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h @@ -42,7 +42,7 @@ #define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL) #define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal -#define PARLIO_LL_TX_VALID_MAX_DELAY 32767 +#define PARLIO_LL_TX_VALID_MAX_DELAY 65535 #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h b/components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h index e48340ad3c7..cda1ef16e7b 100644 --- a/components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h +++ b/components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h @@ -42,7 +42,7 @@ #define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL) #define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal -#define PARLIO_LL_TX_VALID_MAX_DELAY 32767 +#define PARLIO_LL_TX_VALID_MAX_DELAY 65535 #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h b/components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h index 4017ea6623d..b7d48178258 100644 --- a/components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h +++ b/components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h @@ -49,7 +49,7 @@ #define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 15 // TXD[15] can be used as clock gate signal #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 -#define PARLIO_LL_TX_VALID_MAX_DELAY 32767 +#define PARLIO_LL_TX_VALID_MAX_DELAY 65535 #define PARLIO_LL_SUPPORT_TX_EOF_FROM_DMA 1 // Support to treat DMA EOF as TX unit EOF #endif @@ -136,6 +136,7 @@ static inline void _parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clo HAL_ASSERT(false); break; } + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = (src == PARLIO_CLK_SRC_EXTERNAL); HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_src_sel = clk_sel; } @@ -197,7 +198,6 @@ __attribute__((always_inline)) static inline void _parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en) { (void)dev; - LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = en; HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_en = en; } @@ -486,6 +486,7 @@ static inline void _parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clo HAL_ASSERT(false); break; } + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = (src == PARLIO_CLK_SRC_EXTERNAL); HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_src_sel = clk_sel; } @@ -548,7 +549,6 @@ __attribute__((always_inline)) static inline void _parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en) { (void)dev; - LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = en; HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_en = en; }