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Merge branch 'feat/support_p4_clk_tree_ref_cnt_v6.0' into 'release/v6.0'

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feat(esp_hw_support): support clock tree management for esp32p4 (v6.0)

See merge request espressif/esp-idf!46444
This commit is contained in:
Jiang Jiang Jian
2026-03-20 10:16:53 +08:00
parent 6ce33369f1 c6d1bd0f85
commit 779fd7a52c
18 changed files with 509 additions and 42 deletions
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components/soc/esp32p4/include/soc/clk_tree_defs.h
+1 -1
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@@ -166,8 +166,8 @@ typedef enum {
SOC_MOD_CLK_PLL_F25M, /*!< PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz */
SOC_MOD_CLK_PLL_F50M, /*!< PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + default divider 6), its default frequency is 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + default divider 3), its default frequency is 160MHz */
SOC_MOD_CLK_PLL_F120M, /*!< PLL_F120M_CLK is derived from SPLL (clock gating + default divider 4), its default frequency is 120MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + default divider 3), its default frequency is 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from SPLL (clock gating + default divider 2), its default frequency is 240MHz */
SOC_MOD_CLK_CPLL, /*!< CPLL is from 40MHz XTAL oscillator frequency multipliers */
SOC_MOD_CLK_SPLL, /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 480MHz */
components/soc/esp32p4/include/soc/reset_reasons.h
+1 -1
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@@ -36,7 +36,7 @@ typedef enum {
RESET_REASON_CPU_MWDT = 0x0B, // MWDT HP CPU 0/1 reset
RESET_REASON_CPU_SW = 0x0C, // Software resets HP CPU 0/1
RESET_REASON_CPU0_SW = 0x0C, // Software resets HP CPU 0, kept to be compatible with older chips
RESET_REASON_CPU_RWDT = 0x0D, // RWDT resets digital core
RESET_REASON_CPU_RWDT = 0x0D, // RWDT resets HP CPU 0/1
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RWDT = 0x10, // RWDT system reset
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module