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fix(hal): fix LP WDT stage timeout and reset configuration for ESP32S31

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This commit is contained in:
Marius Vikhammer
2026-04-28 12:10:23 +08:00
parent e17f46e240
commit 76983e48fc
8 changed files with 43 additions and 32 deletions
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components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_rtc_wdt.c
+16 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -126,14 +126,27 @@ TEST_CASE("RTC WDT triggers interrupt at expected time for all stages", "[rtc_wd
esp_intr_free(ret_handle);
#endif
/* Check that wdt interrupts for various stages occurred within a reasonable window (WDT_TIMEOUT_MARGIN_MS) */
/* Check that wdt interrupts for various stages occurred within a reasonable window (WDT_TIMEOUT_MARGIN_MS)
* Do not abort on first failure: print all stage results and report aggregate failure at the end so later
* stage timings can be inspected even if earlier stages are out of tolerance.
*/
int64_t elapsed_us[4], expected_us[4];
int failures = 0;
for (stage = WDT_STAGE0; stage <= WDT_STAGE3; stage++) {
elapsed_us[stage] = wdt_stage_int_time[stage] - wdt_start_time[stage];
expected_us[stage] = wdt_stage_timeout_ms[stage] * 1000;
printf("Stage-%d: interrupt time %lld us, start time %lld us\n", stage, wdt_stage_int_time[stage], wdt_start_time[stage]);
printf("Stage-%d: expected %lld us, elapsed %lld us\n", stage, expected_us[stage], elapsed_us[stage]);
TEST_ASSERT_INT_WITHIN(WDT_TIMEOUT_MARGIN_MS(wdt_stage_timeout_ms[stage]) * 1000, expected_us[stage], elapsed_us[stage]);
int64_t margin_us = (int64_t)WDT_TIMEOUT_MARGIN_MS(wdt_stage_timeout_ms[stage]) * 1000;
if (llabs(expected_us[stage] - elapsed_us[stage]) > margin_us) {
failures++;
printf("Stage-%d: OUT OF TOLERANCE (expected %lld +/- %lld, got %lld)\n", stage, expected_us[stage], margin_us, elapsed_us[stage]);
} else {
printf("Stage-%d: within tolerance\n", stage);
}
}
if (failures) {
TEST_FAIL_MESSAGE("One or more WDT stages timed out outside allowed margin. See logs for details.");
}
}