Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-03 03:31:41 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(hal): fix LP WDT stage timeout and reset configuration for ESP32S31

Browse Source
This commit is contained in:
Marius Vikhammer
2026-04-28 12:10:23 +08:00
parent e17f46e240
commit 76983e48fc
8 changed files with 43 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hal_wdt/esp32s31/include/hal/rwdt_ll.h
+9 -16
View File
@@ -21,8 +21,6 @@ extern "C" {
#include "esp32s31/rom/ets_sys.h"
// TODO: ["ESP32S31"] IDF-14636
/* The value that needs to be written to RTC_WDT_WPROTECT_REG to write-enable the wdt registers */
#define RTC_WDT_WKEY_VALUE 0x50D83AA1
/* The value that needs to be written to RTC_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
@@ -238,28 +236,23 @@ FORCE_INLINE_ATTR void rwdt_ll_set_pause_in_sleep_en(rwdt_dev_t *hw, bool enable
}
/**
* @brief Enable/Disable chip reset on RWDT timeout.
*
* A chip reset also resets the analog portion of the chip. It will appear as a
* POWERON reset rather than an RTC reset.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable, false to disable.
* @brief No register for setting chip_reset_en, we keep an empty function to
* provide the same HAL interface as other targets.
*/
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rwdt_dev_t *hw, bool enable)
{
// hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
(void)hw;
(void)enable;
}
/**
* @brief Set width of chip reset signal
*
* @param hw Start address of the peripheral registers.
* @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
* @brief No register for setting reset width, we keep an empty function to
* provide the same HAL interface as other targets.
*/
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rwdt_dev_t *hw, uint32_t width)
{
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
(void)hw;
(void)width;
}
/**
@@ -271,7 +264,7 @@ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rwdt_dev_t *hw, uint32_t wid
*/
FORCE_INLINE_ATTR void rwdt_ll_feed(rwdt_dev_t *hw)
{
// hw->feed.rtc_wdt_feed = 1;
hw->feed.feed = 1;
}
/**
components/esp_hal_wdt/esp32s31/rom.wdt.ld
+3 -3
View File
@@ -18,9 +18,9 @@
***************************************/
/* Functions */
wdt_hal_init = 0x2f800368;
wdt_hal_deinit = 0x2f80036c;
wdt_hal_config_stage = 0x2f800370;
rom_wdt_hal_init = 0x2f800368;
rom_wdt_hal_deinit = 0x2f80036c;
rom_wdt_hal_config_stage = 0x2f800370;
wdt_hal_write_protect_disable = 0x2f800374;
wdt_hal_write_protect_enable = 0x2f800378;
wdt_hal_enable = 0x2f80037c;
components/esp_hal_wdt/rom_patch.c
+5 -10
View File
@@ -5,11 +5,7 @@
*/
#include <stddef.h>
#include "hal/config.h"
#include "soc/soc_caps.h"
#include "soc/chip_revision.h"
#include "esp_rom_caps.h"
#include "hal/efuse_hal.h"
#include "hal/mwdt_periph.h"
#include "hal/wdt_hal.h"
@@ -41,16 +37,15 @@ void wdt_hal_deinit(wdt_hal_context_t *hal)
rom_wdt_hal_deinit(hal);
}
#if SOC_IS(ESP32P4) && (HAL_CONFIG(CHIP_SUPPORT_MIN_REV) <= 301)
#if ESP_ROM_WDT_CONFIG_STAGE_PATCH
extern void rom_wdt_hal_config_stage(wdt_hal_context_t *hal, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior);
/* rwdt_ll_config_stage is implemented erroneously in ESP32P4 rom code, TODO: PM-654*/
void wdt_hal_config_stage(wdt_hal_context_t *hal, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
{
if ((hal->inst == WDT_RWDT && stage == WDT_STAGE0) && !ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 302)) {
timeout_ticks = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
}
rom_wdt_hal_config_stage(hal, stage, timeout_ticks, behavior);
if (hal->inst == WDT_RWDT) {
rwdt_ll_config_stage(hal->rwdt_dev, stage, timeout_ticks, behavior);
}
}
#endif // SOC_IS(ESP32P4)
#endif // ESP_ROM_WDT_CONFIG_STAGE_PATCH
#endif // ESP_ROM_WDT_INIT_PATCH