From 368900ceddcaf517bf61042bd47907c03b0a7895 Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 2 Jul 2026 16:58:52 +0800 Subject: [PATCH] refactor(mwdt): move sleep retention config into system layer Move MWDT retention descriptors out of esp_hal_wdt and into esp_system so the backup policy lives with the watchdog users, while keeping the per-chip retention sources under the existing port/soc target directories. --- components/esp_hal_wdt/esp32c5/mwdt_periph.c | 25 ------ components/esp_hal_wdt/esp32c6/mwdt_periph.c | 25 ------ components/esp_hal_wdt/esp32c61/mwdt_periph.c | 25 ------ components/esp_hal_wdt/esp32h2/mwdt_periph.c | 25 ------ components/esp_hal_wdt/esp32h21/mwdt_periph.c | 27 ------- components/esp_hal_wdt/esp32h4/mwdt_periph.c | 29 ------- components/esp_hal_wdt/esp32p4/mwdt_periph.c | 25 ------ components/esp_hal_wdt/esp32s31/mwdt_periph.c | 29 ------- .../esp_hal_wdt/include/hal/mwdt_periph.h | 15 +--- components/esp_system/CMakeLists.txt | 3 + components/esp_system/int_wdt.c | 6 +- .../port/include/private/mwdt_priv.h | 31 +++++++ .../port/soc/esp32c5/mwdt_retention.c | 81 +++++++++++++++++++ .../port/soc/esp32c6/mwdt_retention.c | 81 +++++++++++++++++++ .../port/soc/esp32c61/mwdt_retention.c | 81 +++++++++++++++++++ .../port/soc/esp32h2/mwdt_retention.c | 81 +++++++++++++++++++ .../port/soc/esp32h21/mwdt_retention.c | 81 +++++++++++++++++++ .../port/soc/esp32h4/mwdt_retention.c | 81 +++++++++++++++++++ .../port/soc/esp32p4/mwdt_retention.c | 81 +++++++++++++++++++ .../port/soc/esp32s31/mwdt_retention.c | 81 +++++++++++++++++++ .../task_wdt/task_wdt_impl_timergroup.c | 6 +- 21 files changed, 689 insertions(+), 230 deletions(-) create mode 100644 components/esp_system/port/include/private/mwdt_priv.h create mode 100644 components/esp_system/port/soc/esp32c5/mwdt_retention.c create mode 100644 components/esp_system/port/soc/esp32c6/mwdt_retention.c create mode 100644 components/esp_system/port/soc/esp32c61/mwdt_retention.c create mode 100644 components/esp_system/port/soc/esp32h2/mwdt_retention.c create mode 100644 components/esp_system/port/soc/esp32h21/mwdt_retention.c create mode 100644 components/esp_system/port/soc/esp32h4/mwdt_retention.c create mode 100644 components/esp_system/port/soc/esp32p4/mwdt_retention.c create mode 100644 components/esp_system/port/soc/esp32s31/mwdt_retention.c diff --git a/components/esp_hal_wdt/esp32c5/mwdt_periph.c b/components/esp_hal_wdt/esp32c5/mwdt_periph.c index 33c52fafad7..c81ca5756a1 100644 --- a/components/esp_hal_wdt/esp32c5/mwdt_periph.c +++ b/components/esp_hal_wdt/esp32c5/mwdt_periph.c @@ -6,28 +6,3 @@ #include "hal/mwdt_periph.h" #include "hal/mwdt_ll.h" - -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, -}; diff --git a/components/esp_hal_wdt/esp32c6/mwdt_periph.c b/components/esp_hal_wdt/esp32c6/mwdt_periph.c index 33c52fafad7..c81ca5756a1 100644 --- a/components/esp_hal_wdt/esp32c6/mwdt_periph.c +++ b/components/esp_hal_wdt/esp32c6/mwdt_periph.c @@ -6,28 +6,3 @@ #include "hal/mwdt_periph.h" #include "hal/mwdt_ll.h" - -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, -}; diff --git a/components/esp_hal_wdt/esp32c61/mwdt_periph.c b/components/esp_hal_wdt/esp32c61/mwdt_periph.c index 33c52fafad7..c81ca5756a1 100644 --- a/components/esp_hal_wdt/esp32c61/mwdt_periph.c +++ b/components/esp_hal_wdt/esp32c61/mwdt_periph.c @@ -6,28 +6,3 @@ #include "hal/mwdt_periph.h" #include "hal/mwdt_ll.h" - -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, -}; diff --git a/components/esp_hal_wdt/esp32h2/mwdt_periph.c b/components/esp_hal_wdt/esp32h2/mwdt_periph.c index 33c52fafad7..c81ca5756a1 100644 --- a/components/esp_hal_wdt/esp32h2/mwdt_periph.c +++ b/components/esp_hal_wdt/esp32h2/mwdt_periph.c @@ -6,28 +6,3 @@ #include "hal/mwdt_periph.h" #include "hal/mwdt_ll.h" - -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, -}; diff --git a/components/esp_hal_wdt/esp32h21/mwdt_periph.c b/components/esp_hal_wdt/esp32h21/mwdt_periph.c index a9d37a3609b..c81ca5756a1 100644 --- a/components/esp_hal_wdt/esp32h21/mwdt_periph.c +++ b/components/esp_hal_wdt/esp32h21/mwdt_periph.c @@ -6,30 +6,3 @@ #include "hal/mwdt_periph.h" #include "hal/mwdt_ll.h" - -#if SOC_PAU_SUPPORTED && SOC_MWDT_SUPPORT_SLEEP_RETENTION -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, -}; -#endif diff --git a/components/esp_hal_wdt/esp32h4/mwdt_periph.c b/components/esp_hal_wdt/esp32h4/mwdt_periph.c index 41e911747f2..02a29a09d2a 100644 --- a/components/esp_hal_wdt/esp32h4/mwdt_periph.c +++ b/components/esp_hal_wdt/esp32h4/mwdt_periph.c @@ -7,32 +7,3 @@ #include "hal/mwdt_periph.h" #include "hal/mwdt_ll.h" #include "soc/soc_caps.h" - -#if SOC_PAU_SUPPORTED && SOC_MWDT_SUPPORT_SLEEP_RETENTION - -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, -}; - -#endif // SOC_PAU_SUPPORTED diff --git a/components/esp_hal_wdt/esp32p4/mwdt_periph.c b/components/esp_hal_wdt/esp32p4/mwdt_periph.c index ab1601d7c26..c81ca5756a1 100644 --- a/components/esp_hal_wdt/esp32p4/mwdt_periph.c +++ b/components/esp_hal_wdt/esp32p4/mwdt_periph.c @@ -6,28 +6,3 @@ #include "hal/mwdt_periph.h" #include "hal/mwdt_ll.h" - -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0)}, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0)}, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0)}, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0)}, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0)}, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0)}, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0)}, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0)}, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0)}, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0)}, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0)}, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0)}, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, -}; diff --git a/components/esp_hal_wdt/esp32s31/mwdt_periph.c b/components/esp_hal_wdt/esp32s31/mwdt_periph.c index 09be0ba80fc..fc34c14941b 100644 --- a/components/esp_hal_wdt/esp32s31/mwdt_periph.c +++ b/components/esp_hal_wdt/esp32s31/mwdt_periph.c @@ -7,32 +7,3 @@ #include "hal/mwdt_periph.h" #include "hal/mwdt_ll.h" #include "soc/soc_caps.h" - -#if SOC_PAU_SUPPORTED && SOC_MWDT_SUPPORT_SLEEP_RETENTION - -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, -}; - -#endif // SOC_PAU_SUPPORTED diff --git a/components/esp_hal_wdt/include/hal/mwdt_periph.h b/components/esp_hal_wdt/include/hal/mwdt_periph.h index 1e46b6bff3d..b530ed5dfbd 100644 --- a/components/esp_hal_wdt/include/hal/mwdt_periph.h +++ b/components/esp_hal_wdt/include/hal/mwdt_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,10 +9,6 @@ #include #include "soc/timer_group_reg.h" #include "soc/timer_group_struct.h" -#include "soc/soc_caps.h" -#include "soc/periph_defs.h" -#include "soc/regdma.h" -#include "hal/mwdt_ll.h" /* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ #define TIMG_WDT_WKEY_VALUE 0x50D83AA1 @@ -21,15 +17,6 @@ extern "C" { #endif -#if SOC_MWDT_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED -typedef struct { - const regdma_entries_config_t *link_list; - uint32_t link_num; -} tg_reg_ctx_link_t; - -extern const tg_reg_ctx_link_t tg_wdt_regs_retention[TIMG_LL_GET(INST_NUM)]; -#endif // SOC_MWDT_SUPPORT_SLEEP_RETENTION - #ifdef __cplusplus } #endif diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index bcaba1f6db3..5df2ca9d643 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -62,6 +62,9 @@ else() endif() if(CONFIG_SOC_WDT_SUPPORTED) list(APPEND srcs "int_wdt.c") + if(CONFIG_SOC_PAU_SUPPORTED) + list(APPEND srcs "port/soc/${target}/mwdt_retention.c") + endif() endif() if(CONFIG_SOC_XT_WDT_SUPPORTED) list(APPEND srcs "xt_wdt.c") diff --git a/components/esp_system/int_wdt.c b/components/esp_system/int_wdt.c index 96154553a37..8df87b8d095 100644 --- a/components/esp_system/int_wdt.c +++ b/components/esp_system/int_wdt.c @@ -9,7 +9,6 @@ #include #include "sdkconfig.h" #include "soc/soc_caps.h" -#include "hal/mwdt_periph.h" #include "hal/wdt_hal.h" #include "soc/system_intr.h" #include "freertos/FreeRTOS.h" @@ -24,6 +23,7 @@ #include "esp_freertos_hooks.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_int_wdt.h" +#include "mwdt_priv.h" #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_MWDT_SUPPORT_SLEEP_RETENTION #include "esp_private/sleep_retention.h" @@ -58,8 +58,8 @@ ESP_LOG_ATTR_TAG(TAG, "int_wdt"); static esp_err_t sleep_int_wdt_retention_init(void *arg) { uint32_t group_id = *(uint32_t *)arg; - esp_err_t err = sleep_retention_entries_create(tg_wdt_regs_retention[group_id].link_list, - tg_wdt_regs_retention[group_id].link_num, + esp_err_t err = sleep_retention_entries_create(mwdt_reg_retention_info[group_id].regdma_entry_array, + mwdt_reg_retention_info[group_id].array_size, REGDMA_LINK_PRI_SYS_PERIPH_LOW, (group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT); if (err == ESP_OK) { diff --git a/components/esp_system/port/include/private/mwdt_priv.h b/components/esp_system/port/include/private/mwdt_priv.h new file mode 100644 index 00000000000..e268ab6e180 --- /dev/null +++ b/components/esp_system/port/include/private/mwdt_priv.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc_caps.h" +#include "hal/mwdt_ll.h" +#if SOC_PAU_SUPPORTED +#include "soc/regdma.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_PAU_SUPPORTED +typedef struct { + const regdma_entries_config_t *regdma_entry_array; + uint32_t array_size; +} mwdt_reg_retention_info_t; + +extern const mwdt_reg_retention_info_t mwdt_reg_retention_info[TIMG_LL_GET(INST_NUM)]; +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_system/port/soc/esp32c5/mwdt_retention.c b/components/esp_system/port/soc/esp32c5/mwdt_retention.c new file mode 100644 index 00000000000..97755bbf7f0 --- /dev/null +++ b/components/esp_system/port/soc/esp32c5/mwdt_retention.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mwdt_priv.h" +#include "hal/mwdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), + TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), + TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), + TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), + TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), + TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x04), + TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mwdt_reg_retention_info_t mwdt_reg_retention_info[2] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/esp_system/port/soc/esp32c6/mwdt_retention.c b/components/esp_system/port/soc/esp32c6/mwdt_retention.c new file mode 100644 index 00000000000..97755bbf7f0 --- /dev/null +++ b/components/esp_system/port/soc/esp32c6/mwdt_retention.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mwdt_priv.h" +#include "hal/mwdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), + TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), + TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), + TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), + TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), + TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x04), + TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mwdt_reg_retention_info_t mwdt_reg_retention_info[2] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/esp_system/port/soc/esp32c61/mwdt_retention.c b/components/esp_system/port/soc/esp32c61/mwdt_retention.c new file mode 100644 index 00000000000..97755bbf7f0 --- /dev/null +++ b/components/esp_system/port/soc/esp32c61/mwdt_retention.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mwdt_priv.h" +#include "hal/mwdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), + TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), + TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), + TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), + TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), + TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x04), + TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mwdt_reg_retention_info_t mwdt_reg_retention_info[2] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/esp_system/port/soc/esp32h2/mwdt_retention.c b/components/esp_system/port/soc/esp32h2/mwdt_retention.c new file mode 100644 index 00000000000..97755bbf7f0 --- /dev/null +++ b/components/esp_system/port/soc/esp32h2/mwdt_retention.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mwdt_priv.h" +#include "hal/mwdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), + TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), + TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), + TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), + TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), + TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x04), + TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mwdt_reg_retention_info_t mwdt_reg_retention_info[2] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/esp_system/port/soc/esp32h21/mwdt_retention.c b/components/esp_system/port/soc/esp32h21/mwdt_retention.c new file mode 100644 index 00000000000..ad107211f4f --- /dev/null +++ b/components/esp_system/port/soc/esp32h21/mwdt_retention.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mwdt_priv.h" +#include "hal/mwdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), + TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), + TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) + }, + [4] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), + TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), + .owner = ENTRY(0) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) + }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), + TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), + .owner = ENTRY(0) + }, + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), + TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) + }, + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x04), + TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) + }, +}; + +const mwdt_reg_retention_info_t mwdt_reg_retention_info[2] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/esp_system/port/soc/esp32h4/mwdt_retention.c b/components/esp_system/port/soc/esp32h4/mwdt_retention.c new file mode 100644 index 00000000000..97755bbf7f0 --- /dev/null +++ b/components/esp_system/port/soc/esp32h4/mwdt_retention.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mwdt_priv.h" +#include "hal/mwdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), + TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), + TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), + TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), + TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), + TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x04), + TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mwdt_reg_retention_info_t mwdt_reg_retention_info[2] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/esp_system/port/soc/esp32p4/mwdt_retention.c b/components/esp_system/port/soc/esp32p4/mwdt_retention.c new file mode 100644 index 00000000000..ad107211f4f --- /dev/null +++ b/components/esp_system/port/soc/esp32p4/mwdt_retention.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mwdt_priv.h" +#include "hal/mwdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), + TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), + TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) + }, + [4] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), + TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), + .owner = ENTRY(0) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) + }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), + TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), + .owner = ENTRY(0) + }, + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), + TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) + }, + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x04), + TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) + }, +}; + +const mwdt_reg_retention_info_t mwdt_reg_retention_info[2] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/esp_system/port/soc/esp32s31/mwdt_retention.c b/components/esp_system/port/soc/esp32s31/mwdt_retention.c new file mode 100644 index 00000000000..dbe19a8de47 --- /dev/null +++ b/components/esp_system/port/soc/esp32s31/mwdt_retention.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mwdt_priv.h" +#include "hal/mwdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), + TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), + TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), + TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), + TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), + TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), + TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), + TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x04), + TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [5] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), + TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mwdt_reg_retention_info_t mwdt_reg_retention_info[2] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c index 26b6beb636d..4ac5af54369 100644 --- a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c +++ b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c @@ -8,7 +8,6 @@ #include #include #include "sdkconfig.h" -#include "hal/mwdt_periph.h" #include "hal/wdt_hal.h" #include "soc/system_intr.h" #include "esp_check.h" @@ -16,6 +15,7 @@ #include "esp_attr.h" #include "esp_intr_alloc.h" #include "esp_log.h" +#include "mwdt_priv.h" #include "esp_private/system_internal.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_task_wdt_impl.h" @@ -56,8 +56,8 @@ ESP_LOG_ATTR_TAG(TAG, "task_wdt"); static esp_err_t sleep_task_wdt_retention_init(void *arg) { uint32_t group_id = *(uint32_t *)arg; - esp_err_t err = sleep_retention_entries_create(tg_wdt_regs_retention[group_id].link_list, - tg_wdt_regs_retention[group_id].link_num, + esp_err_t err = sleep_retention_entries_create(mwdt_reg_retention_info[group_id].regdma_entry_array, + mwdt_reg_retention_info[group_id].array_size, REGDMA_LINK_PRI_SYS_PERIPH_LOW, (group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_WDT : SLEEP_RETENTION_MODULE_TG1_WDT); if (err == ESP_OK) {