From 7666c7b0f612943b9a72ccc76e23300122fc5e2b Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 1 Aug 2025 11:39:36 +0800 Subject: [PATCH] feat(i2s): add PLL240M clock source on S3 and C6 Closes https://github.com/espressif/esp-idf/issues/17056 --- components/hal/esp32c6/include/hal/i2s_ll.h | 6 ++++++ components/hal/esp32s3/include/hal/i2s_ll.h | 6 ++++++ components/soc/esp32c6/include/soc/clk_tree_defs.h | 3 ++- components/soc/esp32s3/include/soc/clk_tree_defs.h | 7 +++++-- 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/components/hal/esp32c6/include/hal/i2s_ll.h b/components/hal/esp32c6/include/hal/i2s_ll.h index 2e739d86d5d..e26ba9dccea 100644 --- a/components/hal/esp32c6/include/hal/i2s_ll.h +++ b/components/hal/esp32c6/include/hal/i2s_ll.h @@ -245,6 +245,9 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) case I2S_CLK_SRC_XTAL: PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0; break; + case I2S_CLK_SRC_PLL_240M: + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 1; + break; case I2S_CLK_SRC_PLL_160M: PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 2; break; @@ -271,6 +274,9 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) case I2S_CLK_SRC_XTAL: PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0; break; + case I2S_CLK_SRC_PLL_240M: + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 1; + break; case I2S_CLK_SRC_PLL_160M: PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 2; break; diff --git a/components/hal/esp32s3/include/hal/i2s_ll.h b/components/hal/esp32s3/include/hal/i2s_ll.h index f66575ea0b3..01c47edd65b 100644 --- a/components/hal/esp32s3/include/hal/i2s_ll.h +++ b/components/hal/esp32s3/include/hal/i2s_ll.h @@ -233,6 +233,9 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) case I2S_CLK_SRC_XTAL: hw->tx_clkm_conf.tx_clk_sel = 0; break; + case I2S_CLK_SRC_PLL_240M: + hw->tx_clkm_conf.tx_clk_sel = 1; + break; case I2S_CLK_SRC_PLL_160M: hw->tx_clkm_conf.tx_clk_sel = 2; break; @@ -258,6 +261,9 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) case I2S_CLK_SRC_XTAL: hw->rx_clkm_conf.rx_clk_sel = 0; break; + case I2S_CLK_SRC_PLL_240M: + hw->rx_clkm_conf.rx_clk_sel = 1; + break; case I2S_CLK_SRC_PLL_160M: hw->rx_clkm_conf.rx_clk_sel = 2; break; diff --git a/components/soc/esp32c6/include/soc/clk_tree_defs.h b/components/soc/esp32c6/include/soc/clk_tree_defs.h index a63e2fbc099..89cb807203b 100644 --- a/components/soc/esp32c6/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c6/include/soc/clk_tree_defs.h @@ -308,13 +308,14 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of I2S */ -#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F240M, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} /** * @brief I2S clock source enum */ typedef enum { I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ + I2S_CLK_SRC_PLL_240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ diff --git a/components/soc/esp32s3/include/soc/clk_tree_defs.h b/components/soc/esp32s3/include/soc/clk_tree_defs.h index 2febc75bb12..de54c62bccd 100644 --- a/components/soc/esp32s3/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s3/include/soc/clk_tree_defs.h @@ -311,16 +311,19 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of I2S */ -#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F240M, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} /** * @brief I2S clock source enum */ typedef enum { I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ + I2S_CLK_SRC_PLL_240M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the source clock. + It is default to 240MHz while PLL is 480MHz, + but it will be 160MHz if PLL is 320MHz */ I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ + I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ } soc_periph_i2s_clk_src_t; /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////