Merge branch 'fix/spi_enable_p4_c5_test_v5.3' into 'release/v5.3'

fix(driver_spi): enable p4 test (v5.3)

See merge request espressif/esp-idf!34281

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -19,7 +19,7 @@ extern "C" {
  *
  * 2) External 40MHz Crystal Clock: XTAL
  *
- * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.

components/soc/esp32h2/include/soc/clk_tree_defs.h

@@ -19,7 +19,7 @@ extern "C" {
  *
  * 2) External 32MHz Crystal Clock: XTAL
  *
- * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as SOSC in TRM or reg. description)
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as SOSC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.
@@ -332,7 +332,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of SPI
  */
-#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M}
+#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST}
 
 /**
  * @brief Type of SPI clock source.

components/soc/esp32p4/spi_periph.c

@@ -73,7 +73,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spiclk_in = SPI3_CK_PAD_IN_IDX,
         .spid_out = SPI3_D_PAD_OUT_IDX,
         .spiq_out = SPI3_QO_PAD_OUT_IDX,
-        //SPI3 doesn't have wp and hd signals
         .spiwp_out = SPI3_WP_PAD_OUT_IDX,
         .spihd_out = SPI3_HOLD_PAD_OUT_IDX,
         .spid_in = SPI3_D_PAD_IN_IDX,