Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(esp_rom): implement cache writeback related apis in iram

Browse Source 
avoid critical issues caused by manual cache writeback and conflicting
writes. The issue exist on chips after esp32p4
This commit is contained in:
wanglei
2026-05-20 17:43:43 +08:00
committed by BOT
parent 8609249317
commit 751a75a982
21 changed files with 186 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_rom/esp32s31/Kconfig.soc_caps.in
+4
View File
@@ -94,3 +94,7 @@ config ESP_ROM_PRINTS_LOCKUP_STATUS
config ESP_ROM_BOOTLOADER_OFFSET_FLASH
hex
default 0x2000
config ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_MAP
bool
default y
components/esp_rom/esp32s31/esp_rom_caps.h
+1
View File
@@ -30,3 +30,4 @@
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_PRINTS_LOCKUP_STATUS (1) // ROM bootloader already prints CPU lockup diagnostic status
#define ESP_ROM_BOOTLOADER_OFFSET_FLASH (0x2000) // Bootloader offset in flash determined by the ROM bootloader
#define ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_MAP (1) // ROM cache writeback related needs patch to avoid sync loss, need map parameter
components/esp_rom/esp32s31/ld/esp32s31.rom.ld
+4 -4
View File
@@ -213,12 +213,12 @@ ROM_Boot_Cache_Init = 0x2f8005e0;
Cache_Sync_Addr = 0x2f8005e4;
Cache_Invalidate_Addr = 0x2f8005e8;
Cache_Clean_Addr = 0x2f8005ec;
Cache_WriteBack_Addr = 0x2f8005f0;
Cache_WriteBack_Invalidate_Addr = 0x2f8005f4;
PROVIDE( Cache_WriteBack_Addr = 0x2f8005f0 );
PROVIDE( Cache_WriteBack_Invalidate_Addr = 0x2f8005f4 );
Cache_Invalidate_All = 0x2f8005f8;
Cache_Clean_All = 0x2f8005fc;
Cache_WriteBack_All = 0x2f800600;
Cache_WriteBack_Invalidate_All = 0x2f800604;
PROVIDE( Cache_WriteBack_All = 0x2f800600 );
PROVIDE( Cache_WriteBack_Invalidate_All = 0x2f800604 );
Cache_Mask_All = 0x2f800608;
Cache_Suspend_L1_CORE0_ICache_Autoload = 0x2f80060c;
Cache_Resume_L1_CORE0_ICache_Autoload = 0x2f800610;