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refactor(lcdcam): move shared core clock setup to drivers

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Configure the shared LCDCAM core clock through guarded LCD and CAM LL APIs,
and unify LCD functional clock LL calls around group IDs across supported targets.

Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
morris
2026-07-27 18:40:04 +08:00
co-authored by Cursor
parent 8550997ada
commit 74d9e99d91
9 changed files with 183 additions and 52 deletions
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components/esp_hal_cam/esp32s31/include/hal/cam_ll.h
+58 -4
View File
@@ -29,7 +29,7 @@ extern "C" {
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void cam_ll_enable_bus_clock(int group_id, bool en)
static inline void _cam_ll_enable_bus_clock(int group_id, bool en)
{
(void)group_id;
// the core clock is a shared clock for both LCD and CAM
@@ -42,7 +42,7 @@ static inline void cam_ll_enable_bus_clock(int group_id, bool en)
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define cam_ll_enable_bus_clock(...) do { \
(void)__DECLARE_RCC_RC_ATOMIC_ENV; \
cam_ll_enable_bus_clock(__VA_ARGS__); \
_cam_ll_enable_bus_clock(__VA_ARGS__); \
} while(0)
/**
@@ -50,7 +50,7 @@ static inline void cam_ll_enable_bus_clock(int group_id, bool en)
*
* @param group_id Group ID
*/
static inline void cam_ll_reset_register(int group_id)
static inline void _cam_ll_reset_register(int group_id)
{
(void)group_id;
HP_SYS_CLKRST.lcdcam_ctrl0.reg_lcdcam_apb_rst_en = 1;
@@ -63,7 +63,61 @@ static inline void cam_ll_reset_register(int group_id)
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define cam_ll_reset_register(...) do { \
(void)__DECLARE_RCC_RC_ATOMIC_ENV; \
cam_ll_reset_register(__VA_ARGS__); \
_cam_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* @brief Select shared core clock source for LCDCAM peripheral
*
* @param group_id Group ID
* @param src Core clock source
*/
static inline void _cam_ll_select_core_clk_src(int group_id, soc_periph_cam_core_clk_src_t src)
{
(void)group_id;
switch (src) {
case CAM_CORE_CLK_SRC_XTAL:
HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 0;
break;
case CAM_CORE_CLK_SRC_PLL120M:
HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 1;
break;
case CAM_CORE_CLK_SRC_APLL:
HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 2;
break;
default:
HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 3;
break;
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define cam_ll_select_core_clk_src(...) do { \
(void)__DECLARE_RCC_RC_ATOMIC_ENV; \
_cam_ll_select_core_clk_src(__VA_ARGS__); \
} while(0)
/**
* @brief Set shared core clock divider for LCDCAM peripheral
*
* @param group_id Group ID
* @param div_num Integer part of the divider
* @param div_a Denominator of the fractional part; set to 0 to disable fractional division
* @param div_b Numerator of the fractional part; set to 0 to disable fractional division
*/
static inline void _cam_ll_set_core_clock_divider(int group_id, uint32_t div_num, uint32_t div_a, uint32_t div_b)
{
(void)group_id;
HAL_ASSERT(div_num > 0 && div_num <= CAM_LL_CLK_FRAC_DIV_N_MAX);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0, reg_lcdcam_clk_div_num, div_num - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0, reg_lcdcam_clk_div_denominator, div_a);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0, reg_lcdcam_clk_div_numerator, div_b);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define cam_ll_set_core_clock_divider(...) do { \
(void)__DECLARE_RCC_RC_ATOMIC_ENV; \
_cam_ll_set_core_clock_divider(__VA_ARGS__); \
} while(0)
/**