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Merge branch 'feat/esp_idf_h21_clock_output_support' into 'master'

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feat(esp_hw_support): support clock output in esp32h21

Closes PM-785 and IDF-11582

See merge request espressif/esp-idf!49393
This commit is contained in:
He Binglin
2026-06-09 15:26:34 +08:00
parent 19287f5f0c eb6bb0acf0
commit 74c3a56614
7 changed files with 150 additions and 16 deletions
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components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+12
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@@ -471,6 +471,18 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
config SOC_CLOCKOUT_HAS_SOURCE_GATE
bool
default y
config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_SDM_SUPPORT_SLEEP_RETENTION
bool
default y
components/soc/esp32h21/include/soc/clk_tree_defs.h
+16 -10
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@@ -431,17 +431,23 @@ typedef enum {
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
/**
* @brief Clock output signal ID
*/
typedef enum {
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
CLKOUT_SIG_APB = 18, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_INVALID = 0xFF,
CLKOUT_SIG_MODEM_32M = 0x0, /*!< 32MHz clock for modem (clk8M) */
CLKOUT_SIG_MODEM_16M = 0x1, /*!< 16MHz clock for modem (clk16) */
CLKOUT_SIG_MODEM_8M = 0x2, /*!< 8MHz clock for modem (clk32) */
CLKOUT_SIG_XTAL = 0x6, /*!< 32MHz CPU debug mode clock */
CLKOUT_SIG_RTC_FAST = 0xA, /*!< RTC fast clock from LP system */
CLKOUT_SIG_CPU = 0xB, /*!< CPU clock */
CLKOUT_SIG_AHB = 0xC, /*!< AHB clock */
CLKOUT_SIG_APB = 0xD, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 0x10, /*!< 32KHz external crystal clock */
CLKOUT_SIG_EXT32K = 0x11, /*!< 32KHz external slow clock input */
CLKOUT_SIG_RC_FAST = 0x12, /*!< 20MHz FOSC clock (RTC fast clock) */
CLKOUT_SIG_RC_SLOW = 0x13, /*!< 600KHz SOSC clock (RTC slow clock) */
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
components/soc/esp32h21/include/soc/soc_caps.h
+3 -3
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@@ -216,9 +216,9 @@
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// The Clock Out signal is route to the pin by GPIO matrix
// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
// #define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
// #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1