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refactor(apll): move the apll soc caps to clk_tree_ll

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laokaiyao
2023-09-28 15:03:27 +08:00
parent 0b0f25c30d
commit 72a0746e62
30 changed files with 430 additions and 312 deletions
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components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -1123,6 +1123,10 @@ config SOC_PM_PAU_LINK_NUM
int
default 4
config SOC_SYS_DIGI_CLKRST_REG_SHARED
bool
default y
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
default n
components/soc/esp32p4/include/soc/soc_caps.h
+2
View File
@@ -154,6 +154,7 @@
#define SOC_CPU_HAS_PMA 1
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
// TODO: IDF-5360 (Copy from esp32c3, need check)
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (4096)
@@ -513,6 +514,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
#define SOC_SYS_DIGI_CLKRST_REG_SHARED (1)
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (0)
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (0)