From 7168e2967834d361b661b6827862e07ba183a1b1 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 10 Nov 2025 17:40:49 +0800 Subject: [PATCH] fix(esp_system): fix XTAL32K power breaks ADC function on 32k XTAL clock pin --- components/esp_system/port/soc/esp32c5/clk.c | 9 +++++++++ components/esp_system/port/soc/esp32c6/clk.c | 8 ++++++++ components/esp_system/port/soc/esp32c61/clk.c | 9 +++++++++ components/esp_system/port/soc/esp32h2/clk.c | 8 ++++++++ components/esp_system/port/soc/esp32p4/clk.c | 8 ++++++++ 5 files changed, 42 insertions(+) diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 5f3d0e84b29..fb4056e08cd 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -180,6 +180,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) rtc_clk_32k_enable(false); rtc_clk_32k_disable_external(); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW), + .xpd_rc32k = 0, + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 0c25691a813..d510f956895 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -199,6 +199,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { rtc_clk_rc32k_enable(false); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW), + .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K), + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index 8e2966afbec..6ba15a6c9ab 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -159,6 +159,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) rtc_clk_32k_enable(false); rtc_clk_32k_disable_external(); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW), + .xpd_rc32k = 0, + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index 57daa142041..5372dacde73 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -197,6 +197,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { rtc_clk_rc32k_enable(false); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW), + .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K), + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index bf88f0dd6d2..6d5bf4defc1 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -203,6 +203,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { rtc_clk_rc32k_enable(false); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K), + .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K), + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup.