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feat(dsi): add timeout check for lp cmd rx

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This commit is contained in:
Chen Jichang
2026-09-02 15:16:40 +08:00
parent 0158ad3d99
commit 7133a54828
7 changed files with 47 additions and 20 deletions
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components/esp_hal_lcd/esp32p4/include/hal/mipi_dsi_host_ll.h
+12 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -665,6 +665,17 @@ static inline bool mipi_dsi_host_ll_gen_is_read_cmd_busy(dsi_host_dev_t *dev)
return dev->cmd_pkt_status.gen_rd_cmd_busy;
}
/**
* @brief Has the low-power reception timed out?
*
* @param dev Pointer to the DSI Host controller register base address
* @return True if low-power reception timed out, False otherwise
*/
static inline bool mipi_dsi_host_ll_is_lp_rx_timeout(dsi_host_dev_t *dev)
{
return dev->int_st1.to_lp_rx;
}
/**
* @brief Is the read payload FIFO of the generic interface full?
*
components/esp_hal_lcd/include/hal/mipi_dsi_hal.h
+4 -2
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@@ -104,8 +104,9 @@ void mipi_dsi_hal_host_gen_write_dcs_command(mipi_dsi_hal_context_t *hal, uint8_
* @param command_bytes Number of bytes of the command
* @param ret_param Pointer to the buffer to store the returned parameters
* @param param_buf_size Size of the buffer to store the returned parameters
* @return True if the command response is received, False if LP RX times out
*/
void mipi_dsi_hal_host_gen_read_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t vc,
bool mipi_dsi_hal_host_gen_read_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t vc,
uint32_t command, uint32_t command_bytes, void *ret_param, uint16_t param_buf_size);
/**
@@ -140,8 +141,9 @@ void mipi_dsi_hal_host_gen_write_short_packet(mipi_dsi_hal_context_t *hal, uint8
* @param header_data Data to be filled into the DSI packet header
* @param ret_buffer Pointer to the buffer to store the returned data
* @param buffer_size Size of the buffer to store the returned data
* @return True if the packet response is received, False if LP RX times out
*/
void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc,
bool mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc,
mipi_dsi_data_type_t dt, uint16_t header_data, void *ret_buffer, uint16_t buffer_size);
/**
components/esp_hal_lcd/mipi_dsi_hal.c
+23 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,6 +16,18 @@
HAL_LOG_ATTR_TAG(TAG, "dsi_hal");
static inline bool mipi_dsi_hal_host_wait_timeout(mipi_dsi_hal_context_t *hal,
bool (*condition)(mipi_dsi_host_soc_handle_t host),
bool (*timeout)(mipi_dsi_host_soc_handle_t host))
{
while (condition(hal->host)) {
if (timeout(hal->host)) {
return true;
}
}
return timeout(hal->host);
}
void mipi_dsi_hal_init(mipi_dsi_hal_context_t *hal, const mipi_dsi_hal_config_t *config)
{
hal->host = MIPI_DSI_LL_GET_HOST(config->bus_id);
@@ -203,7 +215,7 @@ void mipi_dsi_hal_host_gen_write_long_packet(mipi_dsi_hal_context_t *hal, uint8_
mipi_dsi_host_ll_gen_set_packet_header(hal->host, vc, dt, wc_msb, wc_lsb);
}
void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, uint16_t header_data, void *ret_buffer, uint16_t buffer_size)
bool mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, uint16_t header_data, void *ret_buffer, uint16_t buffer_size)
{
uint8_t *receive_buffer = (uint8_t *)ret_buffer;
// set the maximum returned data size, it should equal to the parameter size of the read command
@@ -215,9 +227,13 @@ void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_
// listen to the same virtual channel as the one sent to
mipi_dsi_host_ll_gen_set_rx_vcid(hal->host, vc);
mipi_dsi_hal_host_gen_write_short_packet(hal, vc, dt, header_data);
while (mipi_dsi_host_ll_gen_is_read_cmd_busy(hal->host));
if (mipi_dsi_hal_host_wait_timeout(hal, mipi_dsi_host_ll_gen_is_read_cmd_busy, mipi_dsi_host_ll_is_lp_rx_timeout)) {
return false;
}
// wait data to come into the fifo
while (mipi_dsi_host_ll_gen_is_read_fifo_empty(hal->host));
if (mipi_dsi_hal_host_wait_timeout(hal, mipi_dsi_host_ll_gen_is_read_fifo_empty, mipi_dsi_host_ll_is_lp_rx_timeout)) {
return false;
}
uint32_t temp = 0;
uint32_t counter = 0;
while (!mipi_dsi_host_ll_gen_is_read_fifo_empty(hal->host)) {
@@ -229,12 +245,13 @@ void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_
}
}
}
return true;
}
void mipi_dsi_hal_host_gen_read_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t vc, uint32_t command, uint32_t command_bytes, void *ret_param, uint16_t param_buf_size)
bool mipi_dsi_hal_host_gen_read_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t vc, uint32_t command, uint32_t command_bytes, void *ret_param, uint16_t param_buf_size)
{
uint16_t header_data = command & ((1U << (8 * command_bytes)) - 1);
mipi_dsi_hal_host_gen_read_short_packet(hal, vc, MIPI_DSI_DT_DCS_READ_0, header_data, ret_param, param_buf_size);
return mipi_dsi_hal_host_gen_read_short_packet(hal, vc, MIPI_DSI_DT_DCS_READ_0, header_data, ret_param, param_buf_size);
}
void mipi_dsi_hal_host_dpi_set_horizontal_timing(mipi_dsi_hal_context_t *hal, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp)