Merge branch 'feature/sram1_iram' into 'master'

system: add kconfig option for using parts of SRAM1 for IRAM

Closes IDFGH-8351 and IDF-942

See merge request espressif/esp-idf!21214

components/bootloader/subproject/main/ld/esp32/bootloader.ld

@@ -25,7 +25,7 @@ MEMORY
   */
   iram_seg (RWX) :                  org = 0x40080400, len = 0xfc00
   /* 64k at the end of DRAM, after ROM bootloader stack */
-  dram_seg (RW) :                  	org = 0x3FFF0000, len = 0x10000
+  dram_seg (RW) :                  	org = 0x3FFF0000, len = 0x6000
 }
 
 /*  Default entry point:  */

components/esp_system/ld/esp32/memory.ld.in

@@ -48,6 +48,13 @@ ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200),
 #define DRAM0_0_SEG_LEN 0x2c200
 #endif
 
+#if CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM
+#define SRAM1_IRAM_LEN 0xA000
+#else
+#define SRAM1_IRAM_LEN 0x0
+#endif
+
+
 MEMORY
 {
   /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
@@ -55,7 +62,7 @@ MEMORY
   are connected to the data port of the CPU and eg allow bytewise access. */
 
   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
-  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000
+  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000 + SRAM1_IRAM_LEN
 
 #ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Even though the segment name is iram, it is actually mapped to flash
@@ -121,8 +128,14 @@ _heap_start = 0x3FFB0000 + DRAM0_0_SEG_LEN;
 _heap_start = _heap_low_start;
 #endif
 
-/* Heap ends at top of dram0_0_seg */
+_sram1_iram_start = 0x400A0000;
+_sram1_iram_len = ( _iram_end > _sram1_iram_start) ? (_iram_end - _sram1_iram_start) : 0;
+_heap_end = ALIGN(0x40000000 - _sram1_iram_len - 3, 4);
+
+#if CONFIG_ESP32_TRACEMEM_RESERVE_DRAM != 0
 _heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
+#endif
+
 
 _data_seg_org = ORIGIN(rtc_data_seg);
 

components/esp_system/port/soc/esp32/Kconfig.memory

@@ -41,4 +41,19 @@ menu "Memory"
             This is possible due to handling of exceptions `LoadStoreError (3)` and `LoadStoreAlignmentError (9)`
             Each unaligned read/write access will incur a penalty of maximum of 167 CPU cycles.
 
+    menu "Non-backward compatible options"
+
+        config ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM
+            bool "Reserve parts of SRAM1 for app IRAM (WARNING, read help before enabling)"
+            depends on !ESP32_TRAX
+            help
+                Reserve parts of SRAM1 for app IRAM which was previously reserved for bootloader DRAM.
+                If booting an app on an older bootloader from before this option was introduced, the app may fail
+                to boot due to overlapping memory areas. If this is the case please test carefully before pushing out
+                any OTA updates.
+
+                The bootloader DRAM memory should be sufficient for any non-modified IDF bootloader.
+
+    endmenu
+
 endmenu # Memory

components/heap/port/esp32/memory_layout.c

@@ -172,7 +172,7 @@ SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace me
 SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, spi_ram);
 #endif
 
-extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end;
+extern int _data_start, _heap_start, _heap_end, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end;
 // Static data region. DRAM used by data+bss and possibly rodata
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
 
@@ -180,6 +180,11 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_d
 // ESP32 has an IRAM-only region 0x4008_0000 - 0x4009_FFFF, reserve the used part
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
 
+// If IRAM spans into SRAM1 due to CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM, reserve the corresponding part of DRAM
+#ifdef CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM
+SOC_RESERVE_MEMORY_REGION((intptr_t) &_heap_end, 0x40000000, sram1_iram);
+#endif
+
 // RTC Fast RAM region
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
 #ifdef CONFIG_ESP32_RTCDATA_IN_FAST_MEM

components/soc/esp32/include/soc/soc.h

@@ -182,7 +182,7 @@
 #define SOC_CACHE_APP_LOW       0x40078000
 #define SOC_CACHE_APP_HIGH      0x40080000
 #define SOC_IRAM_LOW            0x40080000
-#define SOC_IRAM_HIGH           0x400A0000
+#define SOC_IRAM_HIGH           0x400AA000
 #define SOC_RTC_IRAM_LOW        0x400C0000
 #define SOC_RTC_IRAM_HIGH       0x400C2000
 #define SOC_RTC_DRAM_LOW        0x3FF80000