mirror of
https://github.com/espressif/esp-idf.git
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feat(isp): added isp dvp driver
This commit is contained in:
Armando
@@ -0,0 +1,568 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp_types.h>
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#include <sys/lock.h>
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "esp_check.h"
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#include "esp_heap_caps.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/idf_additions.h"
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#include "driver/isp_types.h"
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#include "driver/gpio.h"
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#include "hal/isp_hal.h"
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#include "hal/gpio_hal.h"
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#include "hal/isp_ll.h"
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#include "hal/mipi_csi_brg_ll.h"
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#include "hal/mipi_csi_ll.h"
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#include "hal/color_hal.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/isp_private.h"
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#include "esp_private/esp_cache_private.h"
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#include "esp_private/mipi_csi_share_hw_ctrl.h"
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#include "esp_private/dw_gdma.h"
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#include "esp_cam_ctlr_types.h"
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#include "esp_cam_ctlr_interface.h"
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#include "esp_cache.h"
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#include "esp_cam_ctlr_isp_dvp.h"
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#include "../../dvp_share_ctrl.h"
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#if CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE
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#define ISP_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define ISP_DVP_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
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#endif
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typedef struct isp_dvp_controller_t {
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int id; //dvp id
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isp_fsm_t fsm; //finite state machine
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portMUX_TYPE spinlock; //spinlock
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isp_processor_t *isp_proc; //isp processor
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int in_bpp; //input data type, bit per pixel
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int out_bpp; //output data type, bit per pixel
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size_t fb_size_in_bytes; //Frame buffer size, in bytes
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esp_cam_ctlr_trans_t trans; //Saved done transaction to be given out to callers
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void *backup_buffer; //backup buffer to make csi bridge can work to avoid wrong state
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bool bk_buffer_exposed; //status of if back_buffer is exposed to users
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bool bk_buffer_dis; //allow to not malloc backup_buffer
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QueueHandle_t trans_que; //transaction queue
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esp_cam_ctlr_evt_cbs_t cbs; //user callbacks
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void *cbs_user_data; //callback userdata
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dw_gdma_channel_handle_t dma_chan; //dwgdma channel handle
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size_t dvp_transfer_size; //csi transfer size for dwgdma
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bool isr_installed; //is isr installed
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esp_cam_ctlr_t base;
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} isp_dvp_controller_t;
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typedef struct isp_dvp_ctx_t {
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_lock_t mutex;
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isp_dvp_controller_t *dvp_ctlr[SOC_ISP_DVP_CTLR_NUMS];
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} isp_dvp_ctx_t;
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static const char *TAG = "ISP_DVP";
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static isp_dvp_ctx_t s_ctx;
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static esp_err_t s_isp_io_init(isp_dvp_controller_t *dvp_ctlr, const esp_cam_ctlr_isp_dvp_cfg_t *ctlr_config);
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static esp_err_t s_isp_claim_dvp_controller(isp_proc_handle_t isp_proc, isp_dvp_controller_t *dvp_ctlr);
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static esp_err_t s_isp_declaim_dvp_controller(isp_dvp_controller_t *dvp_ctlr);
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static esp_err_t s_isp_del_dvp_controller(esp_cam_ctlr_handle_t handle);
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static esp_err_t s_isp_dvp_get_frame_buffer(esp_cam_ctlr_handle_t handle, uint32_t fb_num, const void **fb0, ...);
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static esp_err_t s_isp_dvp_get_frame_buffer_length(esp_cam_ctlr_handle_t handle, size_t *ret_fb_len);
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static esp_err_t s_isp_dvp_register_event_callbacks(esp_cam_ctlr_handle_t handle, const esp_cam_ctlr_evt_cbs_t *cbs, void *user_data);
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static esp_err_t s_isp_dvp_enable(esp_cam_ctlr_handle_t handle);
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static esp_err_t s_isp_dvp_disable(esp_cam_ctlr_handle_t handle);
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static esp_err_t s_isp_dvp_start(esp_cam_ctlr_handle_t handle);
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static esp_err_t s_isp_dvp_stop(esp_cam_ctlr_handle_t handle);
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static esp_err_t s_isp_dvp_receive(esp_cam_ctlr_handle_t handle, esp_cam_ctlr_trans_t *trans, uint32_t timeout_ms);
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static bool s_dvp_dma_trans_done_callback(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data);
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esp_err_t esp_cam_new_isp_dvp_ctlr(isp_proc_handle_t isp_proc, const esp_cam_ctlr_isp_dvp_cfg_t *ctlr_config, esp_cam_ctlr_handle_t *ret_handle)
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{
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esp_err_t ret = ESP_FAIL;
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ESP_RETURN_ON_FALSE(isp_proc && ctlr_config && ret_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_dvp_controller_t *dvp_ctlr = heap_caps_calloc(1, sizeof(isp_dvp_controller_t), ISP_DVP_MEM_ALLOC_CAPS);
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ESP_RETURN_ON_FALSE(dvp_ctlr, ESP_ERR_NO_MEM, TAG, "no mem for isp dvp controller");
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dvp_ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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dvp_ctlr->isp_proc = isp_proc;
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#if SOC_ISP_SHARE_CSI_BRG
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ESP_GOTO_ON_ERROR(mipi_csi_brg_claim(MIPI_CSI_BRG_USER_ISP_DVP, &isp_proc->csi_brg_id), err, TAG, "csi bridge is in use already");
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#endif
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//claim an DVP controller
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ESP_GOTO_ON_ERROR(s_isp_claim_dvp_controller(isp_proc, dvp_ctlr), err, TAG, "no available controller");
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ESP_GOTO_ON_ERROR(dvp_shared_ctrl_claim_io_signals(), err, TAG, "failed to claim io signals");
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ESP_GOTO_ON_ERROR(s_isp_io_init(dvp_ctlr, ctlr_config), err, TAG, "io init fail");
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dvp_ctlr->trans_que = xQueueCreateWithCaps(ctlr_config->queue_items, sizeof(esp_cam_ctlr_trans_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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ESP_GOTO_ON_FALSE(dvp_ctlr->trans_que, ESP_ERR_NO_MEM, err, TAG, "no memory for transaction queue");
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//in color type
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int in_bits_per_pixel = color_hal_pixel_format_get_bit_depth(isp_proc->in_color_format);
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dvp_ctlr->in_bpp = in_bits_per_pixel;
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ESP_LOGD(TAG, "dvp_ctlr->in_bpp: 0d %d", dvp_ctlr->in_bpp);
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//out color type
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int out_bits_per_pixel = color_hal_pixel_format_get_bit_depth(isp_proc->out_color_format);
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dvp_ctlr->out_bpp = out_bits_per_pixel;
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ESP_LOGD(TAG, "dvp_ctlr->out_bpp: 0d %d", dvp_ctlr->out_bpp);
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// Note: Width * Height * BitsPerPixel must be divisible by 8
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int fb_size_in_bits = isp_proc->v_res * isp_proc->h_res * out_bits_per_pixel;
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ESP_GOTO_ON_FALSE((fb_size_in_bits % 8 == 0), ESP_ERR_INVALID_ARG, err, TAG, "framesize not 8bit aligned");
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dvp_ctlr->fb_size_in_bytes = fb_size_in_bits / 8;
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ESP_LOGD(TAG, "dvp_ctlr->fb_size_in_bytes=%d", dvp_ctlr->fb_size_in_bytes);
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dvp_ctlr->bk_buffer_dis = ctlr_config->bk_buffer_dis;
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if (!dvp_ctlr->bk_buffer_dis) {
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size_t dma_alignment = 4;
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size_t cache_alignment = 1;
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ESP_GOTO_ON_ERROR(esp_cache_get_alignment(MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA, &cache_alignment), err, TAG, "failed to get cache alignment");
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size_t alignment = MAX(cache_alignment, dma_alignment);
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ESP_LOGD(TAG, "alignment: 0x%x\n", alignment);
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dvp_ctlr->backup_buffer = heap_caps_aligned_alloc(alignment, dvp_ctlr->fb_size_in_bytes, MALLOC_CAP_SPIRAM);
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ESP_GOTO_ON_FALSE(dvp_ctlr->backup_buffer, ESP_ERR_NO_MEM, err, TAG, "no mem for backup buffer");
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ESP_LOGD(TAG, "dvp_ctlr->backup_buffer: %p\n", dvp_ctlr->backup_buffer);
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esp_cache_msync((void *)(dvp_ctlr->backup_buffer), dvp_ctlr->fb_size_in_bytes, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
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}
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bool valid_format = isp_ll_dvp_set_data_type(isp_proc->hal.hw, isp_proc->in_color_format);
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ESP_GOTO_ON_FALSE(valid_format, ESP_ERR_INVALID_ARG, err, TAG, "invalid dvp color space config");
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if (ctlr_config->io_flags.pclk_invert) {
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isp_ll_cam_enable_pclk_invert(isp_proc->hal.hw, true);
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}
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if (ctlr_config->io_flags.hsync_invert) {
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isp_ll_cam_enable_hsync_invert(isp_proc->hal.hw, true);
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}
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if (ctlr_config->io_flags.vsync_invert) {
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isp_ll_cam_enable_vsync_invert(isp_proc->hal.hw, true);
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}
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if (ctlr_config->io_flags.de_invert) {
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isp_ll_cam_enable_de_invert(isp_proc->hal.hw, true);
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}
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isp_ll_dvp_cam_reset(isp_proc->hal.hw);
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// configure DW_GDMA for ISP DVP
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dw_gdma_channel_alloc_config_t dvp_dma_alloc_config = {
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.src = {
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.block_transfer_type = DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS,
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#if SOC_ISP_SHARE_CSI_BRG
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.role = DW_GDMA_ROLE_PERIPH_CSI, //CSI bridge
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#endif
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.handshake_type = DW_GDMA_HANDSHAKE_HW,
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.num_outstanding_requests = 5,
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.status_fetch_addr = MIPI_CSI_BRG_MEM_BASE,
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},
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.dst = {
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.block_transfer_type = DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS,
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.role = DW_GDMA_ROLE_MEM,
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.handshake_type = DW_GDMA_HANDSHAKE_HW,
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.num_outstanding_requests = 5,
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},
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.flow_controller = DW_GDMA_FLOW_CTRL_SRC,
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.chan_priority = 1,
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};
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ESP_ERROR_CHECK(dw_gdma_new_channel(&dvp_dma_alloc_config, &dvp_ctlr->dma_chan));
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size_t dvp_transfer_size = isp_proc->h_res * isp_proc->v_res * dvp_ctlr->in_bpp / 64;
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dvp_ctlr->dvp_transfer_size = dvp_transfer_size;
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ESP_LOGD(TAG, "dvp_transfer_size: 0d %d", dvp_transfer_size);
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dvp_ctlr->fsm = ISP_FSM_INIT;
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isp_proc->csi_brg_hw = MIPI_CSI_BRG_LL_GET_HW(isp_proc->csi_brg_id);
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mipi_csi_brg_ll_set_intput_data_h_pixel_num(isp_proc->csi_brg_hw, isp_proc->h_res);
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mipi_csi_brg_ll_set_intput_data_v_row_num(isp_proc->csi_brg_hw, isp_proc->v_res);
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mipi_csi_brg_ll_set_burst_len(isp_proc->csi_brg_hw, 512);
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esp_cam_ctlr_t *cam_ctlr = &(dvp_ctlr->base);
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cam_ctlr->del = s_isp_del_dvp_controller;
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cam_ctlr->enable = s_isp_dvp_enable;
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cam_ctlr->start = s_isp_dvp_start;
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cam_ctlr->stop = s_isp_dvp_stop;
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cam_ctlr->disable = s_isp_dvp_disable;
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cam_ctlr->receive = s_isp_dvp_receive;
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cam_ctlr->register_event_callbacks = s_isp_dvp_register_event_callbacks;
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cam_ctlr->get_internal_buffer = s_isp_dvp_get_frame_buffer;
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cam_ctlr->get_buffer_len = s_isp_dvp_get_frame_buffer_length;
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*ret_handle = cam_ctlr;
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return ESP_OK;
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err:
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if (dvp_ctlr) {
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s_isp_del_dvp_controller(&(dvp_ctlr->base));
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}
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return ret;
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}
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esp_err_t s_isp_del_dvp_controller(esp_cam_ctlr_handle_t handle)
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{
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ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
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ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
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if (dvp_ctlr->dma_chan) {
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ESP_RETURN_ON_ERROR(dw_gdma_del_channel(dvp_ctlr->dma_chan), TAG, "failed to delete dwgdma channel");
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}
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#if SOC_ISP_SHARE_CSI_BRG
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ESP_RETURN_ON_ERROR(mipi_csi_brg_declaim(dvp_ctlr->isp_proc->csi_brg_id), TAG, "declaim csi bridge fail");
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#endif
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ESP_RETURN_ON_ERROR(s_isp_declaim_dvp_controller(dvp_ctlr), TAG, "controller isn't in use");
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ESP_RETURN_ON_ERROR(dvp_shared_ctrl_declaim_io_signals(), TAG, "failed to declaim io signals");
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if (!dvp_ctlr->bk_buffer_dis) {
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free(dvp_ctlr->backup_buffer);
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}
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if (dvp_ctlr->trans_que) {
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vQueueDeleteWithCaps(dvp_ctlr->trans_que);
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}
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free(dvp_ctlr);
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return ESP_OK;
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}
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static esp_err_t s_isp_dvp_get_frame_buffer(esp_cam_ctlr_handle_t handle, uint32_t fb_num, const void **fb0, ...)
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{
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isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
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ESP_RETURN_ON_FALSE((dvp_ctlr->fsm >= ISP_FSM_INIT) && (dvp_ctlr->backup_buffer), ESP_ERR_INVALID_STATE, TAG, "driver isn't initialized or back_buffer isn't available");
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ESP_RETURN_ON_FALSE(fb_num && fb_num <= 1, ESP_ERR_INVALID_ARG, TAG, "invalid frame buffer number");
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dvp_ctlr->bk_buffer_exposed = true;
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const void **fb_itor = fb0;
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va_list args;
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va_start(args, fb0);
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for (uint32_t i = 0; i < fb_num; i++) {
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if (fb_itor) {
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*fb_itor = dvp_ctlr->backup_buffer;
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fb_itor = va_arg(args, const void **);
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}
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}
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va_end(args);
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return ESP_OK;
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}
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static esp_err_t s_isp_dvp_get_frame_buffer_length(esp_cam_ctlr_handle_t handle, size_t *ret_fb_len)
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{
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isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
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ESP_RETURN_ON_FALSE((dvp_ctlr->fsm >= ISP_FSM_INIT) && (dvp_ctlr->backup_buffer), ESP_ERR_INVALID_STATE, TAG, "driver isn't initialized or back_buffer isn't available");
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*ret_fb_len = dvp_ctlr->fb_size_in_bytes;
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return ESP_OK;
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}
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static esp_err_t s_isp_dvp_register_event_callbacks(esp_cam_ctlr_handle_t handle, const esp_cam_ctlr_evt_cbs_t *cbs, void *user_data)
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{
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ESP_RETURN_ON_FALSE(handle && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
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ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
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#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE
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if (cbs->on_get_new_trans) {
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ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM");
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}
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if (cbs->on_trans_finished) {
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ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_trans_finished), ESP_ERR_INVALID_ARG, TAG, "on_trans_finished callback not in IRAM");
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}
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#endif
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if (!dvp_ctlr->isr_installed) {
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dw_gdma_event_callbacks_t csi_dma_cbs = {
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.on_full_trans_done = s_dvp_dma_trans_done_callback,
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};
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ESP_RETURN_ON_ERROR(dw_gdma_channel_register_event_callbacks(dvp_ctlr->dma_chan, &csi_dma_cbs, dvp_ctlr), TAG, "failed to register dma callbacks");
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dvp_ctlr->isr_installed = true;
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}
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dvp_ctlr->cbs.on_get_new_trans = cbs->on_get_new_trans;
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dvp_ctlr->cbs.on_trans_finished = cbs->on_trans_finished;
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dvp_ctlr->cbs_user_data = user_data;
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return ESP_OK;
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}
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static esp_err_t s_isp_dvp_enable(esp_cam_ctlr_handle_t handle)
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{
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ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
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ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
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portENTER_CRITICAL(&dvp_ctlr->spinlock);
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dvp_ctlr->fsm = ISP_FSM_ENABLE;
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portEXIT_CRITICAL(&dvp_ctlr->spinlock);
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return ESP_OK;
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}
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static esp_err_t s_isp_dvp_disable(esp_cam_ctlr_handle_t handle)
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{
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ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
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ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state");
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portENTER_CRITICAL(&dvp_ctlr->spinlock);
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dvp_ctlr->fsm = ISP_FSM_INIT;
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portEXIT_CRITICAL(&dvp_ctlr->spinlock);
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return ESP_OK;
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}
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static esp_err_t s_isp_dvp_start(esp_cam_ctlr_handle_t handle)
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{
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ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
|
||||
ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state");
|
||||
ESP_RETURN_ON_FALSE(dvp_ctlr->isp_proc->isp_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "ISP processor isn't in enable state");
|
||||
ESP_RETURN_ON_FALSE(dvp_ctlr->cbs.on_trans_finished, ESP_ERR_INVALID_STATE, TAG, "no on_trans_finished callback registered");
|
||||
|
||||
mipi_csi_brg_ll_enable(dvp_ctlr->isp_proc->csi_brg_hw, true);
|
||||
isp_ll_cam_enable(dvp_ctlr->isp_proc->hal.hw, true);
|
||||
|
||||
esp_cam_ctlr_trans_t trans = {};
|
||||
bool has_new_trans = false;
|
||||
|
||||
if (dvp_ctlr->cbs.on_get_new_trans) {
|
||||
dvp_ctlr->cbs.on_get_new_trans(handle, &trans, dvp_ctlr->cbs_user_data);
|
||||
if (trans.buffer) {
|
||||
has_new_trans = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (!has_new_trans) {
|
||||
if (!dvp_ctlr->bk_buffer_dis) {
|
||||
trans.buffer = dvp_ctlr->backup_buffer;
|
||||
trans.buflen = dvp_ctlr->fb_size_in_bytes;
|
||||
} else {
|
||||
ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_STATE, TAG, "no ready transaction, and no backup buffer");
|
||||
}
|
||||
}
|
||||
|
||||
ESP_LOGD(TAG, "trans.buffer: %p, trans.buflen: %d", trans.buffer, trans.buflen);
|
||||
dvp_ctlr->trans = trans;
|
||||
|
||||
portENTER_CRITICAL(&dvp_ctlr->spinlock);
|
||||
dvp_ctlr->fsm = ISP_FSM_START;
|
||||
portEXIT_CRITICAL(&dvp_ctlr->spinlock);
|
||||
|
||||
dw_gdma_block_transfer_config_t dvp_dma_transfer_config = {};
|
||||
dvp_dma_transfer_config = (dw_gdma_block_transfer_config_t) {
|
||||
.src = {
|
||||
.addr = MIPI_CSI_BRG_MEM_BASE,
|
||||
.burst_mode = DW_GDMA_BURST_MODE_FIXED,
|
||||
.burst_items = DW_GDMA_BURST_ITEMS_512,
|
||||
.burst_len = 16,
|
||||
.width = DW_GDMA_TRANS_WIDTH_64,
|
||||
},
|
||||
.dst = {
|
||||
.addr = (uint32_t)(trans.buffer),
|
||||
.burst_mode = DW_GDMA_BURST_MODE_INCREMENT,
|
||||
.burst_items = DW_GDMA_BURST_ITEMS_512,
|
||||
.burst_len = 16,
|
||||
.width = DW_GDMA_TRANS_WIDTH_64,
|
||||
},
|
||||
.size = dvp_ctlr->dvp_transfer_size,
|
||||
};
|
||||
ESP_RETURN_ON_ERROR(dw_gdma_channel_config_transfer(dvp_ctlr->dma_chan, &dvp_dma_transfer_config), TAG, "failed to configure dwgdma transfer");
|
||||
ESP_RETURN_ON_ERROR(dw_gdma_channel_enable_ctrl(dvp_ctlr->dma_chan, true), TAG, "failed to enable dwgdma");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t s_isp_dvp_stop(esp_cam_ctlr_handle_t handle)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
|
||||
isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
|
||||
ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_START, ESP_ERR_INVALID_STATE, TAG, "driver isn't started");
|
||||
|
||||
isp_ll_cam_enable(dvp_ctlr->isp_proc->hal.hw, false);
|
||||
mipi_csi_brg_ll_enable(dvp_ctlr->isp_proc->csi_brg_hw, false);
|
||||
ESP_RETURN_ON_ERROR(dw_gdma_channel_enable_ctrl(dvp_ctlr->dma_chan, false), TAG, "failed to disable dwgdma");
|
||||
|
||||
portENTER_CRITICAL(&dvp_ctlr->spinlock);
|
||||
dvp_ctlr->fsm = ISP_FSM_INIT;
|
||||
portEXIT_CRITICAL(&dvp_ctlr->spinlock);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t s_isp_dvp_receive(esp_cam_ctlr_handle_t handle, esp_cam_ctlr_trans_t *trans, uint32_t timeout_ms)
|
||||
{
|
||||
esp_err_t ret = ESP_OK;
|
||||
ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
|
||||
isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
|
||||
|
||||
ESP_RETURN_ON_FALSE(trans->buffer, ESP_ERR_INVALID_ARG, TAG, "invalid argument: no trans buffer");
|
||||
ESP_RETURN_ON_FALSE((trans->buflen >= dvp_ctlr->fb_size_in_bytes), ESP_ERR_INVALID_ARG, TAG, "invalid argument: trans buffer smaller than framebuffer size");
|
||||
|
||||
TickType_t ticks_to_wait = timeout_ms / portTICK_PERIOD_MS;
|
||||
if (timeout_ms == ESP_CAM_CTLR_MAX_DELAY) {
|
||||
ticks_to_wait = portMAX_DELAY;
|
||||
}
|
||||
|
||||
BaseType_t r = xQueueSend(dvp_ctlr->trans_que, trans, ticks_to_wait);
|
||||
if (r != pdTRUE) {
|
||||
ret = ESP_ERR_TIMEOUT;
|
||||
ESP_LOGW(TAG, "csi recv API, transaction queue is full, failed to send transaction to the queue");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
IRAM_ATTR static bool s_dvp_dma_trans_done_callback(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data)
|
||||
{
|
||||
bool need_yield = false;
|
||||
BaseType_t high_task_woken = pdFALSE;
|
||||
isp_dvp_controller_t *dvp_ctlr = (isp_dvp_controller_t *)user_data;
|
||||
bool has_new_trans = false;
|
||||
|
||||
dw_gdma_block_transfer_config_t dvp_dma_transfer_config = {};
|
||||
dvp_dma_transfer_config = (dw_gdma_block_transfer_config_t) {
|
||||
.src = {
|
||||
.addr = MIPI_CSI_BRG_MEM_BASE,
|
||||
.burst_mode = DW_GDMA_BURST_MODE_FIXED,
|
||||
.burst_items = DW_GDMA_BURST_ITEMS_512,
|
||||
.burst_len = 16,
|
||||
.width = DW_GDMA_TRANS_WIDTH_64,
|
||||
},
|
||||
.dst = {
|
||||
.addr = 0,
|
||||
.burst_mode = DW_GDMA_BURST_MODE_INCREMENT,
|
||||
.burst_items = DW_GDMA_BURST_ITEMS_512,
|
||||
.burst_len = 16,
|
||||
.width = DW_GDMA_TRANS_WIDTH_64,
|
||||
},
|
||||
.size = dvp_ctlr->dvp_transfer_size,
|
||||
};
|
||||
esp_cam_ctlr_trans_t new_trans = {};
|
||||
|
||||
if (dvp_ctlr->cbs.on_get_new_trans) {
|
||||
need_yield = dvp_ctlr->cbs.on_get_new_trans(&(dvp_ctlr->base), &new_trans, dvp_ctlr->cbs_user_data);
|
||||
if (new_trans.buffer && new_trans.buflen >= dvp_ctlr->fb_size_in_bytes) {
|
||||
dvp_dma_transfer_config.dst.addr = (uint32_t)(new_trans.buffer);
|
||||
has_new_trans = true;
|
||||
}
|
||||
} else if (xQueueReceiveFromISR(dvp_ctlr->trans_que, &new_trans, &high_task_woken) == pdTRUE) {
|
||||
if (new_trans.buffer && new_trans.buflen >= dvp_ctlr->fb_size_in_bytes) {
|
||||
dvp_dma_transfer_config.dst.addr = (uint32_t)(new_trans.buffer);
|
||||
has_new_trans = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (!has_new_trans) {
|
||||
if (!dvp_ctlr->bk_buffer_dis) {
|
||||
new_trans.buffer = dvp_ctlr->backup_buffer;
|
||||
new_trans.buflen = dvp_ctlr->fb_size_in_bytes;
|
||||
ESP_EARLY_LOGD(TAG, "no new buffer or no long enough new buffer, use driver internal buffer");
|
||||
dvp_dma_transfer_config.dst.addr = (uint32_t)dvp_ctlr->backup_buffer;
|
||||
} else {
|
||||
assert(false && "no new buffer, and no driver internal buffer");
|
||||
}
|
||||
}
|
||||
|
||||
ESP_EARLY_LOGD(TAG, "new_trans.buffer: %p, new_trans.buflen: %d", new_trans.buffer, new_trans.buflen);
|
||||
dw_gdma_channel_config_transfer(chan, &dvp_dma_transfer_config);
|
||||
dw_gdma_channel_enable_ctrl(chan, true);
|
||||
|
||||
if ((dvp_ctlr->trans.buffer != dvp_ctlr->backup_buffer) || dvp_ctlr->bk_buffer_exposed) {
|
||||
esp_err_t ret = esp_cache_msync((void *)(dvp_ctlr->trans.buffer), dvp_ctlr->trans.received_size, ESP_CACHE_MSYNC_FLAG_INVALIDATE);
|
||||
assert(ret == ESP_OK);
|
||||
assert(dvp_ctlr->cbs.on_trans_finished);
|
||||
if (dvp_ctlr->cbs.on_trans_finished) {
|
||||
dvp_ctlr->trans.received_size = dvp_ctlr->fb_size_in_bytes;
|
||||
need_yield |= dvp_ctlr->cbs.on_trans_finished(&(dvp_ctlr->base), &dvp_ctlr->trans, dvp_ctlr->cbs_user_data);
|
||||
}
|
||||
}
|
||||
|
||||
//dvp_ctlr->trans is the transaction saved before dma starts
|
||||
memset(&dvp_ctlr->trans, 0x0, sizeof(esp_cam_ctlr_trans_t));
|
||||
dvp_ctlr->trans = new_trans;
|
||||
|
||||
need_yield |= high_task_woken == pdTRUE;
|
||||
return need_yield;
|
||||
}
|
||||
|
||||
static esp_err_t s_isp_io_init(isp_dvp_controller_t *dvp_ctlr, const esp_cam_ctlr_isp_dvp_cfg_t *ctlr_config)
|
||||
{
|
||||
gpio_config_t gpio_conf = {
|
||||
.intr_type = GPIO_INTR_DISABLE,
|
||||
.mode = GPIO_MODE_INPUT,
|
||||
.pull_down_en = false,
|
||||
.pull_up_en = true,
|
||||
};
|
||||
|
||||
if (ctlr_config->pclk_io) {
|
||||
gpio_conf.pin_bit_mask = 1ULL << ctlr_config->pclk_io;
|
||||
ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "failed to configure pclk gpio");
|
||||
ESP_LOGD(TAG, "pclk_io: %d, dvp_pclk_sig: %"PRId32, ctlr_config->pclk_io, isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_pclk_sig);
|
||||
esp_rom_gpio_connect_in_signal(ctlr_config->pclk_io, isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_pclk_sig, false);
|
||||
}
|
||||
|
||||
if (ctlr_config->hsync_io) {
|
||||
gpio_conf.pin_bit_mask = 1ULL << ctlr_config->hsync_io;
|
||||
ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "failed to configure hsync gpio");
|
||||
ESP_LOGD(TAG, "hsync_io: %d, dvp_hsync_sig: %"PRId32, ctlr_config->hsync_io, isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_hsync_sig);
|
||||
esp_rom_gpio_connect_in_signal(ctlr_config->hsync_io, isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_hsync_sig, false);
|
||||
}
|
||||
|
||||
if (ctlr_config->vsync_io) {
|
||||
gpio_conf.pin_bit_mask = 1ULL << ctlr_config->vsync_io;
|
||||
ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "failed to configure vsync gpio");
|
||||
ESP_LOGD(TAG, "vsync_io: %d, dvp_vsync_sig: %"PRId32, ctlr_config->vsync_io, isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_vsync_sig);
|
||||
esp_rom_gpio_connect_in_signal(ctlr_config->vsync_io, isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_vsync_sig, false);
|
||||
}
|
||||
|
||||
if (ctlr_config->de_io) {
|
||||
gpio_conf.pin_bit_mask = 1ULL << ctlr_config->de_io;
|
||||
ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "failed to configure de gpio");
|
||||
ESP_LOGD(TAG, "de_io: %d, dvp_de_sig: %"PRId32, ctlr_config->de_io, isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_de_sig);
|
||||
esp_rom_gpio_connect_in_signal(ctlr_config->de_io, isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_de_sig, false);
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < ctlr_config->data_width; i++) {
|
||||
gpio_conf.pin_bit_mask = 1ULL << ctlr_config->data_io[i];
|
||||
ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "failed to configure data gpio");
|
||||
ESP_LOGD(TAG, "data_io: %d, dvp_data_sig: %"PRId32, ctlr_config->data_io[i], isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_data_sig[i]);
|
||||
esp_rom_gpio_connect_in_signal(ctlr_config->data_io[i], isp_hw_info.dvp_ctlr[dvp_ctlr->id].dvp_data_sig[i], false);
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t s_isp_claim_dvp_controller(isp_proc_handle_t isp_proc, isp_dvp_controller_t *dvp_ctlr)
|
||||
{
|
||||
assert(isp_proc && dvp_ctlr);
|
||||
|
||||
_lock_acquire(&s_ctx.mutex);
|
||||
bool found = false;
|
||||
for (int i = 0; i < SOC_ISP_DVP_CTLR_NUMS; i++) {
|
||||
found = !s_ctx.dvp_ctlr[i];
|
||||
if (found) {
|
||||
s_ctx.dvp_ctlr[i] = dvp_ctlr;
|
||||
dvp_ctlr->id = i;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
_lock_release(&s_ctx.mutex);
|
||||
|
||||
if (!found) {
|
||||
return ESP_ERR_NOT_FOUND;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t s_isp_declaim_dvp_controller(isp_dvp_controller_t *dvp_ctlr)
|
||||
{
|
||||
assert(dvp_ctlr);
|
||||
|
||||
_lock_acquire(&s_ctx.mutex);
|
||||
s_ctx.dvp_ctlr[dvp_ctlr->id] = NULL;
|
||||
_lock_release(&s_ctx.mutex);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
Reference in New Issue
Block a user