mirror of
https://github.com/espressif/esp-idf.git
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change(soc/usb): Merge duplicated definitions for P4 v1 and v3
This commit is contained in:
Tomas Rezucha
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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@@ -21,92 +21,92 @@ typedef union {
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* the signal is controlled by the chip input, 1'b1: the signal is controlled by the
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* software.
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*/
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uint32_t srp_sessend_override:1;
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uint32_t srp_sessend_override: 1;
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/** srp_sessend_value : R/W; bitpos: [1]; default: 0;
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* Software over-ride value of srp session end signal.
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*/
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uint32_t srp_sessend_value:1;
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uint32_t srp_sessend_value: 1;
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/** phy_sel : R/W; bitpos: [2]; default: 0;
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* Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
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*/
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uint32_t phy_sel:1;
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uint32_t phy_sel: 1;
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/** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
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* Force the dfifo to go into low power mode. The data in dfifo will not lost.
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*/
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uint32_t dfifo_force_pd:1;
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uint32_t dfifo_force_pd: 1;
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/** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
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* Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
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*/
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uint32_t dbnce_fltr_bypass:1;
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uint32_t dbnce_fltr_bypass: 1;
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/** exchg_pins_override : R/W; bitpos: [5]; default: 0;
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* Enable software controlle USB D+ D- exchange
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*/
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uint32_t exchg_pins_override:1;
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uint32_t exchg_pins_override: 1;
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/** exchg_pins : R/W; bitpos: [6]; default: 0;
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* USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
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*/
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uint32_t exchg_pins:1;
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uint32_t exchg_pins: 1;
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/** vrefh : R/W; bitpos: [8:7]; default: 0;
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* Control single-end input high threshold,1.76V to 2V, step 80mV.
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*/
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uint32_t vrefh:2;
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uint32_t vrefh: 2;
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/** vrefl : R/W; bitpos: [10:9]; default: 0;
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* Control single-end input low threshold,0.8V to 1.04V, step 80mV.
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*/
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uint32_t vrefl:2;
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uint32_t vrefl: 2;
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/** vref_override : R/W; bitpos: [11]; default: 0;
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* Enable software controlle input threshold.
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*/
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uint32_t vref_override:1;
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uint32_t vref_override: 1;
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/** pad_pull_override : R/W; bitpos: [12]; default: 0;
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* Enable software controlle USB D+ D- pullup pulldown.
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*/
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uint32_t pad_pull_override:1;
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uint32_t pad_pull_override: 1;
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/** dp_pullup : R/W; bitpos: [13]; default: 0;
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* Controlle USB D+ pullup.
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*/
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uint32_t dp_pullup:1;
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uint32_t dp_pullup: 1;
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/** dp_pulldown : R/W; bitpos: [14]; default: 0;
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* Controlle USB D+ pulldown.
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*/
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uint32_t dp_pulldown:1;
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uint32_t dp_pulldown: 1;
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/** dm_pullup : R/W; bitpos: [15]; default: 0;
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* Controlle USB D+ pullup.
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*/
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uint32_t dm_pullup:1;
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uint32_t dm_pullup: 1;
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/** dm_pulldown : R/W; bitpos: [16]; default: 0;
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* Controlle USB D+ pulldown.
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*/
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uint32_t dm_pulldown:1;
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uint32_t dm_pulldown: 1;
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/** pullup_value : R/W; bitpos: [17]; default: 0;
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* Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
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*/
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uint32_t pullup_value:1;
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uint32_t pullup_value: 1;
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/** usb_pad_enable : R/W; bitpos: [18]; default: 0;
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* Enable USB pad function.
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*/
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uint32_t usb_pad_enable:1;
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uint32_t usb_pad_enable: 1;
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/** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
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* Force ahb clock always on.
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*/
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uint32_t ahb_clk_force_on:1;
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uint32_t ahb_clk_force_on: 1;
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/** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
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* Force phy clock always on.
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*/
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uint32_t phy_clk_force_on:1;
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uint32_t phy_clk_force_on: 1;
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/** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
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* Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
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*/
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uint32_t phy_tx_edge_sel:1;
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uint32_t phy_tx_edge_sel: 1;
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/** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
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* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
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*/
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uint32_t dfifo_force_pu:1;
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uint32_t reserved_23:8;
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uint32_t dfifo_force_pu: 1;
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uint32_t reserved_23: 8;
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/** clk_en : R/W; bitpos: [31]; default: 0;
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* Disable auto clock gating of CSR registers.
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*/
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uint32_t clk_en:1;
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uint32_t clk_en: 1;
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};
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uint32_t val;
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} usb_wrap_otg_conf_reg_t;
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@@ -119,32 +119,32 @@ typedef union {
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/** test_enable : R/W; bitpos: [0]; default: 0;
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* Enable to test the USB pad.
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*/
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uint32_t test_enable:1;
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uint32_t test_enable: 1;
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/** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
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* USB pad oen in test.
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*/
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uint32_t test_usb_wrap_oe:1;
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uint32_t test_usb_wrap_oe: 1;
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/** test_tx_dp : R/W; bitpos: [2]; default: 0;
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* USB D+ tx value in test.
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*/
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uint32_t test_tx_dp:1;
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uint32_t test_tx_dp: 1;
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/** test_tx_dm : R/W; bitpos: [3]; default: 0;
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* USB D- tx value in test.
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*/
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uint32_t test_tx_dm:1;
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uint32_t test_tx_dm: 1;
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/** test_rx_rcv : RO; bitpos: [4]; default: 0;
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* USB differential rx value in test.
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*/
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uint32_t test_rx_rcv:1;
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uint32_t test_rx_rcv: 1;
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/** test_rx_dp : RO; bitpos: [5]; default: 0;
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* USB D+ rx value in test.
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*/
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uint32_t test_rx_dp:1;
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uint32_t test_rx_dp: 1;
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/** test_rx_dm : RO; bitpos: [6]; default: 0;
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* USB D- rx value in test.
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*/
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uint32_t test_rx_dm:1;
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uint32_t reserved_7:25;
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uint32_t test_rx_dm: 1;
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uint32_t reserved_7: 25;
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};
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uint32_t val;
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} usb_wrap_test_conf_reg_t;
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@@ -157,12 +157,11 @@ typedef union {
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/** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
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* Date register.
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*/
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uint32_t usb_wrap_date:32;
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uint32_t usb_wrap_date: 32;
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};
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uint32_t val;
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} usb_wrap_date_reg_t;
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typedef struct usb_wrap_dev_t {
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volatile usb_wrap_otg_conf_reg_t otg_conf;
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volatile usb_wrap_test_conf_reg_t test_conf;
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@@ -1,181 +0,0 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** USB_WRAP_OTG_CONF_REG register
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* USB wrapper configuration registers.
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*/
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#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
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/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
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* This bit is used to enable the software over-ride of srp session end signal. 1'b0:
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* the signal is controlled by the chip input, 1'b1: the signal is controlled by the
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* software.
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*/
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#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0))
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#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S)
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#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001U
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#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0
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/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0;
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* Software over-ride value of srp session end signal.
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*/
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#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1))
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#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S)
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#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001U
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#define USB_WRAP_SRP_SESSEND_VALUE_S 1
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/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0;
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* Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
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*/
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#define USB_WRAP_PHY_SEL (BIT(2))
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#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S)
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#define USB_WRAP_PHY_SEL_V 0x00000001U
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#define USB_WRAP_PHY_SEL_S 2
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/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0;
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* Force the dfifo to go into low power mode. The data in dfifo will not lost.
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*/
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#define USB_WRAP_DFIFO_FORCE_PD (BIT(3))
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#define USB_WRAP_DFIFO_FORCE_PD_M (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S)
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#define USB_WRAP_DFIFO_FORCE_PD_V 0x00000001U
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#define USB_WRAP_DFIFO_FORCE_PD_S 3
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/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0;
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* Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
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*/
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#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4))
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#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S)
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#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001U
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#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4
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/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0;
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* Enable software controlle USB D+ D- exchange
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*/
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#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5))
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#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S)
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#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001U
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#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5
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/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0;
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* USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
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*/
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#define USB_WRAP_EXCHG_PINS (BIT(6))
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#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S)
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#define USB_WRAP_EXCHG_PINS_V 0x00000001U
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#define USB_WRAP_EXCHG_PINS_S 6
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/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0;
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* Control single-end input high threshold,1.76V to 2V, step 80mV.
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*/
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#define USB_WRAP_VREFH 0x00000003U
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#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S)
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#define USB_WRAP_VREFH_V 0x00000003U
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#define USB_WRAP_VREFH_S 7
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/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0;
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* Control single-end input low threshold,0.8V to 1.04V, step 80mV.
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*/
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#define USB_WRAP_VREFL 0x00000003U
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#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S)
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#define USB_WRAP_VREFL_V 0x00000003U
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#define USB_WRAP_VREFL_S 9
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/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0;
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* Enable software controlle input threshold.
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*/
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#define USB_WRAP_VREF_OVERRIDE (BIT(11))
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#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S)
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#define USB_WRAP_VREF_OVERRIDE_V 0x00000001U
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#define USB_WRAP_VREF_OVERRIDE_S 11
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/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0;
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* Enable software controlle USB D+ D- pullup pulldown.
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*/
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#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12))
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#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S)
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#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001U
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#define USB_WRAP_PAD_PULL_OVERRIDE_S 12
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/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0;
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* Controlle USB D+ pullup.
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*/
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#define USB_WRAP_DP_PULLUP (BIT(13))
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#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S)
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#define USB_WRAP_DP_PULLUP_V 0x00000001U
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#define USB_WRAP_DP_PULLUP_S 13
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/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0;
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* Controlle USB D+ pulldown.
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*/
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#define USB_WRAP_DP_PULLDOWN (BIT(14))
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#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S)
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#define USB_WRAP_DP_PULLDOWN_V 0x00000001U
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#define USB_WRAP_DP_PULLDOWN_S 14
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/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0;
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* Controlle USB D+ pullup.
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*/
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#define USB_WRAP_DM_PULLUP (BIT(15))
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#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S)
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#define USB_WRAP_DM_PULLUP_V 0x00000001U
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#define USB_WRAP_DM_PULLUP_S 15
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/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0;
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* Controlle USB D+ pulldown.
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*/
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#define USB_WRAP_DM_PULLDOWN (BIT(16))
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#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S)
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#define USB_WRAP_DM_PULLDOWN_V 0x00000001U
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#define USB_WRAP_DM_PULLDOWN_S 16
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/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0;
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* Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
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*/
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#define USB_WRAP_PULLUP_VALUE (BIT(17))
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#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S)
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#define USB_WRAP_PULLUP_VALUE_V 0x00000001U
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#define USB_WRAP_PULLUP_VALUE_S 17
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/** USB_WRAP_USB_PAD_ENABLE : R/W; bitpos: [18]; default: 0;
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* Enable USB pad function.
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*/
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#define USB_WRAP_USB_PAD_ENABLE (BIT(18))
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#define USB_WRAP_USB_PAD_ENABLE_M (USB_WRAP_USB_PAD_ENABLE_V << USB_WRAP_USB_PAD_ENABLE_S)
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#define USB_WRAP_USB_PAD_ENABLE_V 0x00000001U
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#define USB_WRAP_USB_PAD_ENABLE_S 18
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/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 0;
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* Force ahb clock always on.
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*/
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#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19))
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#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S)
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#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001U
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#define USB_WRAP_AHB_CLK_FORCE_ON_S 19
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/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1;
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* Force phy clock always on.
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*/
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#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20))
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S)
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001U
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_S 20
|
||||
/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0;
|
||||
* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
#define USB_WRAP_DFIFO_FORCE_PU (BIT(22))
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_M (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S)
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_V 0x00000001U
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_S 22
|
||||
/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Disable auto clock gating of CSR registers.
|
||||
*/
|
||||
#define USB_WRAP_CLK_EN (BIT(31))
|
||||
#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S)
|
||||
#define USB_WRAP_CLK_EN_V 0x00000001U
|
||||
#define USB_WRAP_CLK_EN_S 31
|
||||
|
||||
/** USB_WRAP_DATE_REG register
|
||||
* Date register.
|
||||
*/
|
||||
#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc)
|
||||
/** USB_WRAP_USB_WRAP_DATE : HRO; bitpos: [31:0]; default: 587400452;
|
||||
* Date register.
|
||||
*/
|
||||
#define USB_WRAP_USB_WRAP_DATE 0xFFFFFFFFU
|
||||
#define USB_WRAP_USB_WRAP_DATE_M (USB_WRAP_USB_WRAP_DATE_V << USB_WRAP_USB_WRAP_DATE_S)
|
||||
#define USB_WRAP_USB_WRAP_DATE_V 0xFFFFFFFFU
|
||||
#define USB_WRAP_USB_WRAP_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,231 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: IDF-13430
|
||||
|
||||
/**
|
||||
* Following register description is taken from
|
||||
* U2OPHYT40LL USB 2.0 OTG PHY specification v2.0
|
||||
*/
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_gate_rx : R/W; bitpos: [0]; default 2'b0;
|
||||
* Clock Gating Control Signal for Rx.
|
||||
* 2'b0 Lower power consumption
|
||||
* 2'b1 Lowest power consumption mode
|
||||
* 2'b2 Normal power consumption mode
|
||||
*/
|
||||
uint32_t clk_gate_rx: 2;
|
||||
/** clk_gate_tx : R/W; bitpos: [2]; default: 1'b0;
|
||||
* Clock Gating Control Signal for Rx.
|
||||
* 1'b0 Low power consumption mode
|
||||
* 1'b1 Normal power consumption mode
|
||||
*/
|
||||
uint32_t clk_gate_tx: 1;
|
||||
/** adj_res_fs : Reserved; bitpos: [3]; default: 0;
|
||||
* Fine tune the 45ohm termination resistor (FS)
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t adj_res_fs: 2;
|
||||
/** adj_res_hs : R/W; bitpos: [5]; default: 3'b100;
|
||||
* Fine tune the 45ohm termination resistor (HS)
|
||||
* 3'b000 40 Ohm
|
||||
* 3'b100 45 Ohm
|
||||
* 3'b110 50 Ohm
|
||||
*/
|
||||
uint32_t adj_res_hs: 3;
|
||||
uint32_t reserved_8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_utmi_fc_00_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
/** adj_vref_sq : R/W; bitpos: [0]; default: 4'b0010;
|
||||
* Squelch detection threshold voltage control bits
|
||||
* 4'b0000 92 mV
|
||||
* 4'b0010 124 mV
|
||||
* 4'b0011 152 mV
|
||||
*/
|
||||
uint32_t adj_vref_sq: 4;
|
||||
/** adj_pw_hs : R/W; bitpos: [4]; default: 4'b1111;
|
||||
* Super power saving with reduced output swing mode control bits (for HS mode only)
|
||||
* 4'b0001 100 mV output swing
|
||||
* 4'b0011 200 mV output swing
|
||||
* 4'b0111 300 mV output swing
|
||||
* 4'b1111 400 mV output swing
|
||||
*/
|
||||
uint32_t adj_pw_hs: 4;
|
||||
uint32_t reserved_8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_utmi_fc_01_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
/** adj_iref_res : R/W; bitpos: [0]; default: 4'b0111
|
||||
* Internal bias current adjustment control bits
|
||||
* 4'b0000 125 uA
|
||||
* 4'b0111 100 uA
|
||||
* 4'b1111 78 uA
|
||||
*/
|
||||
uint32_t adj_iref_res: 4;
|
||||
/** adj_vsw_hs : R/W; bitpos: [4]; default: 3'b100
|
||||
* Output eye shape adjustment control bits
|
||||
* 3'b000 320 mV
|
||||
* 3'b100 400 mV
|
||||
* 3'b111 460 mV
|
||||
*/
|
||||
uint32_t adj_vsw_hs: 3;
|
||||
uint32_t reserved_7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_utmi_fc_02_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
/** adj_pll : R/W; bitpos: [0]; default: 4'b0101
|
||||
* PLL adjustment signal
|
||||
*/
|
||||
uint32_t adj_pll: 4;
|
||||
/** adj_osc : R/W; bitpos: [4]; default: 3'b000
|
||||
* TX Clock phase adjust signal
|
||||
*/
|
||||
uint32_t adj_txclk_phase: 3;
|
||||
uint32_t reserved_7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_utmi_fc_03_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
/** test_sel : R/W; bitpos: [0]; default: 8'b0
|
||||
* The PHY has test_sel register here, which normally drives DTO (Digital Test Output) signal.
|
||||
* In our implementation output of this register is left floating and DTO is driven from Probe module.
|
||||
* Thus writing to this register has no effect and is renamed to 'reserved'
|
||||
*/
|
||||
uint32_t reserved: 8;
|
||||
uint32_t reserved_8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_utmi_fc_04_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
/** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1
|
||||
* RXGAP fix enable
|
||||
*/
|
||||
uint32_t rxgap_fix_en: 1;
|
||||
/** counter_sel : R/W; bitpos: [1]; default: 1'b0
|
||||
* SIE_input sample enable
|
||||
*/
|
||||
uint32_t counter_sel: 1;
|
||||
/** clk_sel : R/W; bitpos: [2]; default: 1'b0
|
||||
* CLK60_30 source select
|
||||
*/
|
||||
uint32_t clk_sel: 1;
|
||||
/** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0
|
||||
* PHY MODE select
|
||||
*/
|
||||
uint32_t phy_mode_sel: 1;
|
||||
/** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0
|
||||
* UNI_BIDI signal
|
||||
*/
|
||||
uint32_t uni_bidi_i: 1;
|
||||
/** short_5v : R/W; bitpos: [5]; default: 1'b0
|
||||
* SHORT_5V signal
|
||||
*/
|
||||
uint32_t short_5v: 1;
|
||||
/** short_5v_enable : R/W; bitpos: [6]; default: 1'b1
|
||||
* SHORT_5V_ENABLE signal
|
||||
*/
|
||||
uint32_t short_5v_enable: 1;
|
||||
/** usable_en : R/W; bitpos: [7]; default: 1'b1
|
||||
* compare_begin delay time select
|
||||
*/
|
||||
uint32_t usable_en: 1;
|
||||
uint32_t reserved_8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_utmi_fc_05_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
/** ls_par_en : R/W; bitpos: [0]; default: 1'b0
|
||||
* LS mode with parallel enable
|
||||
*/
|
||||
uint32_t ls_par_en: 1;
|
||||
/** det_fseop_en : R/W; bitpos: [1]; default: 1'b0
|
||||
* FS EOP detect enable
|
||||
*/
|
||||
uint32_t det_fseop_en: 1;
|
||||
/** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0
|
||||
* Dis_preamble enable
|
||||
*/
|
||||
uint32_t pre_hphy_lsie: 1;
|
||||
/** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0
|
||||
* LS mode keep alive enable
|
||||
*/
|
||||
uint32_t ls_kpalv_en: 1;
|
||||
/** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100
|
||||
* PHY High-SPeed bus turn-around time select
|
||||
*/
|
||||
uint32_t hs_tx2rx_dly_cnt_sel: 3;
|
||||
uint32_t reserved_7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_utmi_fc_06_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
/** cnt_num : R/W; bitpos: [1:0]; default: 2'b00
|
||||
* 3 ms counter select
|
||||
* 00: 392us (Default)
|
||||
* 01: 682us
|
||||
* 10: 1.36ms
|
||||
* 11: 2.72ms
|
||||
*/
|
||||
uint32_t cnt_num: 2;
|
||||
/** clk480_sel : R/W; bitpos: [2]; default: 1'b0
|
||||
* CLK_480 output time select
|
||||
* 0: CLK_480 is valid after a delay time when PLL is locked
|
||||
* 1: CLK_480 is valid immediately after PLL is locked
|
||||
*/
|
||||
uint32_t clk480_sel: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_utmi_fc_07_reg_t;
|
||||
|
||||
typedef struct usb_utmi_dev_t {
|
||||
volatile usb_utmi_fc_00_reg_t fc_00;
|
||||
volatile usb_utmi_fc_01_reg_t fc_01;
|
||||
volatile usb_utmi_fc_02_reg_t fc_02;
|
||||
volatile usb_utmi_fc_03_reg_t fc_03;
|
||||
volatile usb_utmi_fc_04_reg_t fc_04;
|
||||
volatile usb_utmi_fc_05_reg_t fc_05;
|
||||
volatile usb_utmi_fc_06_reg_t fc_06;
|
||||
volatile usb_utmi_fc_07_reg_t fc_07;
|
||||
} usb_utmi_dev_t;
|
||||
|
||||
extern usb_utmi_dev_t USB_UTMI;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(usb_utmi_dev_t) == 0x20, "Invalid size of usb_utmi_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,181 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: USB wrapper registers. */
|
||||
/** Type of otg_conf register
|
||||
* USB wrapper configuration registers.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** srp_sessend_override : R/W; bitpos: [0]; default: 0;
|
||||
* This bit is used to enable the software over-ride of srp session end signal. 1'b0:
|
||||
* the signal is controlled by the chip input, 1'b1: the signal is controlled by the
|
||||
* software.
|
||||
*/
|
||||
uint32_t srp_sessend_override:1;
|
||||
/** srp_sessend_value : R/W; bitpos: [1]; default: 0;
|
||||
* Software over-ride value of srp session end signal.
|
||||
*/
|
||||
uint32_t srp_sessend_value:1;
|
||||
/** phy_sel : R/W; bitpos: [2]; default: 0;
|
||||
* Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
|
||||
*/
|
||||
uint32_t phy_sel:1;
|
||||
/** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
|
||||
* Force the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
uint32_t dfifo_force_pd:1;
|
||||
/** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
|
||||
* Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
|
||||
*/
|
||||
uint32_t dbnce_fltr_bypass:1;
|
||||
/** exchg_pins_override : R/W; bitpos: [5]; default: 0;
|
||||
* Enable software controlle USB D+ D- exchange
|
||||
*/
|
||||
uint32_t exchg_pins_override:1;
|
||||
/** exchg_pins : R/W; bitpos: [6]; default: 0;
|
||||
* USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
|
||||
*/
|
||||
uint32_t exchg_pins:1;
|
||||
/** vrefh : R/W; bitpos: [8:7]; default: 0;
|
||||
* Control single-end input high threshold,1.76V to 2V, step 80mV.
|
||||
*/
|
||||
uint32_t vrefh:2;
|
||||
/** vrefl : R/W; bitpos: [10:9]; default: 0;
|
||||
* Control single-end input low threshold,0.8V to 1.04V, step 80mV.
|
||||
*/
|
||||
uint32_t vrefl:2;
|
||||
/** vref_override : R/W; bitpos: [11]; default: 0;
|
||||
* Enable software controlle input threshold.
|
||||
*/
|
||||
uint32_t vref_override:1;
|
||||
/** pad_pull_override : R/W; bitpos: [12]; default: 0;
|
||||
* Enable software controlle USB D+ D- pullup pulldown.
|
||||
*/
|
||||
uint32_t pad_pull_override:1;
|
||||
/** dp_pullup : R/W; bitpos: [13]; default: 0;
|
||||
* Controlle USB D+ pullup.
|
||||
*/
|
||||
uint32_t dp_pullup:1;
|
||||
/** dp_pulldown : R/W; bitpos: [14]; default: 0;
|
||||
* Controlle USB D+ pulldown.
|
||||
*/
|
||||
uint32_t dp_pulldown:1;
|
||||
/** dm_pullup : R/W; bitpos: [15]; default: 0;
|
||||
* Controlle USB D+ pullup.
|
||||
*/
|
||||
uint32_t dm_pullup:1;
|
||||
/** dm_pulldown : R/W; bitpos: [16]; default: 0;
|
||||
* Controlle USB D+ pulldown.
|
||||
*/
|
||||
uint32_t dm_pulldown:1;
|
||||
/** pullup_value : R/W; bitpos: [17]; default: 0;
|
||||
* Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
|
||||
*/
|
||||
uint32_t pullup_value:1;
|
||||
/** usb_pad_enable : R/W; bitpos: [18]; default: 0;
|
||||
* Enable USB pad function.
|
||||
*/
|
||||
uint32_t usb_pad_enable:1;
|
||||
/** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
|
||||
* Force ahb clock always on.
|
||||
*/
|
||||
uint32_t ahb_clk_force_on:1;
|
||||
/** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
|
||||
* Force phy clock always on.
|
||||
*/
|
||||
uint32_t phy_clk_force_on:1;
|
||||
/** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
|
||||
* Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
|
||||
*/
|
||||
uint32_t phy_tx_edge_sel:1;
|
||||
/** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
|
||||
* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
uint32_t dfifo_force_pu:1;
|
||||
uint32_t reserved_23:8;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Disable auto clock gating of CSR registers.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_otg_conf_reg_t;
|
||||
|
||||
/** Type of test_conf register
|
||||
* TEST relative configuration registers.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** test_enable : R/W; bitpos: [0]; default: 0;
|
||||
* Enable to test the USB pad.
|
||||
*/
|
||||
uint32_t test_enable:1;
|
||||
/** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
|
||||
* USB pad oen in test.
|
||||
*/
|
||||
uint32_t test_usb_wrap_oe:1;
|
||||
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
|
||||
* USB D+ tx value in test.
|
||||
*/
|
||||
uint32_t test_tx_dp:1;
|
||||
/** test_tx_dm : R/W; bitpos: [3]; default: 0;
|
||||
* USB D- tx value in test.
|
||||
*/
|
||||
uint32_t test_tx_dm:1;
|
||||
/** test_rx_rcv : RO; bitpos: [4]; default: 0;
|
||||
* USB differential rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_rcv:1;
|
||||
/** test_rx_dp : RO; bitpos: [5]; default: 0;
|
||||
* USB D+ rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_dp:1;
|
||||
/** test_rx_dm : RO; bitpos: [6]; default: 0;
|
||||
* USB D- rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_dm:1;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_test_conf_reg_t;
|
||||
|
||||
/** Type of date register
|
||||
* Date register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
|
||||
* Date register.
|
||||
*/
|
||||
uint32_t usb_wrap_date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_date_reg_t;
|
||||
|
||||
|
||||
typedef struct usb_wrap_dev_t {
|
||||
volatile usb_wrap_otg_conf_reg_t otg_conf;
|
||||
volatile usb_wrap_test_conf_reg_t test_conf;
|
||||
uint32_t reserved_008[253];
|
||||
volatile usb_wrap_date_reg_t date;
|
||||
} usb_wrap_dev_t;
|
||||
|
||||
extern usb_wrap_dev_t USB_WRAP;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user