mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-03 03:31:41 +03:00
Merge branch 'refactor/remove_redundant_rom_cache_dependency' into 'master'
cache: remove redundant rom cache dependency in bootloader Closes IDF-4523 See merge request espressif/esp-idf!17077
This commit is contained in:
Armando (Dou Yiwen)
@@ -143,6 +143,10 @@ config SOC_ADC_MAX_BITWIDTH
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int
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default 12
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config SOC_SHARED_IDCACHE_SUPPORTED
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bool
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default y
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config SOC_CPU_BREAKPOINTS_NUM
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int
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default 2
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@@ -0,0 +1,45 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _CACHE_MEMORY_H_
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#define _CACHE_MEMORY_H_
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define IRAM0_CACHE_ADDRESS_LOW 0x400D0000
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#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
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#define IRAM1_CACHE_ADDRESS_LOW 0x40400000
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#define IRAM1_CACHE_ADDRESS_HIGH 0x40800000
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#define IROM0_CACHE_ADDRESS_LOW 0x40800000
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#define IROM0_CACHE_ADDRESS_HIGH 0x40C00000
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#define DRAM1_CACHE_ADDRESS_LOW 0x3F800000
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#define DRAM1_CACHE_ADDRESS_HIGH 0x3FC00000
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#define DROM0_CACHE_ADDRESS_LOW 0x3F400000
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#define DROM0_CACHE_ADDRESS_HIGH 0x3F800000
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#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
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#define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr)
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#define ADDRESS_IN_IROM0_CACHE(vaddr) ADDRESS_IN_BUS(IROM0_CACHE, vaddr)
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#define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr)
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#define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr)
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#ifdef __cplusplus
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}
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#endif
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#endif /*_CACHE_MEMORY_H_ */
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@@ -121,6 +121,9 @@
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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#endif
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/*-------------------------- CACHE CAPS --------------------------------------*/
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#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
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/*-------------------------- CPU CAPS ----------------------------------------*/
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#define SOC_CPU_BREAKPOINTS_NUM 2
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#define SOC_CPU_WATCHPOINTS_NUM 2
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@@ -67,10 +67,6 @@ config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
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bool
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default n
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config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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bool
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default y
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config SOC_FLASH_ENCRYPTION_XTS_AES
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bool
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default y
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@@ -147,6 +143,10 @@ config SOC_BROWNOUT_RESET_SUPPORTED
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bool
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default y
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config SOC_SHARED_IDCACHE_SUPPORTED
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bool
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default y
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config SOC_CPU_BREAKPOINTS_NUM
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int
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default 2
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+29
-8
@@ -6,16 +6,18 @@
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#ifndef _CACHE_MEMORY_H_
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#define _CACHE_MEMORY_H_
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "esp32c2/rom/cache.h"
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//TODO IDF-3821, for now it's always 64KB
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#define MMU_PAGE_MODE 2
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/*IRAM0 is connected with Cache IBUS0*/
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#define MMU_PAGE_MODE MMU_Get_Page_Mode()
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#define IRAM0_ADDRESS_LOW 0x40000000
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#define IRAM0_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH
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#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
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@@ -51,6 +53,7 @@ extern "C" {
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#define CACHE_DBUS_MMU_START 0
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#define CACHE_DBUS_MMU_END 0x100
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//TODO, remove these cache function dependencies
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#define CACHE_IROM_MMU_START 0
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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@@ -68,6 +71,7 @@ extern "C" {
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#define MMU_BUS_SIZE(i) 0x100
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#define MMU_INVALID BIT(6)
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#define MMU_VALID 0
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#define MMU_TYPE 0
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#define MMU_ACCESS_FLASH 0
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@@ -79,12 +83,29 @@ extern "C" {
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#define MMU_TABLE_INVALID_VAL MMU_INVALID
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#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
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#define MMU_ADDRESS_MASK (MMU_TABLE_INVALID_VAL - 1)
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#define MMU_PAGE_SIZE (0x4000 << (MMU_PAGE_MODE))
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#define INVALID_PHY_PAGE (MMU_PAGE_SIZE - 1)
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/**
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* MMU entry valid bit mask for mapping value. For an entry:
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* valid bit + value bits
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* valid bit is BIT(6), so value bits are 0x3f
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*/
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#define MMU_VALID_VAL_MASK 0x3f
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/**
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* Helper macro to make a MMU entry invalid
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* Check this! IDF-3821
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*/
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#define INVALID_PHY_PAGE 0x7f
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/**
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* Max MMU entry num.
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* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
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* 64 * 64KB, means MMU can map 4MB at most
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*/
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#define MMU_MAX_ENTRY_NUM 64
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/**
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* This is the mask used for mapping. e.g.:
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* 0x4200_0000 & MMU_VADDR_MASK
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*/
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#define MMU_VADDR_MASK ((0x100000 << (MMU_PAGE_MODE)) - 1)
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#define BUS_ADDR_SIZE (0x100000 << (MMU_PAGE_MODE))
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#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
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#define BUS_PMS_MASK 0xffffff
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#define CACHE_ICACHE_LOW_SHIFT 0
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@@ -6,7 +6,7 @@
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#pragma once
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#include <stdint.h>
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#include "soc/cache_memory.h"
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#include "soc/ext_mem_defs.h"
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#include "soc/soc.h"
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#ifdef __cplusplus
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@@ -21,7 +21,7 @@ extern "C" {
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#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
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#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
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#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
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#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
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#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
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#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
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#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
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#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
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@@ -41,7 +41,6 @@
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#define SOC_RTC_FAST_MEM_SUPPORTED 0
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#define SOC_RTC_SLOW_MEM_SUPPORTED 0
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#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 0
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#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES 1
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/*-------------------------- AES CAPS -----------------------------------------*/
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@@ -79,6 +78,9 @@
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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||||
#define SOC_BROWNOUT_RESET_SUPPORTED 1
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/*-------------------------- CACHE CAPS --------------------------------------*/
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#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
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/*-------------------------- CPU CAPS ----------------------------------------*/
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#define SOC_CPU_BREAKPOINTS_NUM 2
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#define SOC_CPU_WATCHPOINTS_NUM 2
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@@ -75,10 +75,6 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
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bool
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default y
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config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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bool
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default y
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config SOC_RTC_FAST_MEM_SUPPORTED
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bool
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default y
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@@ -191,6 +187,10 @@ config SOC_BROWNOUT_RESET_SUPPORTED
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bool
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default y
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config SOC_SHARED_IDCACHE_SUPPORTED
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bool
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default y
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config SOC_CPU_BREAKPOINTS_NUM
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int
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default 8
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+24
-4
@@ -6,6 +6,8 @@
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#ifndef _CACHE_MEMORY_H_
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#define _CACHE_MEMORY_H_
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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@@ -43,6 +45,7 @@ extern "C" {
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#define CACHE_DBUS_MMU_START 0
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#define CACHE_DBUS_MMU_END 0x200
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//TODO, remove these cache function dependencies
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#define CACHE_IROM_MMU_START 0
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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@@ -60,6 +63,7 @@ extern "C" {
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#define MMU_BUS_SIZE(i) 0x200
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#define MMU_INVALID BIT(8)
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#define MMU_VALID 0
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#define MMU_TYPE 0
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#define MMU_ACCESS_FLASH 0
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@@ -71,12 +75,28 @@ extern "C" {
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#define MMU_TABLE_INVALID_VAL 0x100
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#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
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#define MMU_ADDRESS_MASK 0xff
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#define MMU_PAGE_SIZE 0x10000
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/**
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* MMU entry valid bit mask for mapping value. For an entry:
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* valid bit + value bits
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* valid bit is BIT(8), so value bits are 0xff
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*/
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#define MMU_VALID_VAL_MASK 0xff
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/**
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* Helper macro to make a MMU entry invalid
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*/
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#define INVALID_PHY_PAGE 0xffff
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/**
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* Max MMU entry num.
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* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
|
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* 256 * 64KB, means MMU can map 16MB at most
|
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*/
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#define MMU_MAX_ENTRY_NUM 256
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/**
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* This is the mask used for mapping. e.g.:
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* 0x4200_0000 & MMU_VADDR_MASK
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*/
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#define MMU_VADDR_MASK 0x7FFFFF
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#define BUS_ADDR_SIZE 0x800000
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#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
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#define CACHE_ICACHE_LOW_SHIFT 0
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#define CACHE_ICACHE_HIGH_SHIFT 2
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@@ -1,20 +1,12 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
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#include <stdint.h>
|
||||
#include "soc/cache_memory.h"
|
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#include "soc/ext_mem_defs.h"
|
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#include "soc/soc.h"
|
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|
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#ifdef __cplusplus
|
||||
@@ -29,7 +21,7 @@ extern "C" {
|
||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
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#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
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#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
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#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
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#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
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#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
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#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
|
||||
@@ -43,7 +43,6 @@
|
||||
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
|
||||
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
|
||||
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
|
||||
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
|
||||
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
|
||||
@@ -93,6 +92,9 @@
|
||||
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
|
||||
#define SOC_BROWNOUT_RESET_SUPPORTED 1
|
||||
|
||||
/*-------------------------- CACHE CAPS --------------------------------------*/
|
||||
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
|
||||
|
||||
/*-------------------------- CPU CAPS ----------------------------------------*/
|
||||
#define SOC_CPU_BREAKPOINTS_NUM 8
|
||||
#define SOC_CPU_WATCHPOINTS_NUM 8
|
||||
|
||||
@@ -55,10 +55,6 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TEMP_SENSOR_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
@@ -167,6 +163,10 @@ config SOC_BROWNOUT_RESET_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SHARED_IDCACHE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CPU_BREAKPOINTS_NUM
|
||||
int
|
||||
default 8
|
||||
|
||||
+24
-5
@@ -6,6 +6,8 @@
|
||||
#ifndef _CACHE_MEMORY_H_
|
||||
#define _CACHE_MEMORY_H_
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@@ -35,6 +37,7 @@ extern "C" {
|
||||
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
|
||||
|
||||
//TODO, remove these cache function dependencies
|
||||
#define CACHE_IBUS 0
|
||||
#define CACHE_IBUS_MMU_START 0
|
||||
#define CACHE_IBUS_MMU_END 0x200
|
||||
@@ -60,6 +63,7 @@ extern "C" {
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#define MMU_INVALID BIT(8)
|
||||
#define MMU_VALID 0
|
||||
#define MMU_TYPE 0
|
||||
#define MMU_ACCESS_FLASH 0
|
||||
|
||||
@@ -71,12 +75,27 @@ extern "C" {
|
||||
|
||||
#define MMU_TABLE_INVALID_VAL 0x100
|
||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
||||
#define MMU_ADDRESS_MASK 0xff
|
||||
#define MMU_PAGE_SIZE 0x10000
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(8), so value bits are 0xff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0xff
|
||||
/**
|
||||
* Helper macro to make a MMU entry invalid
|
||||
*/
|
||||
#define INVALID_PHY_PAGE 0xffff
|
||||
|
||||
#define BUS_ADDR_SIZE 0x800000
|
||||
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
|
||||
/**
|
||||
* Max MMU entry num.
|
||||
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
|
||||
* 256 * 64KB, means MMU can map 16MB at most
|
||||
*/
|
||||
#define MMU_MAX_ENTRY_NUM 256
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK 0x7fffff
|
||||
|
||||
#define CACHE_ICACHE_LOW_SHIFT 0
|
||||
#define CACHE_ICACHE_HIGH_SHIFT 2
|
||||
@@ -1,20 +1,12 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/cache_memory.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -29,7 +21,7 @@ extern "C" {
|
||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
||||
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
|
||||
@@ -46,7 +46,6 @@
|
||||
#define SOC_SUPPORTS_SECURE_DL_MODE 1
|
||||
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
|
||||
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
|
||||
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
|
||||
#define SOC_TEMP_SENSOR_SUPPORTED 1
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
|
||||
@@ -95,6 +94,9 @@
|
||||
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
|
||||
#define SOC_BROWNOUT_RESET_SUPPORTED 1
|
||||
|
||||
/*-------------------------- CACHE CAPS --------------------------------------*/
|
||||
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
|
||||
|
||||
/*-------------------------- CPU CAPS ----------------------------------------*/
|
||||
#define SOC_CPU_BREAKPOINTS_NUM 8
|
||||
#define SOC_CPU_WATCHPOINTS_NUM 8
|
||||
|
||||
@@ -79,10 +79,6 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TEMP_SENSOR_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
+20
-5
@@ -6,6 +6,8 @@
|
||||
#ifndef _CACHE_MEMORY_H_
|
||||
#define _CACHE_MEMORY_H_
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@@ -93,6 +95,7 @@ extern "C" {
|
||||
#define MMU_BUS_SIZE 0x100
|
||||
|
||||
#define MMU_INVALID BIT(14)
|
||||
#define MMU_VALID 0
|
||||
#define MMU_ACCESS_FLASH BIT(15)
|
||||
#define MMU_ACCESS_SPIRAM BIT(16)
|
||||
|
||||
@@ -101,11 +104,23 @@ extern "C" {
|
||||
|
||||
#define MMU_TABLE_INVALID_VAL 0x4000
|
||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
||||
#define MMU_ADDRESS_MASK 0x3fff
|
||||
#define MMU_PAGE_SIZE 0x10000
|
||||
|
||||
#define BUS_ADDR_SIZE 0x400000
|
||||
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(14), so value bits are 0x3fff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0x3fff
|
||||
/**
|
||||
* Max MMU entry num.
|
||||
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
|
||||
* 16384 * 64KB, means MMU can map 1GB at most
|
||||
*/
|
||||
#define MMU_MAX_ENTRY_NUM 16384
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK 0x3FFFFF
|
||||
#define BUS_NUM_MASK 0x3
|
||||
|
||||
#define CACHE_MEMORY_BANK_SIZE 8192
|
||||
@@ -1,20 +1,12 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/cache_memory.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -29,7 +21,7 @@ extern "C" {
|
||||
#define SOC_MMU_DROM0_PAGES_START (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
||||
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
|
||||
|
||||
@@ -58,7 +58,6 @@
|
||||
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
|
||||
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
|
||||
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
|
||||
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
|
||||
#define SOC_TEMP_SENSOR_SUPPORTED 1
|
||||
#define SOC_CACHE_SUPPORT_WRAP 1
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
|
||||
|
||||
+24
-5
@@ -5,6 +5,8 @@
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@@ -42,6 +44,7 @@ extern "C" {
|
||||
#define CACHE_DBUS_MMU_START 0
|
||||
#define CACHE_DBUS_MMU_END 0x800
|
||||
|
||||
//TODO, remove these cache function dependencies
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
@@ -59,6 +62,7 @@ extern "C" {
|
||||
#define MMU_BUS_SIZE(i) 0x800
|
||||
|
||||
#define MMU_INVALID BIT(14)
|
||||
#define MMU_VALID 0
|
||||
#define MMU_TYPE BIT(15)
|
||||
#define MMU_ACCESS_FLASH 0
|
||||
#define MMU_ACCESS_SPIRAM BIT(15)
|
||||
@@ -71,12 +75,27 @@ extern "C" {
|
||||
|
||||
#define MMU_TABLE_INVALID_VAL 0x4000
|
||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
||||
#define MMU_ADDRESS_MASK 0x3fff
|
||||
#define MMU_PAGE_SIZE 0x10000
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(14), so value bits are 0x3fff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0x3fff
|
||||
/**
|
||||
* Helper macro to make a MMU entry invalid
|
||||
*/
|
||||
#define INVALID_PHY_PAGE 0xffff
|
||||
|
||||
#define BUS_ADDR_SIZE 0x2000000
|
||||
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
|
||||
/**
|
||||
* Max MMU entry num.
|
||||
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
|
||||
* 16384 * 64KB, means MMU can map 1GB at most
|
||||
*/
|
||||
#define MMU_MAX_ENTRY_NUM 16384
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK 0x1FFFFFF
|
||||
|
||||
#define CACHE_ICACHE_LOW_SHIFT 0
|
||||
#define CACHE_ICACHE_HIGH_SHIFT 2
|
||||
@@ -1,20 +1,12 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/cache_memory.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -29,7 +21,7 @@ extern "C" {
|
||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
||||
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
|
||||
Reference in New Issue
Block a user