diff --git a/components/esp_hw_support/port/esp32s31/esp_cpu_intr.c b/components/esp_hw_support/port/esp32s31/esp_cpu_intr.c
index f8fc9177cec..35ef0389c5f 100644
--- a/components/esp_hw_support/port/esp32s31/esp_cpu_intr.c
+++ b/components/esp_hw_support/port/esp32s31/esp_cpu_intr.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,16 +7,15 @@
 #include "esp_cpu.h"
 #include "esp_riscv_intr.h"
 
-// TODO: [ESP32S31] IDF-14665
-
 void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
 {
     /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
      * interrupts, all the other lines starting from 16 and above can be used by external peripheral.
      *
-     * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts in the
-     * interrupt allocator (INT_MUX_DISABLED_INTNO) */
-    const uint32_t rsvd_mask = BIT(6);
+     * Reserve interrupt line 1 for the Wifi controller.
+     * Reserve interrupt line 6 since it is used for disabling interrupts in the interrupt allocator (INT_MUX_DISABLED_INTNO)
+     */
+    const uint32_t rsvd_mask = BIT(1) | BIT(6);
 
     intr_desc_ret->priority = 1;
     intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
diff --git a/components/hal/esp32s31/include/hal/crosscore_int_ll.h b/components/hal/esp32s31/include/hal/crosscore_int_ll.h
index eb32c812834..967f217bbf1 100644
--- a/components/hal/esp32s31/include/hal/crosscore_int_ll.h
+++ b/components/hal/esp32s31/include/hal/crosscore_int_ll.h
@@ -12,7 +12,6 @@
 extern "C" {
 #endif
 
-// TODO: [ESP32S31] IDF-14666
 /**
  * @brief Clear the crosscore interrupt that just occurred on the current core
  */
diff --git a/components/soc/esp32s31/include/soc/clic_reg.h b/components/soc/esp32s31/include/soc/clic_reg.h
index 8b7f9fd0c6a..92aa4861e5a 100644
--- a/components/soc/esp32s31/include/soc/clic_reg.h
+++ b/components/soc/esp32s31/include/soc/clic_reg.h
@@ -10,8 +10,6 @@
 extern "C" {
 #endif
 
-// TODO: to be checked IDF-14666
-
 #define NLBITS                   3
 #define CLIC_EXT_INTR_NUM_OFFSET 16
 #define DUALCORE_CLIC_CTRL_OFF   0x10000
diff --git a/components/soc/esp32s31/include/soc/interrupt_reg.h b/components/soc/esp32s31/include/soc/interrupt_reg.h
index d18972a80e6..bd841f9713d 100644
--- a/components/soc/esp32s31/include/soc/interrupt_reg.h
+++ b/components/soc/esp32s31/include/soc/interrupt_reg.h
@@ -12,8 +12,6 @@
 extern "C" {
 #endif
 
-// TODO: to be checked IDF-14666
-
 /**
  * ESP32S31 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y)
  *