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refactor(spi_flash): move os layer to esp_mspi and chip configs to spi_flash

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Also fixes the implicit dependency on esp_partition.
This commit is contained in:
armando
2026-09-09 14:17:00 +08:00
committed by Armando (Dou Yiwen)
parent c565262ded
commit 6e3abd12a1
197 changed files with 1227 additions and 1139 deletions
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components/esp_psram/CMakeLists.txt
+1 -1
View File
@@ -10,7 +10,7 @@ if(CONFIG_SOC_SPIRAM_XIP_SUPPORTED)
list(APPEND includes xip_impl/include)
endif()
set(priv_requires heap spi_flash esp_mm esp_hal_mspi esp_hal_gpio)
set(priv_requires heap esp_mspi esp_mm esp_hal_mspi esp_hal_gpio)
if(${target} STREQUAL "esp32")
list(APPEND priv_requires bootloader_support esp_driver_gpio)
endif()
components/esp_psram/esp32s3/esp_psram_impl_octal.c
+14 -1
View File
@@ -23,6 +23,7 @@
#include "esp_private/spi_flash_os.h"
#include "esp_private/mspi_timing_tuning.h"
#include "esp_private/esp_gpio_reserve.h"
#include "esp_private/opi_flash_private.h"
#define OPI_PSRAM_SYNC_READ 0x0000
#define OPI_PSRAM_SYNC_WRITE 0x8080
@@ -336,6 +337,18 @@ static void s_configure_psram_ecc(void)
#endif
}
static void s_set_flash_vendor_required_regs(void)
{
if (spi_flash_is_octal_mode_enabled()) {
esp_opiflash_set_required_regs();
SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 1, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
} else {
//Flash chip requires MSPI specifically, call this function to set them
// Set back MSPI registers after Octal PSRAM initialization.
SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 0, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
}
}
esp_err_t esp_psram_impl_enable(void)
{
s_init_psram_pins();
@@ -386,7 +399,7 @@ esp_err_t esp_psram_impl_enable(void)
*/
spi_flash_set_rom_required_regs();
//Flash chip requires MSPI specifically, call this function to set them
spi_flash_set_vendor_required_regs();
s_set_flash_vendor_required_regs();
s_config_psram_spi_phases();
return ESP_OK;