mirror of
https://github.com/espressif/esp-idf.git
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refactor(spi_flash): move os layer to esp_mspi and chip configs to spi_flash
Also fixes the implicit dependency on esp_partition.
This commit is contained in:
armando
committed by
Armando (Dou Yiwen)
Armando (Dou Yiwen)
parent
c565262ded
commit
6e3abd12a1
@@ -0,0 +1,105 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_err.h"
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Structure for flash dummy bits.
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* For some flash chips, dummy bits are configurable under different conditions.
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*/
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typedef struct {
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uint8_t dio_dummy;
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uint8_t dout_dummy;
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uint8_t qio_dummy;
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uint8_t qout_dummy;
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uint8_t fastrd_dummy;
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} spi_flash_hpm_dummy_conf_t;
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typedef enum {
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SPI_FLASH_HPM_CMD_NEEDED, // Means that in the certain condition, flash needs to enter the high performance mode by command.
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SPI_FLASH_HPM_DUMMY_NEEDED, // Means that in the certain condition, flash needs to enter the high performance mode by adjusting dummy.
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SPI_FLASH_HPM_WRITE_SR_NEEDED, // Means that in the certain condition, flash needs to enter the high performance mode by writing status register.
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SPI_FLASH_HPM_UNNEEDED, // Means that flash doesn't need to enter the high performance mode.
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SPI_FLASH_HPM_BEYOND_LIMIT, // Means that flash has no capability to meet that condition.
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} spi_flash_requirement_t;
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typedef void (*spi_flash_hpm_enable_fn_t)(void);
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typedef esp_err_t (*spi_flash_hpf_check_fn_t)(void);
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typedef void (*spi_flash_get_chip_dummy_fn_t)(spi_flash_hpm_dummy_conf_t *dummy_conf);
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typedef esp_err_t (*spi_flash_hpm_probe_fn_t)(uint32_t flash_id);
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typedef spi_flash_requirement_t (*spi_flash_hpm_chip_requirement_check_t)(uint32_t flash_id, uint32_t freq_mhz, int voltage_mv, int temperature);
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typedef struct __attribute__((packed))
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{
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const char *method; /* Flash HPM method */
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spi_flash_hpm_probe_fn_t probe;
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spi_flash_hpm_chip_requirement_check_t chip_hpm_requirement_check;
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spi_flash_hpm_enable_fn_t flash_hpm_enable;
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spi_flash_hpf_check_fn_t flash_hpf_check;
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spi_flash_get_chip_dummy_fn_t flash_get_dummy;
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} spi_flash_hpm_info_t;
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/**
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* @brief Enum for user to select valid wrap size.
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*/
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typedef enum {
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FLASH_WRAP_SIZE_8B = 8,
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FLASH_WRAP_SIZE_16B = 16,
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FLASH_WRAP_SIZE_32B = 32,
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FLASH_WRAP_SIZE_64B = 64,
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} spi_flash_wrap_size_t;
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/**
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* @brief Probe flash wrap method
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*
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* @param flash_id Flash chip ID
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*
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* @return ESP_OK: If succeed
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*/
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typedef esp_err_t (*spi_flash_wrap_probe_fn_t)(uint32_t flash_id);
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/**
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* @brief Set flash wrap
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*
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* @param wrap_size: wrap_size
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*
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* @return ESP_OK: If succeed
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*/
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typedef esp_err_t (*spi_flash_wrap_set_fn_t)(spi_flash_wrap_size_t wrap_size);
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/**
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* @brief Clear flash wrap.
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*
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* @return ESP_OK: If succeed
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*/
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typedef esp_err_t (*spi_flash_wrap_clr_fn_t)(void);
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typedef struct __attribute__((packed))
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{
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const char *method;
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spi_flash_wrap_probe_fn_t probe;
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spi_flash_wrap_set_fn_t chip_wrap_set;
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spi_flash_wrap_clr_fn_t chip_wrap_clr;
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} spi_flash_wrap_info_t;
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/**
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* Array of known flash chips and method to enable flash high performance mode.
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*
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* Users can override this array.
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*/
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extern const spi_flash_hpm_info_t __attribute__((weak)) spi_flash_hpm_enable_list[];
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,124 @@
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/*
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* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include "esp_err.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* This header file contains declarations of cache manipulation functions
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* used both in flash_ops.c and flash_mmap.c.
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*
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* These functions are considered internal and are not designed to be called from applications.
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*/
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// Init mutex protecting access to spi_flash_* APIs
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void spi_flash_init_lock(void);
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// Take mutex protecting access to spi_flash_* APIs
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void spi_flash_op_lock(void);
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// Release said mutex
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void spi_flash_op_unlock(void);
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// Suspend the scheduler on both CPUs, disable cache.
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// Contrary to its name this doesn't do anything with interrupts, yet.
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// Interrupt disabling capability will be added once we implement
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// interrupt allocation API.
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void spi_flash_disable_interrupts_caches_and_other_cpu(void);
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// Enable cache, enable interrupts (to be added in future), resume scheduler
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void spi_flash_enable_interrupts_caches_and_other_cpu(void);
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// Disables non-IRAM interrupt handlers on current CPU and caches on both CPUs.
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// This function is implied to be called when other CPU is not running or running code from IRAM.
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void spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void);
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// Enable cache, enable interrupts on current CPU.
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// This function is implied to be called when other CPU is not running or running code from IRAM.
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void spi_flash_enable_interrupts_caches_no_os(void);
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// Mark the pages containing a flash region as having been
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// erased or written to. This means the flash cache needs
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// to be evicted before these pages can be flash_mmap()ed again,
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// as they may contain stale data
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//
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// Only call this while holding spi_flash_op_lock()
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// Returns true if cache was flushed, false otherwise
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bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length);
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//config cache mode
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#if !CONFIG_IDF_TARGET_ESP32
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//config instrcutin cache size and cache block size by menuconfig
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void esp_config_instruction_cache_mode(void);
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//config data cache size and cache block size by menuconfig
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void esp_config_data_cache_mode(void);
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#endif
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#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
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/**
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* @brief enable cache wrap mode for i/d shared cache
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* @param icache_wrap_enable enable cache wrap mode for i/d shared cache
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* @return ESP_OK on success, ESP_FAIL otherwise
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*/
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esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable);
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#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief enable cache wrap mode for instruction cache and data cache
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* @param icache_wrap_enable enable cache wrap mode for i cache
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* @param dcache_wrap_enable enable cache wrap mode for d cache
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* @return ESP_OK on success, ESP_FAIL otherwise
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*/
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esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable);
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#endif
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/** @brief Check at runtime if flash cache is enabled on both CPUs
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*
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* @return true if both CPUs have flash cache enabled, false otherwise.
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*/
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bool spi_flash_cache_enabled(void);
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/**
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* @brief Re-enable cache for the core defined as cpuid parameter.
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*
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* @param cpuid the core number to enable instruction cache for
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*/
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void spi_flash_enable_cache(uint32_t cpuid);
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/**
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* @brief Suspend the Cache access to external memory.
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*
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* @note Callers must disable branch prediction around this window when
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* SOC_BRANCH_PREDICTOR_SUPPORTED, otherwise speculative fetches can
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* raise cache access-fail errors while the cache is suspended.
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*
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* @param cpuid the core number to enable the cache for, meaning less on shared cache.
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* @param saved_state Cache status hold by hal (Used only on ROM impl. in idf, this param unused)
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*/
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void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state);
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/**
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* @brief Resume the Cache access to external memory.
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*
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* @note Callers that disabled branch prediction for the suspend window must
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* re-enable it after this call when SOC_BRANCH_PREDICTOR_SUPPORTED.
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*
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* @param cpuid the core number to enable the cache for, meaning less on shared cache.
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* @param saved_state Cache status hold by hal (Used only on ROM impl. in idf, this param unused)
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*/
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void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,318 @@
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/*
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* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* System level MSPI APIs (private)
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "esp_rom_spiflash.h"
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#include "esp_err.h"
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#include "esp_bit_defs.h"
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#include "soc/soc_caps.h"
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#include "soc/clk_tree_defs.h"
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#include "hal/spi_flash_hal.h"
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#include "esp_private/spi_share_hw_ctrl.h"
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#include "esp_flash_chips/spi_flash_override.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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//-------------------Chip Related------------------//
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// Type of MSPI IO
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typedef enum {
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ESP_MSPI_IO_CLK = 0,
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ESP_MSPI_IO_Q,
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ESP_MSPI_IO_D,
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ESP_MSPI_IO_CS0, /* cs for spi flash */
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ESP_MSPI_IO_HD,
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ESP_MSPI_IO_WP,
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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ESP_MSPI_IO_DQS,
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ESP_MSPI_IO_D4,
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ESP_MSPI_IO_D5,
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ESP_MSPI_IO_D6,
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ESP_MSPI_IO_D7,
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#endif // SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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#if CONFIG_SPIRAM
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ESP_MSPI_IO_CS1, /* cs for spi ram */
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#endif
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ESP_MSPI_IO_MAX, /* Maximum IO MSPI occupied */
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} esp_mspi_io_t;
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/**
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* @brief To setup Flash chip
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*/
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esp_err_t spi_flash_init_chip_state(void);
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/**
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* @brief Check if octal flash mode is enabled in eFuse
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*
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* @return True if flash is in octal mode, false else
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*/
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bool spi_flash_is_octal_mode_enabled(void);
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/**
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* @brief To initislize the MSPI pins
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*/
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void esp_mspi_pin_init(void);
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/**
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* @brief Reserve MSPI IOs
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*/
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void esp_mspi_pin_reserve(void);
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/**
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* @brief Get the number of the GPIO corresponding to the given MSPI io
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*
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* @param[in] io MSPI io
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*
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* @return MSPI IO number
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*/
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uint8_t esp_mspi_get_io(esp_mspi_io_t io);
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/**
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* @brief Set SPI1 registers to make ROM functions work
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* @note This function is used for setting SPI1 registers to the state that ROM SPI functions work
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*/
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void spi_flash_set_rom_required_regs(void);
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/**
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* @brief Should be only used by SPI1 Flash driver to know the necessary timing registers
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* @param out_timing_config Pointer to timing_tuning parameters.
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*/
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void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config);
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/**
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* @brief Get the knowledge if the Flash timing is tuned or not
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*/
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bool spi_flash_timing_is_tuned(void);
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/**
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* @brief Set Flash chip specifically required MSPI register settings here
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*/
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void spi_flash_set_vendor_required_regs(void);
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/**
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* @brief Judge whether need to reset flash when brownout.
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* Set` flash_brownout_needs_reset` inside the function if really need reset.
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*/
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void spi_flash_needs_reset_check(void);
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/**
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* @brief Set flag to reset flash. set when erase chip or program chip
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*
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* @param bool status. True if flash is eraing. False if flash is not erasing.
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*
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* @return None.
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*/
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void spi_flash_set_erasing_flag(bool status);
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/**
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* @brief Judge whether need to reset flash when brownout.
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*
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* @return true if need reset, otherwise false.
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*/
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bool spi_flash_brownout_need_reset(void);
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/**
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* @brief Check whether esp-chip supports 32bit address properly
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*
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* @return ESP_OK for supported, ESP_ERR_NOT_SUPPORTED for not supported
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*/
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esp_err_t esp_mspi_32bit_address_flash_feature_check(void);
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#if CONFIG_SPI_FLASH_HPM_ON
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/**
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* @brief Enable SPI flash high performance mode.
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*
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* @note 1. When `CONFIG_SPI_FLASH_HPM_ON` is True, caller can always call this function without taking whether the used
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* frequency falls into the HPM range into consideration.
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* 2. However, caller shouldn't attempt to call this function on Octal flash. `CONFIG_SPI_FLASH_HPM_ON` may be
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* True when `CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT && !CONFIG_ESPTOOLPY_OCT_FLASH`
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*
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* @return ESP_OK if success.
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*/
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esp_err_t spi_flash_enable_high_performance_mode(void);
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/**
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* @brief Get the flash dummy through this function
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* This can be used when one flash has several dummy configurations to enable the high performance mode.
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* @note Don't forget to subtract one when assign to the register of mspi e.g. if the value you get is 4, (4-1=3) should be assigned to the register.
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*
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* @return Pointer to spi_flash_hpm_dummy_conf_t.
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*/
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const spi_flash_hpm_dummy_conf_t *spi_flash_hpm_get_dummy(void);
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/**
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* @brief Used to judge whether flash works under HPM mode with dummy adjustment.
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*
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* @return true Yes, and work under HPM with adjusting dummy. Otherwise, false.
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*/
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bool spi_flash_hpm_dummy_adjust(void);
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#endif //CONFIG_SPI_FLASH_HPM_ON
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#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
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//-------------------DPD Related------------------//
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/**
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* @brief Structure holding DPD function pointers
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*/
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typedef struct {
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esp_err_t (*enter_dpd)(void);
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esp_err_t (*exit_dpd)(void);
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} spi_flash_dpd_funcs_t;
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/**
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* @brief Register DPD function pointers
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*
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* @param dpd_funcs Pointer to structure holding DPD function pointers
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* @return ESP_OK on success
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*/
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esp_err_t spi_flash_dpd_register_funcs(spi_flash_dpd_funcs_t *dpd_funcs);
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/**
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* @brief Get the duration of entering deep power-down mode.
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*
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* @return Entering deep power-down mode time(tDp), in microseconds.
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*/
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uint32_t spi_flash_dpd_get_enter_duration(void);
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/**
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* @brief Get the duration of exiting deep power-down mode.
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*
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* @return Exiting deep power-down mode time(tRES1), in microseconds.
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*/
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uint32_t spi_flash_dpd_get_exit_duration(void);
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/**
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* @brief Enable or disable SPI flash deep power-down mode.
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*
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* @param enable True to enter deep power-down mode, false to exit.
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* @param wait_delay If true, wait tDP (enter) or tRES1 (exit) after the command.
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* If false, skip the delay; the caller must ensure timing is met elsewhere
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*
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* @note If using self-provided flash (not the chip's factory-default flash), consult its datasheet to use this API safely.
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*
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* @return ESP_OK if success.
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*/
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esp_err_t spi_flash_enable_deep_power_down_mode(bool enable, bool wait_delay);
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#endif
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#if SOC_SPI_MEM_SUPPORT_WRAP
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/**
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* @brief set wrap size of flash
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*
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* @param wrap_size: wrap mode support disable, 16 32, 64 byte
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*
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* @return esp_err_t : ESP_OK for successful.
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*
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*/
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esp_err_t spi_flash_wrap_enable(spi_flash_wrap_size_t wrap_size);
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/**
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* @brief Probe flash wrap method
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*
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||||
* @return esp_err_t: ESP_OK for success
|
||||
*/
|
||||
esp_err_t spi_flash_wrap_probe(void);
|
||||
|
||||
/**
|
||||
* @brief disable cache wrap
|
||||
*/
|
||||
esp_err_t spi_flash_wrap_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Check whether flash and esp chip supports wrap mode.
|
||||
*
|
||||
* @param wrap_size wrap size.
|
||||
* @return true: wrap support, otherwise, false.
|
||||
*/
|
||||
bool spi_flash_support_wrap_size(uint32_t wrap_size);
|
||||
|
||||
#endif //SOC_SPI_MEM_SUPPORT_WRAP
|
||||
|
||||
/**
|
||||
* @brief SPI flash critical section enter function.
|
||||
*
|
||||
*/
|
||||
typedef void (*spi_flash_guard_start_func_t)(void);
|
||||
/**
|
||||
* @brief SPI flash critical section exit function.
|
||||
*/
|
||||
typedef void (*spi_flash_guard_end_func_t)(void);
|
||||
|
||||
/**
|
||||
* Structure holding SPI flash access critical sections management functions.
|
||||
*
|
||||
* Flash API uses two types of flash access management functions:
|
||||
* 1) Functions which prepare/restore flash cache and interrupts before calling
|
||||
* appropriate ROM functions (SPIWrite, SPIRead and SPIEraseBlock):
|
||||
* - 'start' function should disables flash cache and non-IRAM interrupts and
|
||||
* is invoked before the call to one of ROM function above.
|
||||
* - 'end' function should restore state of flash cache and non-IRAM interrupts and
|
||||
* is invoked after the call to one of ROM function above.
|
||||
* These two functions are not recursive.
|
||||
*
|
||||
* Different versions of the guarding functions should be used depending on the context of
|
||||
* execution (with or without functional OS). In normal conditions when flash API is called
|
||||
* from task the functions use OS primitives. When there is no OS at all or when
|
||||
* it is not guaranteed that OS is functional (accessing flash from exception handler) these
|
||||
* functions cannot use OS primitives or even does not need them (multithreaded access is not possible).
|
||||
*
|
||||
* @note Structure and corresponding guard functions should not reside in flash.
|
||||
* For example structure can be placed in DRAM and functions in IRAM sections.
|
||||
*/
|
||||
typedef struct {
|
||||
spi_flash_guard_start_func_t start; /**< critical section start function. */
|
||||
spi_flash_guard_end_func_t end; /**< critical section end function. */
|
||||
} spi_flash_guard_funcs_t;
|
||||
|
||||
/**
|
||||
* @brief Sets guard functions to access flash.
|
||||
*
|
||||
* @note Pointed structure and corresponding guard functions should not reside in flash.
|
||||
* For example structure can be placed in DRAM and functions in IRAM sections.
|
||||
*
|
||||
* @param funcs pointer to structure holding flash access guard functions.
|
||||
*/
|
||||
void spi_flash_guard_set(const spi_flash_guard_funcs_t* funcs);
|
||||
|
||||
/**
|
||||
* @brief Get the guard functions used for flash access
|
||||
*
|
||||
* @return The guard functions that were set via spi_flash_guard_set(). These functions
|
||||
* can be called if implementing custom low-level SPI flash operations.
|
||||
*/
|
||||
const spi_flash_guard_funcs_t *spi_flash_guard_get(void);
|
||||
|
||||
/**
|
||||
* @brief Default OS-aware flash access guard functions
|
||||
*/
|
||||
extern const spi_flash_guard_funcs_t g_flash_guard_default_ops;
|
||||
|
||||
/**
|
||||
* @brief Non-OS flash access guard functions
|
||||
*
|
||||
* @note This version of flash guard functions is to be used when no OS is present or from panic handler.
|
||||
* It does not use any OS primitives and IPC and implies that only calling CPU is active.
|
||||
*/
|
||||
extern const spi_flash_guard_funcs_t g_flash_guard_no_os_ops;
|
||||
|
||||
/**
|
||||
* @brief This function is used to re-initialize the flash mmap when using ROM flash
|
||||
* implementations.
|
||||
*
|
||||
* @note Only called in startup. User should not call this function.
|
||||
*/
|
||||
void spi_flash_rom_impl_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
#pragma once
|
||||
|
||||
// SPI commands
|
||||
#define CMD_RDID 0x9F
|
||||
#define CMD_RDUID 0x4B /* Read the flash unique ID*/
|
||||
#define CMD_WRSR 0x01
|
||||
#define SR_WIP (1<<0) /* Status register write-in-progress bit */
|
||||
#define SR_WREN (1<<1) /* Status register write enable bit */
|
||||
#define CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
|
||||
#define CMD_WRSR3 0x11 /* Not all SPI flash uses this command */
|
||||
#define CMD_WREN 0x06
|
||||
#define CMD_WRENVSR 0x50 /* Flash write enable for volatile SR bits */
|
||||
#define CMD_WRDI 0x04
|
||||
#define CMD_RDSR 0x05
|
||||
#define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
|
||||
#define CMD_RDSR3 0x15 /* Not all SPI flash uses this command */
|
||||
#define CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
|
||||
#define CMD_RDSCUR 0x2B /* MXIC-specific, read security register */
|
||||
#define CMD_8READ 0xEC /* MXIC-specific, 8 I/O read */
|
||||
#define CMD_8DTRD 0xEE /* MXIC-specific, 8 I/O DTR read */
|
||||
#define CMD_RDFR 0x48 /* ISSI-specific, read function register */
|
||||
|
||||
#define CMD_FASTRD_QIO 0xEB
|
||||
#define CMD_FASTRD_QIO_4B 0xEC
|
||||
#define CMD_FASTRD_QUAD 0x6B
|
||||
#define CMD_FASTRD_QUAD_4B 0x6C
|
||||
#define CMD_FASTRD_DIO 0xBB
|
||||
#define CMD_FASTRD_DIO_4B 0xBC
|
||||
#define CMD_FASTRD_DUAL 0x3B
|
||||
#define CMD_FASTRD_DUAL_4B 0x3C
|
||||
#define CMD_FASTRD 0x0B
|
||||
#define CMD_FASTRD_4B 0x0C
|
||||
#define CMD_READ 0x03 /* Speed limited */
|
||||
#define CMD_READ_4B 0x13 /* Speed limited */
|
||||
#define CMD_SLOWRD_4B 0x13
|
||||
|
||||
#define CMD_CHIP_ERASE 0xC7
|
||||
#define CMD_SECTOR_ERASE 0x20
|
||||
#define CMD_SECTOR_ERASE_4B 0x21
|
||||
#define CMD_LARGE_BLOCK_ERASE 0xD8 /* 64KB block erase command */
|
||||
#define CMD_LARGE_BLOCK_ERASE_4B 0xDC /* 64KB block erase command */
|
||||
#define CMD_PROGRAM_PAGE 0x02
|
||||
#define CMD_PROGRAM_PAGE_4B 0x12
|
||||
#define CMD_SUSPEND 0x75
|
||||
#define CMD_RESUME 0x7A
|
||||
#define CMD_HPMEN 0xA3 /* Enable High Performance mode on flash */
|
||||
#define CMD_WRAP 0x77
|
||||
#define CMD_BURST_RD 0xC0 /* wrap(0x77) and burst read are functionally same. But commands and formats is different */
|
||||
|
||||
#define CMD_RST_EN 0x66
|
||||
#define CMD_RST_DEV 0x99
|
||||
#define CMD_RESETEN 0x66
|
||||
#define CMD_RESET 0x99
|
||||
|
||||
#define CMD_RDSFDP 0x5A /* Read the SFDP of the flash */
|
||||
|
||||
// Flash vendors.
|
||||
#define SPI_FLASH_GD 0xC8
|
||||
#define SPI_FLASH_ISSI 0x9D
|
||||
#define SPI_FLASH_MXIC 0xC2
|
||||
#define SPI_FLASH_XMC_1 0x20
|
||||
#define SPI_FLASH_XMC_2 0x46
|
||||
#define SPI_FLASH_WINBOND 0xEF
|
||||
#define SPI_FLASH_TH 0xCD
|
||||
#define SPI_FLASH_BY 0x68
|
||||
|
||||
#define SPI_FLASH_DIO_DUMMY_BITLEN 4
|
||||
#define SPI_FLASH_QIO_DUMMY_BITLEN 6
|
||||
#define SPI_FLASH_DIO_ADDR_BITLEN 24
|
||||
#define SPI_FLASH_QIO_ADDR_BITLEN 24
|
||||
#define SPI_FLASH_QOUT_ADDR_BITLEN 24
|
||||
#define SPI_FLASH_QOUT_DUMMY_BITLEN 8
|
||||
#define SPI_FLASH_DOUT_ADDR_BITLEN 24
|
||||
#define SPI_FLASH_DOUT_DUMMY_BITLEN 8
|
||||
#define SPI_FLASH_FASTRD_ADDR_BITLEN 24
|
||||
#define SPI_FLASH_FASTRD_DUMMY_BITLEN 8
|
||||
#define SPI_FLASH_SLOWRD_ADDR_BITLEN 24
|
||||
#define SPI_FLASH_SLOWRD_DUMMY_BITLEN 0
|
||||
#define SPI_FLASH_OPISTR_ADDR_BITLEN 32
|
||||
#define SPI_FLASH_OPISTR_DUMMY_BITLEN 20
|
||||
#define SPI_FLASH_OPIDTR_ADDR_BITLEN 32
|
||||
#define SPI_FLASH_OPIDTR_DUMMY_BITLEN 40
|
||||
#define SPI_FLASH_QIO_HPM_DUMMY_BITLEN 10
|
||||
#define SPI_FLASH_DIO_HPM_DUMMY_BITLEN 8
|
||||
Reference in New Issue
Block a user