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https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
refactor(clk_tree): use general api to enable the clk
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -22,7 +22,7 @@
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#include "../dac_priv_dma.h"
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#include "esp_private/i2s_platform.h"
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#include "esp_private/esp_clk.h"
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#include "clk_ctrl_os.h"
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#include "esp_clk_tree.h"
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#if CONFIG_DAC_ENABLE_DEBUG_LOG
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// The local log level must be defined before including esp_log.h
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// Set the maximum log level for this source file
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@@ -56,7 +56,7 @@ static uint32_t s_dac_set_apll_freq(uint32_t mclk)
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uint32_t expt_freq = mclk * div;
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/* Set APLL coefficients to the given frequency */
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uint32_t real_freq = 0;
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esp_err_t ret = periph_rtc_apll_freq_set(expt_freq, &real_freq);
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esp_err_t ret = esp_clk_tree_src_set_freq_hz(SOC_MOD_CLK_APLL, expt_freq, &real_freq);
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if (ret == ESP_ERR_INVALID_ARG) {
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return 0;
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}
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@@ -120,7 +120,7 @@ esp_err_t dac_dma_periph_init(uint32_t freq_hz, bool is_alternate, bool is_apll)
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s_ddp->periph_dev = (void *)I2S_LL_GET_HW(DAC_DMA_PERIPH_I2S_NUM);
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if (is_apll) {
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periph_rtc_apll_acquire();
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ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, true), err, TAG, "APLL enable failed");
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s_ddp->use_apll = true;
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}
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ESP_GOTO_ON_ERROR(s_dac_dma_periph_set_clock(freq_hz, is_apll), err, TAG, "Failed to set clock of DMA peripheral");
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@@ -157,7 +157,7 @@ esp_err_t dac_dma_periph_deinit(void)
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ESP_RETURN_ON_ERROR(i2s_platform_release_occupation(I2S_CTLR_HP, DAC_DMA_PERIPH_I2S_NUM), TAG, "Failed to release DAC DMA peripheral");
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i2s_ll_enable_intr(s_ddp->periph_dev, I2S_LL_EVENT_TX_EOF | I2S_LL_EVENT_TX_TEOF, false);
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if (s_ddp->use_apll) {
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periph_rtc_apll_release();
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ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, false), TAG, "APLL disable failed");
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s_ddp->use_apll = false;
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}
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free(s_ddp);
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