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https://github.com/espressif/esp-idf.git
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refactor(hal): Created esp_hal_security for security code
This commit is contained in:
Aditya Patwardhan
@@ -0,0 +1,258 @@
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/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <string.h>
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#include "soc/hwcrypto_reg.h"
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#include "soc/system_struct.h"
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#include "esp_hal_security/aes_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief State of AES accelerator, busy, idle or done
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*
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*/
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typedef enum {
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ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */
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ESP_AES_STATE_BUSY, /* Transform in progress */
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ESP_AES_STATE_DONE, /* Transform completed */
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} esp_aes_state_t;
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/**
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* @brief Enable the bus clock for AES peripheral module
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*
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* @param enable true to enable the module, false to disable the module
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*/
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static inline void aes_ll_enable_bus_clock(bool enable)
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{
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SYSTEM.perip_clk_en1.crypto_aes_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define aes_ll_enable_bus_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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aes_ll_enable_bus_clock(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Reset the AES peripheral module
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*/
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static inline void aes_ll_reset_register(void)
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{
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SYSTEM.perip_rst_en1.crypto_aes_rst = 1;
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SYSTEM.perip_rst_en1.crypto_aes_rst = 0;
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// Clear reset on digital signature also, otherwise AES is held in reset
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SYSTEM.perip_rst_en1.crypto_ds_rst = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define aes_ll_reset_register(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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aes_ll_reset_register(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Write the encryption/decryption key to hardware
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*
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* @param key Key to be written to the AES hardware
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* @param key_word_len Number of words in the key
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*
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* @return Number of bytes written to hardware, used for fault injection check
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*/
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static inline uint8_t aes_ll_write_key(const uint8_t *key, size_t key_word_len)
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{
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/* This variable is used for fault injection checks, so marked volatile to avoid optimisation */
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volatile uint8_t key_in_hardware = 0;
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/* Memcpy to avoid potential unaligned access */
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uint32_t key_word;
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for (int i = 0; i < key_word_len; i++) {
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memcpy(&key_word, key + 4 * i, 4);
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REG_WRITE(AES_KEY_BASE + i * 4, key_word);
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key_in_hardware += 4;
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}
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return key_in_hardware;
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}
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/**
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* @brief Sets the mode
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*
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* @param mode ESP_AES_ENCRYPT = 1, or ESP_AES_DECRYPT = 0
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* @param key_bytes Number of bytes in the key
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*/
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static inline void aes_ll_set_mode(int mode, uint8_t key_bytes)
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{
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const uint32_t MODE_DECRYPT_BIT = 4;
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unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT;
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/* See TRM for the mapping between keylength and mode bit */
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REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2));
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}
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/**
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* @brief Writes message block to AES hardware
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*
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* @param input Block to be written
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*/
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static inline void aes_ll_write_block(const void *input)
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{
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uint32_t input_word;
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for (int i = 0; i < AES_BLOCK_WORDS; i++) {
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memcpy(&input_word, (uint8_t*)input + 4 * i, 4);
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REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word);
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}
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}
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/**
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* @brief Read the AES block
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*
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* @param output the output of the transform, length = AES_BLOCK_BYTES
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*/
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static inline void aes_ll_read_block(void *output)
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{
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uint32_t output_word;
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const size_t REG_WIDTH = sizeof(uint32_t);
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for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
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output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH));
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/* Memcpy to avoid potential unaligned access */
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memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
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}
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}
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/**
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* @brief Starts block transform
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*
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*/
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static inline void aes_ll_start_transform(void)
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{
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REG_WRITE(AES_TRIGGER_REG, 1);
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}
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/**
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* @brief Read state of AES accelerator
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*
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* @return esp_aes_state_t
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*/
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static inline esp_aes_state_t aes_ll_get_state(void)
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{
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return (esp_aes_state_t)REG_READ(AES_STATE_REG);
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}
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/**
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* @brief Set mode of operation
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*
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* @note Only used for DMA transforms
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*
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* @param mode Mode of operation to set (e.g., ECB, CBC, CTR, etc.)
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*/
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static inline void aes_ll_set_block_mode(esp_aes_mode_t mode)
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{
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REG_WRITE(AES_BLOCK_MODE_REG, mode);
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}
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/**
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* @brief Set AES-CTR counter to INC32
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*
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* @note Only affects AES-CTR mode
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*
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*/
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static inline void aes_ll_set_inc(void)
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{
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REG_WRITE(AES_INC_SEL_REG, 0);
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}
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/**
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* @brief Release the DMA
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*
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*/
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static inline void aes_ll_dma_exit(void)
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{
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REG_WRITE(AES_DMA_EXIT_REG, 0);
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}
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/**
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* @brief Sets the number of blocks to be transformed
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*
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* @note Only used for DMA transforms
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*
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* @param num_blocks Number of blocks to transform
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*/
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static inline void aes_ll_set_num_blocks(size_t num_blocks)
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{
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REG_WRITE(AES_BLOCK_NUM_REG, num_blocks);
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}
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/*
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* Write IV to hardware iv registers
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*/
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static inline void aes_ll_set_iv(const uint8_t *iv)
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{
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uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_BASE);
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uint32_t iv_word;
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for (int i = 0; i < IV_WORDS; i++) {
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/* Memcpy to avoid potential unaligned access */
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memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
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REG_WRITE(®_addr_buf[i], iv_word);
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}
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}
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/*
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* Read IV from hardware iv registers
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*/
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static inline void aes_ll_read_iv(uint8_t *iv)
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{
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uint32_t iv_word;
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const size_t REG_WIDTH = sizeof(uint32_t);
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for (size_t i = 0; i < IV_WORDS; i++) {
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iv_word = REG_READ(AES_IV_BASE + (i * REG_WIDTH));
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/* Memcpy to avoid potential unaligned access */
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memcpy(iv + i * 4, &iv_word, sizeof(iv_word));
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}
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}
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/**
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* @brief Enable or disable DMA mode
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*
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* @param enable true to enable, false to disable.
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*/
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static inline void aes_ll_dma_enable(bool enable)
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{
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REG_WRITE(AES_DMA_ENABLE_REG, enable);
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}
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/**
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* @brief Enable or disable transform completed interrupt
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*
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* @param enable true to enable, false to disable.
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*/
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static inline void aes_ll_interrupt_enable(bool enable)
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{
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REG_WRITE(AES_INT_ENA_REG, enable);
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}
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/**
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* @brief Clears the interrupt
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*
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*/
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static inline void aes_ll_interrupt_clear(void)
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{
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REG_WRITE(AES_INT_CLEAR_REG, 1);
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,197 @@
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/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include "soc/hwcrypto_reg.h"
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#include "soc/soc_caps.h"
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#include "soc/system_struct.h"
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#include "esp_hal_security/ds_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enable the bus clock for Digital Signature peripheral module
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*
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* @param true to enable the module, false to disable the module
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*/
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static inline void ds_ll_enable_bus_clock(bool enable)
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{
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SYSTEM.perip_clk_en1.crypto_ds_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define ds_ll_enable_bus_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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ds_ll_enable_bus_clock(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Reset the Digital Signature peripheral module
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*/
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static inline void ds_ll_reset_register(void)
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{
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SYSTEM.perip_rst_en1.crypto_ds_rst = 1;
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SYSTEM.perip_rst_en1.crypto_ds_rst = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define ds_ll_reset_register(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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ds_ll_reset_register(__VA_ARGS__); \
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} while(0)
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static inline void ds_ll_start(void)
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{
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REG_WRITE(DS_SET_START_REG, 1);
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}
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/**
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* @brief Wait until DS peripheral has finished any outstanding operation.
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*/
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static inline bool ds_ll_busy(void)
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{
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return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false;
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}
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/**
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* @brief Busy wait until the hardware is ready.
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*/
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static inline void ds_ll_wait_busy(void)
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{
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while (ds_ll_busy());
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}
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/**
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* @brief In case of a key error, check what caused it.
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*/
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static inline ds_key_check_t ds_ll_key_error_source(void)
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{
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uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG);
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if (key_error == 0) {
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return DS_NO_KEY_INPUT;
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} else {
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return DS_OTHER_WRONG;
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}
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}
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/**
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* @brief Write the initialization vector to the corresponding register field.
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*/
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static inline void ds_ll_configure_iv(const uint32_t *iv)
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{
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for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
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REG_WRITE(DS_IV_BASE + (i * 4), iv[i]);
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}
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}
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/**
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* @brief Write the message which should be signed.
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*
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* @param msg Pointer to the message.
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* @param size Length of msg in bytes. It is the RSA signature length in bytes.
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*/
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static inline void ds_ll_write_message(const uint8_t *msg, size_t size)
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{
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memcpy((uint8_t *) DS_X_BASE, msg, size);
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}
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/**
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* @brief Write the encrypted private key parameters.
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*/
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static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_params)
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{
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/* Note: as the internal peripheral still has RSA 4096 structure,
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but C is encrypted based on the actual max RSA length (ETS_DS_MAX_BITS), need to fragment it
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when copying to hardware...
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(note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment)
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*/
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typedef struct {
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uint32_t addr;
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size_t len;
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} frag_t;
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const frag_t frags[] = {
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{DS_C_Y_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
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{DS_C_M_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
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{DS_C_RB_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
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{DS_C_BOX_BASE, DS_IV_BASE - DS_C_BOX_BASE},
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};
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const size_t NUM_FRAGS = sizeof(frags) / sizeof(frag_t);
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const uint8_t *from = encrypted_key_params;
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for (int i = 0; i < NUM_FRAGS; i++) {
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memcpy((uint8_t *)frags[i].addr, from, frags[i].len);
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from += frags[i].len;
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}
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}
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/**
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* @brief Begin signing procedure.
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*/
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static inline void ds_ll_start_sign(void)
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{
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REG_WRITE(DS_SET_ME_REG, 1);
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}
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/**
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* @brief check the calculated signature.
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*
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* @return
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* - DS_SIGNATURE_OK if no issue is detected with the signature.
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* - DS_SIGNATURE_PADDING_FAIL if the padding of the private key parameters is wrong.
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* - DS_SIGNATURE_MD_FAIL if the message digest check failed. This means that the message digest calculated using
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* the private key parameters fails, i.e., the integrity of the private key parameters is not protected.
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* - DS_SIGNATURE_PADDING_AND_MD_FAIL if both padding and message digest check fail.
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*/
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static inline ds_signature_check_t ds_ll_check_signature(void)
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{
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uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
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switch (result) {
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case 0:
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return DS_SIGNATURE_OK;
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case 1:
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return DS_SIGNATURE_MD_FAIL;
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case 2:
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return DS_SIGNATURE_PADDING_FAIL;
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default:
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return DS_SIGNATURE_PADDING_AND_MD_FAIL;
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}
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}
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/**
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* @brief Read the signature from the hardware.
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*
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* @param result The signature result.
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* @param size Length of signature result in bytes. It is the RSA signature length in bytes.
|
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*/
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static inline void ds_ll_read_result(uint8_t *result, size_t size)
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{
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memcpy(result, (uint8_t *) DS_Z_BASE, size);
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}
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/**
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* @brief Exit the signature operation.
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*
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* @note This does not deactivate the module. Corresponding clock/reset bits have to be triggered for deactivation.
|
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*/
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static inline void ds_ll_finish(void)
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{
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REG_WRITE(DS_SET_FINISH_REG, 1);
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ds_ll_wait_busy();
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}
|
||||
|
||||
#ifdef __cplusplus
|
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}
|
||||
#endif
|
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@@ -0,0 +1,225 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*******************************************************************************
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||||
* NOTICE
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||||
* The hal is not public api, don't use it in application code.
|
||||
* See readme.md in soc/include/hal/readme.md
|
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******************************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stddef.h> /* For size_t type */
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "soc/hwcrypto_reg.h"
|
||||
#include "soc/system_struct.h"
|
||||
#include "esp_hal_security/hmac_types.h"
|
||||
|
||||
#define SHA256_BLOCK_SZ 64
|
||||
#define SHA256_DIGEST_SZ 32
|
||||
|
||||
#define HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_JTAG 6
|
||||
#define HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_DIGITAL_SIGNATURE 7
|
||||
#define HMAC_LL_EFUSE_KEY_PURPOSE_UP 8
|
||||
#define HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_ALL 5
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the bus clock for HMAC peripheral module
|
||||
*
|
||||
* @param true to enable the module, false to disable the module
|
||||
*/
|
||||
static inline void hmac_ll_enable_bus_clock(bool enable)
|
||||
{
|
||||
SYSTEM.perip_clk_en1.crypto_hmac_clk_en = enable;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define hmac_ll_enable_bus_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
hmac_ll_enable_bus_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Reset the HMAC peripheral module
|
||||
*/
|
||||
static inline void hmac_ll_reset_register(void)
|
||||
{
|
||||
SYSTEM.perip_rst_en1.crypto_hmac_rst = 1;
|
||||
SYSTEM.perip_rst_en1.crypto_hmac_rst = 0;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define hmac_ll_reset_register(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
hmac_ll_reset_register(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* Makes the peripheral ready for use, after enabling it.
|
||||
*/
|
||||
static inline void hmac_ll_start(void)
|
||||
{
|
||||
REG_WRITE(HMAC_SET_START_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Determine where the HMAC output should go.
|
||||
*
|
||||
* The HMAC peripheral can be configured to deliver its output to the user directly, or to deliver
|
||||
* the output directly to another peripheral instead, e.g. the Digital Signature peripheral.
|
||||
*/
|
||||
static inline void hmac_ll_config_output(hmac_hal_output_t config)
|
||||
{
|
||||
switch (config) {
|
||||
case HMAC_OUTPUT_USER:
|
||||
REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_UP);
|
||||
break;
|
||||
case HMAC_OUTPUT_DS:
|
||||
REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_DIGITAL_SIGNATURE);
|
||||
break;
|
||||
case HMAC_OUTPUT_JTAG_ENABLE:
|
||||
REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_JTAG);
|
||||
break;
|
||||
case HMAC_OUTPUT_ALL:
|
||||
REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_ALL);
|
||||
break;
|
||||
default:
|
||||
; // do nothing, error will be indicated by hmac_hal_config_error()
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects which hardware key should be used.
|
||||
*/
|
||||
static inline void hmac_ll_config_hw_key_id(uint32_t key_id)
|
||||
{
|
||||
REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Apply and check configuration.
|
||||
*
|
||||
* Afterwards, the configuration can be checked for errors with hmac_hal_config_error().
|
||||
*/
|
||||
static inline void hmac_ll_config_finish(void)
|
||||
{
|
||||
REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Query HMAC error state after configuration actions.
|
||||
*
|
||||
* @return
|
||||
* - 1 or greater on error
|
||||
* - 0 on success
|
||||
*/
|
||||
static inline uint32_t hmac_ll_config_error(void)
|
||||
{
|
||||
return REG_READ(HMAC_QUERY_ERROR_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* Wait until the HAL is ready for the next interaction.
|
||||
*/
|
||||
static inline void hmac_ll_wait_idle(void)
|
||||
{
|
||||
uint32_t query;
|
||||
do {
|
||||
query = REG_READ(HMAC_QUERY_BUSY_REG);
|
||||
} while (query != 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write a message block of 512 bits to the HMAC peripheral.
|
||||
*/
|
||||
static inline void hmac_ll_write_block_512(const uint32_t *block)
|
||||
{
|
||||
const size_t REG_WIDTH = sizeof(uint32_t);
|
||||
for (size_t i = 0; i < SHA256_BLOCK_SZ / REG_WIDTH; i++) {
|
||||
REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]);
|
||||
}
|
||||
|
||||
REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the 256 bit HMAC.
|
||||
*/
|
||||
static inline void hmac_ll_read_result_256(uint32_t *result)
|
||||
{
|
||||
const size_t REG_WIDTH = sizeof(uint32_t);
|
||||
for (size_t i = 0; i < SHA256_DIGEST_SZ / REG_WIDTH; i++) {
|
||||
result[i] = REG_READ(HMAC_RDATA_BASE + (i * REG_WIDTH));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clean the HMAC result provided to other hardware.
|
||||
*/
|
||||
static inline void hmac_ll_clean(void)
|
||||
{
|
||||
REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1);
|
||||
REG_WRITE(HMAC_SET_INVALIDATE_JTAG_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Signals that the following block will be the padded last block.
|
||||
*/
|
||||
static inline void hmac_ll_msg_padding(void)
|
||||
{
|
||||
REG_WRITE(HMAC_SET_MESSAGE_PAD_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Signals that all blocks have been written and a padding block will automatically be applied by hardware.
|
||||
*
|
||||
* Only applies if the message length is a multiple of 512 bits.
|
||||
* See ESP32S3 TRM HMAC chapter for more details.
|
||||
*/
|
||||
static inline void hmac_ll_msg_end(void)
|
||||
{
|
||||
REG_WRITE(HMAC_SET_MESSAGE_END_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The message including padding fits into one block, so no further action needs to be taken.
|
||||
*
|
||||
* This is called after the one-block-message has been written.
|
||||
*/
|
||||
static inline void hmac_ll_msg_one_block(void)
|
||||
{
|
||||
REG_WRITE(HMAC_ONE_BLOCK_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate that more blocks will be written after the last block.
|
||||
*/
|
||||
static inline void hmac_ll_msg_continue(void)
|
||||
{
|
||||
REG_WRITE(HMAC_SET_MESSAGE_ING_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the HMAC result.
|
||||
*
|
||||
* Use this after reading the HMAC result or if aborting after any of the other steps above.
|
||||
*/
|
||||
static inline void hmac_ll_calc_finish(void)
|
||||
{
|
||||
REG_WRITE(HMAC_SET_RESULT_FINISH_REG, 2);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,188 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <sys/param.h>
|
||||
#include "hal/assert.h"
|
||||
#include "esp_hal_security/mpi_types.h"
|
||||
#include "soc/hwcrypto_periph.h"
|
||||
#include "soc/dport_reg.h"
|
||||
#include "soc/mpi_periph.h"
|
||||
#include "soc/system_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the bus clock for MPI peripheral module
|
||||
*
|
||||
* @param enable true to enable the module, false to disable the module
|
||||
*/
|
||||
static inline void mpi_ll_enable_bus_clock(bool enable)
|
||||
{
|
||||
SYSTEM.perip_clk_en1.crypto_rsa_clk_en = enable;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mpi_ll_enable_bus_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
mpi_ll_enable_bus_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Reset the MPI peripheral module
|
||||
*/
|
||||
static inline void mpi_ll_reset_register(void)
|
||||
{
|
||||
SYSTEM.perip_rst_en1.crypto_rsa_rst = 1;
|
||||
SYSTEM.perip_rst_en1.crypto_rsa_rst = 0;
|
||||
|
||||
// Clear reset on digital signature also, otherwise RSA is held in reset
|
||||
SYSTEM.perip_rst_en1.crypto_ds_rst = 0;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define mpi_ll_reset_register(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
mpi_ll_reset_register(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
|
||||
{
|
||||
return words;
|
||||
}
|
||||
|
||||
static inline void mpi_ll_power_up(void)
|
||||
{
|
||||
REG_CLR_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_power_down(void)
|
||||
{
|
||||
REG_SET_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_enable_interrupt(void)
|
||||
{
|
||||
REG_WRITE(RSA_INTERRUPT_REG, 1);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_disable_interrupt(void)
|
||||
{
|
||||
REG_WRITE(RSA_INTERRUPT_REG, 0);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_clear_interrupt(void)
|
||||
{
|
||||
REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
|
||||
}
|
||||
|
||||
static inline bool mpi_ll_check_memory_init_complete(void)
|
||||
{
|
||||
return REG_READ(RSA_QUERY_CLEAN_REG) == 0;
|
||||
}
|
||||
|
||||
static inline void mpi_ll_start_op(mpi_op_t op)
|
||||
{
|
||||
REG_WRITE(MPI_OPERATIONS_REG[op], 1);
|
||||
}
|
||||
|
||||
static inline bool mpi_ll_get_int_status(void)
|
||||
{
|
||||
return REG_READ(RSA_QUERY_INTERRUPT_REG) == 0;
|
||||
}
|
||||
|
||||
/* Copy MPI bignum (p) to hardware memory block at 'mem_base'.
|
||||
|
||||
If num_words is higher than the number of words (n) in the bignum then
|
||||
these additional words will be zeroed in the memory buffer.
|
||||
*/
|
||||
static inline void mpi_ll_write_to_mem_block(mpi_param_t param, size_t offset, const uint32_t* p, size_t n, size_t num_words)
|
||||
{
|
||||
uint32_t mem_base = MPI_BLOCK_BASES[param] + offset;
|
||||
uint32_t* pbase = (uint32_t*) mem_base;
|
||||
uint32_t copy_words = MIN(num_words, n);
|
||||
|
||||
/* Copy MPI data to memory block registers */
|
||||
for (int i = 0; i < copy_words; i++) {
|
||||
pbase[i] = p[i];
|
||||
}
|
||||
|
||||
/* Zero any remaining memory block data */
|
||||
for (int i = copy_words; i < num_words; i++) {
|
||||
pbase[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void mpi_ll_write_m_prime(uint32_t Mprime)
|
||||
{
|
||||
REG_WRITE(RSA_M_DASH_REG, Mprime);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_write_rinv(uint32_t rinv)
|
||||
{
|
||||
REG_WRITE(MPI_BLOCK_BASES[MPI_PARAM_Z], rinv);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_write_at_offset(mpi_param_t param, int offset, uint32_t value)
|
||||
{
|
||||
uint32_t mem_base = MPI_BLOCK_BASES[param] + offset;
|
||||
REG_WRITE(mem_base, value);
|
||||
}
|
||||
|
||||
/* Read MPI bignum (p) back from hardware memory block.
|
||||
|
||||
Reads z_words words from block.
|
||||
*/
|
||||
static inline void mpi_ll_read_from_mem_block(uint32_t* p, size_t n, size_t num_words)
|
||||
{
|
||||
uint32_t mem_base = MPI_BLOCK_BASES[MPI_PARAM_Z];
|
||||
esp_dport_access_read_buffer(p, mem_base, num_words);
|
||||
/* Zero any remaining limbs in the bignum, if the buffer is bigger
|
||||
than num_words */
|
||||
for (size_t i = num_words; i < n; i++) {
|
||||
p[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void mpi_ll_set_mode(size_t length)
|
||||
{
|
||||
REG_WRITE(RSA_LENGTH_REG, length);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_disable_constant_time(void)
|
||||
{
|
||||
REG_WRITE(RSA_CONSTANT_TIME_REG, 0);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_enable_constant_time(void)
|
||||
{
|
||||
REG_WRITE(RSA_CONSTANT_TIME_REG, 1);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_disable_search(void)
|
||||
{
|
||||
REG_WRITE(RSA_SEARCH_OPEN_REG, 0);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_enable_search(void)
|
||||
{
|
||||
REG_WRITE(RSA_SEARCH_OPEN_REG, 1);
|
||||
}
|
||||
|
||||
static inline void mpi_ll_set_search_position(size_t pos)
|
||||
{
|
||||
REG_WRITE(RSA_SEARCH_POS_REG, pos);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
#include "xt_instr_macros.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
|
||||
{
|
||||
// vpn - id
|
||||
// 0x00000000 = 0
|
||||
// 0x20000000 = 1
|
||||
// 0x40000000 = 2
|
||||
// 0x60000000 = 3
|
||||
// 0x80000000 = 4
|
||||
// 0xa0000000 = 5
|
||||
// 0xc0000000 = 6
|
||||
// 0xe0000000 = 7
|
||||
return id * SOC_MPU_MIN_REGION_SIZE;
|
||||
}
|
||||
|
||||
static inline void mpu_ll_set_region_rw(uint32_t addr)
|
||||
{
|
||||
WDTLB(0x0, addr); // cached, no allocate
|
||||
}
|
||||
|
||||
static inline void mpu_ll_set_region_rwx(uint32_t addr)
|
||||
{
|
||||
WDTLB(0x2, addr); // bypass cache
|
||||
}
|
||||
|
||||
static inline void mpu_ll_set_region_x(uint32_t addr)
|
||||
{
|
||||
WITLB(0x3, addr); // cached
|
||||
}
|
||||
|
||||
static inline void mpu_ll_set_region_illegal(uint32_t addr)
|
||||
{
|
||||
WITLB(0xF, addr);
|
||||
WDTLB(0xF, addr);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,206 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/dport_reg.h"
|
||||
#include "soc/hwcrypto_reg.h"
|
||||
#include "soc/system_struct.h"
|
||||
#include "esp_hal_security/sha_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the bus clock for SHA peripheral module
|
||||
*
|
||||
* @param enable true to enable the module, false to disable the module
|
||||
*/
|
||||
static inline void sha_ll_enable_bus_clock(bool enable)
|
||||
{
|
||||
SYSTEM.perip_clk_en1.crypto_sha_clk_en = enable;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define sha_ll_enable_bus_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
sha_ll_enable_bus_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Reset the SHA peripheral module
|
||||
*/
|
||||
static inline void sha_ll_reset_register(void)
|
||||
{
|
||||
SYSTEM.perip_rst_en1.crypto_sha_rst = 1;
|
||||
SYSTEM.perip_rst_en1.crypto_sha_rst = 0;
|
||||
|
||||
// Clear reset on digital signature and hmac also, otherwise SHA is held in reset
|
||||
SYSTEM.perip_rst_en1.crypto_ds_rst = 0;
|
||||
SYSTEM.perip_rst_en1.crypto_hmac_rst = 0;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define sha_ll_reset_register(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
sha_ll_reset_register(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Load the mode for the SHA engine
|
||||
*
|
||||
* @param sha_type The SHA algorithm type
|
||||
*/
|
||||
static inline void sha_ll_set_mode(esp_sha_type sha_type)
|
||||
{
|
||||
REG_WRITE(SHA_MODE_REG, sha_type);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start a new SHA block conversions (no initial hash in HW)
|
||||
*
|
||||
* @param sha_type The SHA algorithm type
|
||||
*/
|
||||
static inline void sha_ll_start_block(esp_sha_type sha_type)
|
||||
{
|
||||
(void) sha_type;
|
||||
REG_WRITE(SHA_START_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Continue a SHA block conversion (initial hash in HW)
|
||||
*
|
||||
* @param sha_type The SHA algorithm type
|
||||
*/
|
||||
static inline void sha_ll_continue_block(esp_sha_type sha_type)
|
||||
{
|
||||
(void) sha_type;
|
||||
REG_WRITE(SHA_CONTINUE_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start a new SHA message conversion using DMA (no initial hash in HW)
|
||||
*/
|
||||
static inline void sha_ll_start_dma(void)
|
||||
{
|
||||
REG_WRITE(SHA_DMA_START_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Continue a SHA message conversion using DMA (initial hash in HW)
|
||||
*/
|
||||
static inline void sha_ll_continue_dma(void)
|
||||
{
|
||||
REG_WRITE(SHA_DMA_CONTINUE_REG, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load the current hash digest to digest register
|
||||
*
|
||||
* @note Happens automatically on ESP32S3
|
||||
*
|
||||
* @param sha_type The SHA algorithm type
|
||||
*/
|
||||
static inline void sha_ll_load(esp_sha_type sha_type)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of message blocks to be hashed
|
||||
*
|
||||
* @note DMA operation only
|
||||
*
|
||||
* @param num_blocks Number of message blocks to process
|
||||
*/
|
||||
static inline void sha_ll_set_block_num(size_t num_blocks)
|
||||
{
|
||||
REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the SHA engine is currently busy hashing a block
|
||||
*
|
||||
* @return true SHA engine busy
|
||||
* @return false SHA engine idle
|
||||
*/
|
||||
static inline bool sha_ll_busy(void)
|
||||
{
|
||||
return REG_READ(SHA_BUSY_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write a text (message) block to the SHA engine
|
||||
*
|
||||
* @param input_text Input buffer to be written to the SHA engine
|
||||
* @param block_word_len Number of words in block
|
||||
*/
|
||||
static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len)
|
||||
{
|
||||
uint32_t *data_words = (uint32_t *)input_text;
|
||||
uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE);
|
||||
|
||||
for (size_t i = 0; i < block_word_len; i++) {
|
||||
REG_WRITE(®_addr_buf[i], data_words[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the message digest from the SHA engine
|
||||
*
|
||||
* @param sha_type The SHA algorithm type
|
||||
* @param digest_state Buffer that message digest will be written to
|
||||
* @param digest_word_len Length of the message digest
|
||||
*/
|
||||
static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
|
||||
{
|
||||
uint32_t *digest_state_words = (uint32_t *)digest_state;
|
||||
|
||||
esp_dport_access_read_buffer(digest_state_words, SHA_H_BASE, digest_word_len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write the message digest to the SHA engine
|
||||
*
|
||||
* @param sha_type The SHA algorithm type
|
||||
* @param digest_state Message digest to be written to SHA engine
|
||||
* @param digest_word_len Length of the message digest
|
||||
*/
|
||||
static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
|
||||
{
|
||||
uint32_t *digest_state_words = (uint32_t *)digest_state;
|
||||
uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_BASE);
|
||||
|
||||
for (size_t i = 0; i < digest_word_len; i++) {
|
||||
REG_WRITE(®_addr_buf[i], digest_state_words[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets SHA512_t T_string parameter
|
||||
*
|
||||
* @param t_string T_string parameter
|
||||
*/
|
||||
static inline void sha_ll_t_string_set(uint32_t t_string)
|
||||
{
|
||||
REG_WRITE(SHA_T_STRING_REG, t_string);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets SHA512_t T_string parameter's length
|
||||
*
|
||||
* @param t_len T_string parameter length
|
||||
*/
|
||||
static inline void sha_ll_t_len_set(uint8_t t_len)
|
||||
{
|
||||
REG_WRITE(SHA_T_LENGTH_REG, t_len);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user