mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-03 03:31:41 +03:00
feat(esp_system): riscv: refactor linker scripts to reduce duplicated code
This commit is contained in:
Alexey Lapshin
BOT
@@ -9,6 +9,12 @@
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#include "sdkconfig.h"
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#include "ld.common"
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/**
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* physical memory is mapped twice to the virtual address (IRAM and DRAM).
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* `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
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*/
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_iram_dram_shared = 1;
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#define SRAM_IRAM_START 0x4037C000
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#define SRAM_DRAM_START 0x3FCA0000
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#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C2 */
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@@ -64,29 +70,15 @@ MEMORY
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000;
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REGION_ALIAS("iram_text_seg", iram0_0_seg);
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REGION_ALIAS("dram_seg", dram0_0_seg);
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_code_seg", iram0_2_seg);
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REGION_ALIAS("flash_text_seg", iram0_2_seg);
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REGION_ALIAS("flash_rodata_seg", drom0_0_seg);
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#else
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REGION_ALIAS("default_code_seg", iram0_0_seg);
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REGION_ALIAS("flash_text_seg", iram0_0_seg);
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REGION_ALIAS("flash_rodata_seg", dram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_rodata_seg", drom0_0_seg);
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#else
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REGION_ALIAS("default_rodata_seg", dram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
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* also be first in the segment.
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*/
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
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".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
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#endif
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#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
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ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
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ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
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#endif
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ALIGN_VECTOR_TABLE = 0x100;
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@@ -4,368 +4,19 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "ld.common"
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/* Default entry point */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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.iram0.text :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to start of IRAM */
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ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
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KEEP(*(.exception_vectors_table.text));
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KEEP(*(.exception_vectors.text));
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#include "ld.iram.sections"
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/* Code marked as running out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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#include "ld.dram.sections"
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mapping[iram0_text]
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#include "ld.flash.sections"
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} > iram0_0_seg
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#include "ld.heap.sections"
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/**
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* This section is required to skip .iram0.text area because iram0_0_seg and
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* dram0_0_seg reflect the same address space on different buses.
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*/
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.dram0.dummy (NOLOAD):
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{
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. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
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} > dram0_0_seg
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/**
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* This section MUST be placed at the beginning of the DRAM0, which will be
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* released along with iram0_bt.text when Bluetooth is no longer in use.
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*/
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.dram0.bt.data :
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{
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_data_start = ABSOLUTE(.);
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mapping[dram0_bt_data]
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} > dram0_0_seg
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.dram0.bt.bss (NOLOAD) :
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{
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ALIGNED_SYMBOL(8, _bss_bt_start)
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mapping[dram0_bt_bss]
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_bss_bt_end = ABSOLUTE(.);
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} > dram0_0_seg
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.dram0.data :
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{
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*(.gnu.linkonce.d.*)
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*(.data1)
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__global_pointer$ = . + 0x800;
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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mapping[dram0_data]
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_data_end = ABSOLUTE(.);
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} > dram0_0_seg
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/**
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* This section holds data that should not be initialized at power up.
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* The section located in Internal SRAM memory region. The macro _NOINIT
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* can be used as attribute to place data into this section.
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* See the "esp_attr.h" file for more information.
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*/
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.noinit (NOLOAD):
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{
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ALIGNED_SYMBOL(4, _noinit_start)
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*(.noinit .noinit.*)
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ALIGNED_SYMBOL(4, _noinit_end)
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} > dram0_0_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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ALIGNED_SYMBOL(8, _bss_start)
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/**
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* ldgen places all bss-related data to mapping[dram0_bss]
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* (See components/esp_system/app.lf).
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*/
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mapping[dram0_bss]
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ALIGNED_SYMBOL(8, _bss_end)
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} > dram0_0_seg
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ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
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"DRAM segment data does not fit.")
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.flash.text :
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{
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_stext = .;
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/**
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* Mark the start of flash.text.
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* This can be used by the MMU driver to maintain the virtual address.
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*/
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_instruction_reserved_start = ABSOLUTE(.);
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_text_start = ABSOLUTE(.);
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mapping[flash_text]
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*(.stub)
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*(.gnu.linkonce.t.*)
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*(.gnu.warning)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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/**
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* CPU will try to prefetch up to 16 bytes of of instructions.
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* This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += _esp_flash_mmap_prefetch_pad_size;
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_text_end = ABSOLUTE(.);
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/**
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* Mark the flash.text end.
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* This can be used for MMU driver to maintain virtual address.
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*/
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_instruction_reserved_end = ABSOLUTE(.);
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_etext = .;
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/**
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* Similar to _iram_start, this symbol goes here so it is
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* resolved by addr2line in preference to the first symbol in
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* the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} > default_code_seg
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/**
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* Dummy section represents the .flash.text section but in default_rodata_seg.
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* Thus, it must have its alignment and (at least) its size.
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*/
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.flash_rodata_dummy (NOLOAD):
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{
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_flash_rodata_dummy_start = .;
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. = ALIGN(ALIGNOF(.flash.text)) + SIZEOF(.flash.text);
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/* Add alignment of MMU page size + 0x20 bytes for the mapping header. */
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. = ALIGN(_esp_mmu_page_size) + 0x20;
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} > default_rodata_seg
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.flash.appdesc : ALIGN(0x10)
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{
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/**
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* Mark flash.rodata start.
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* This can be used for mmu driver to maintain virtual address
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*/
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_rodata_reserved_start = ABSOLUTE(.);
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_rodata_start = ABSOLUTE(.);
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/* !DO NOT PUT ANYTHING BEFORE THIS! */
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/* Should be the first. App version info. */
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*(.rodata_desc .rodata_desc.*)
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/* Should be the second. Custom app version info. */
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*(.rodata_custom_desc .rodata_custom_desc.*)
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/**
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* Create an empty gap within this section. Thanks to this, the end of this
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* section will match .flash.rodata's begin address. Thus, both sections
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* will be merged when creating the final bin image.
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*/
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. = ALIGN(ALIGNOF(.flash.rodata));
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} > default_rodata_seg
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ASSERT_SECTIONS_GAP(.flash.appdesc, .flash.rodata)
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.flash.rodata : ALIGN(0x10)
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{
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_flash_rodata_start = ABSOLUTE(.);
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mapping[flash_rodata]
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#if CONFIG_LIBC_PICOLIBC
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*(.got .got.plt) /* TODO: GCC-439 */
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#endif
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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*(.gcc_except_table .gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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/**
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* C++ constructor tables.
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*
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* Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt.
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*
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* RISC-V gcc is configured with --enable-initfini-array so it emits
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* .init_array section instead. But the init_priority sections will be
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* sorted for iteration in ascending order during startup.
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* The rest of the init_array sections is sorted for iteration in descending
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* order during startup, however. Hence a different section is generated for
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* the init_priority functions which is iterated in ascending order during
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* startup. The corresponding code can be found in startup.c.
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*/
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ALIGNED_SYMBOL(4, __init_priority_array_start)
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
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__init_priority_array_end = ABSOLUTE(.);
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ALIGNED_SYMBOL(4, __init_array_start)
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
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__init_array_end = ABSOLUTE(.);
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/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
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ALIGNED_SYMBOL(4, soc_reserved_memory_region_start)
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KEEP (*(.reserved_memory_address))
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soc_reserved_memory_region_end = ABSOLUTE(.);
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/* System init functions registered via ESP_SYSTEM_INIT_FN */
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ALIGNED_SYMBOL(4, _esp_system_init_fn_array_start)
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KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
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_esp_system_init_fn_array_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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. = ALIGN(ALIGNOF(SECTION_AFTER_FLASH_RODATA));
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} > default_rodata_seg
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ASSERT_SECTIONS_GAP(.flash.rodata, SECTION_AFTER_FLASH_RODATA)
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#if EH_FRAME_LINKING_ENABLED
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.eh_frame_hdr :
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{
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ALIGNED_SYMBOL(4, __eh_frame_hdr)
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KEEP (*(.eh_frame_hdr))
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__eh_frame_hdr_end = ABSOLUTE(.);
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. = ALIGN(ALIGNOF(.eh_frame));
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} > default_rodata_seg
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ASSERT_SECTIONS_GAP(.eh_frame_hdr, .eh_frame)
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.eh_frame :
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{
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ALIGNED_SYMBOL(4, __eh_frame)
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KEEP (*(.eh_frame))
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/**
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* As we are not linking with crtend.o, which includes the CIE terminator
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* (see __FRAME_END__ in libgcc sources), it is manually provided here.
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*/
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LONG(0);
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__eh_frame_end = ABSOLUTE(.);
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. = ALIGN(ALIGNOF(.flash.tdata));
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} > default_rodata_seg
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ASSERT_SECTIONS_GAP(.eh_frame, .flash.tdata)
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#endif // EH_FRAME_LINKING_ENABLED
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.flash.tdata :
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{
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/* Keep tdata and tbss sections contiguous (no gaps between them).
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* The TLS runtime code calculates offsets assuming these sections are
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* adjacent. Gaps would cause incorrect address calculations, leading
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* to accessing wrong memory.
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*/
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/* tdata sections */
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_thread_local_data_start = ABSOLUTE(.);
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#if CONFIG_LIBC_PICOLIBC
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_picolibc_reent_stub_start = ABSOLUTE(.);
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KEEP(*(.tdata.errno))
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#if CONFIG_LIBC_PICOLIBC_NEWLIB_COMPATIBILITY
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/* Reproduce the public fields from struct _reent. */
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KEEP(*(.tdata.tls_stdin))
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KEEP(*(.tdata.tls_stdout))
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KEEP(*(.tdata.tls_stderr))
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#endif // CONFIG_LIBC_PICOLIBC_NEWLIB_COMPATIBILITY
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_picolibc_reent_stub_end = ABSOLUTE(.);
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#endif // CONFIG_LIBC_PICOLIBC
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*(.tdata .tdata.* .gnu.linkonce.td.*)
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. = ALIGN(ALIGNOF(.flash.tbss));
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_thread_local_data_end = ABSOLUTE(.);
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} > default_rodata_seg
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ASSERT_SECTIONS_GAP(.flash.tdata, .flash.tbss)
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ASSERT_PICOLIBC_REENT_STUB()
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.flash.tbss (NOLOAD) :
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{
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/* tbss sections */
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_thread_local_bss_start = ABSOLUTE(.);
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*(.tbss .tbss.* .gnu.linkonce.tb.*)
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*(.tcommon .tcommon.*)
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_thread_local_bss_end = ABSOLUTE(.);
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} > default_rodata_seg
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ASSERT(_thread_local_data_end == _thread_local_bss_start,
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"tdata and tbss must be contiguous.")
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/**
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* This section contains all the rodata that is not used
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* at runtime, helping to avoid an increase in binary size.
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*/
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.flash.rodata_noload (NOLOAD) :
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{
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/**
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* This symbol marks the end of flash.rodata. It can be utilized by the MMU
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* driver to maintain the virtual address.
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* NOLOAD rodata may not be included in this section.
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*/
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_rodata_reserved_end = .;
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mapping[rodata_noload]
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} > default_rodata_seg
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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ALIGNED_SYMBOL(4, _iram_text_end)
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} > iram0_0_seg
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.iram0.data :
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{
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ALIGNED_SYMBOL(16, _iram_data_start)
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mapping[iram0_data]
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_iram_data_end = ABSOLUTE(.);
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} > iram0_0_seg
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.iram0.bss (NOLOAD) :
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{
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ALIGNED_SYMBOL(16, _iram_bss_start)
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mapping[iram0_bss]
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_iram_bss_end = ABSOLUTE(.);
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} > iram0_0_seg
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/**
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* This section needs to be placed at the end of the IRAM0, which will be
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* released along with dram0_bt_data and dram0_bt_bss when Bluetooth is no
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* longer in use.
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*/
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.iram0.bt.text :
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{
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ALIGNED_SYMBOL(16, _iram_bt_text_start)
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mapping[iram0_bt_text]
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ALIGNED_SYMBOL(16, _iram_end)
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} > iram0_0_seg
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/* Marks the end of data, bss and possibly rodata */
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.dram0.heap_start (NOLOAD) :
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{
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ALIGNED_SYMBOL(16, _heap_start)
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} > dram0_0_seg
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#include "elf_misc.ld.in"
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#include "ld.debug.sections"
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#include "ld.discard.sections"
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}
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ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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"IRAM0 segment data does not fit.")
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ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
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"DRAM segment data does not fit.")
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