change(rom): add rom caps for bootloader in flash offset

components/bootloader/Kconfig.projbuild

@@ -6,10 +6,7 @@ menu "Bootloader config"
 
     config BOOTLOADER_OFFSET_IN_FLASH
         hex
-        default 0x1000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2
+        default ESP_ROM_BOOTLOADER_OFFSET_FLASH
-        # the first 2 sectors are reserved for the key manager with AES-XTS (flash encryption) purpose
-        default 0x2000 if IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32S31
-        default 0x0
         help
             Offset address that 2nd bootloader will be flashed to.
             The value is determined by the ROM bootloader.

components/esp_rom/esp32/Kconfig.soc_caps.in

@@ -62,3 +62,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
 config ESP_ROM_HAS_REGI2C_IMPL
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x1000

components/esp_rom/esp32/esp_rom_caps.h

@@ -21,3 +21,4 @@
 #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB  (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep.
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC    (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_HAS_REGI2C_IMPL         (1) // ROM has the implementation of REGI2C read/write functions
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x1000) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32c2/Kconfig.soc_caps.in

@@ -114,3 +114,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
 config ESP_ROM_HAS_REGI2C_IMPL
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x0

components/esp_rom/esp32c2/esp_rom_caps.h

@@ -34,3 +34,4 @@
 #define ESP_ROM_CONSOLE_OUTPUT_SECONDARY    (1) // The console output functions will also output to the USB-serial secondary console
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
 #define ESP_ROM_HAS_REGI2C_IMPL             (1) // ROM has the implementation of REGI2C read/write functions
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x0) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32c3/Kconfig.soc_caps.in

@@ -110,3 +110,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
 config ESP_ROM_HAS_REGI2C_IMPL
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x0

components/esp_rom/esp32c3/esp_rom_caps.h

@@ -33,3 +33,4 @@
 #define ESP_ROM_CONSOLE_OUTPUT_SECONDARY    (1) // The console output functions will also output to the USB-serial secondary console
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
 #define ESP_ROM_HAS_REGI2C_IMPL             (1) // ROM has the implementation of REGI2C read/write functions
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x0) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32c5/Kconfig.soc_caps.in

@@ -118,3 +118,7 @@ config ESP_ROM_DELAY_US_PATCH
 config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x2000

components/esp_rom/esp32c5/esp_rom_caps.h

@@ -35,3 +35,4 @@
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
 #define ESP_ROM_DELAY_US_PATCH              (1) // ROM ets_delay_us needs patch for U-mode operation
 #define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x2000) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32c6/Kconfig.soc_caps.in

@@ -122,3 +122,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
 config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x0

components/esp_rom/esp32c6/esp_rom_caps.h

@@ -36,3 +36,4 @@
 #define ESP_ROM_NO_USB_SERIAL_OUTPUT_API    (1) // ROM does not export the usb-serial-jtag write char function
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
 #define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x0) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32c61/Kconfig.soc_caps.in

@@ -110,3 +110,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
 config ESP_ROM_DELAY_US_PATCH
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x0

components/esp_rom/esp32c61/esp_rom_caps.h

@@ -33,3 +33,4 @@
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
 #define ESP_ROM_DELAY_US_PATCH              (1) // ROM ets_delay_us needs patch for U-mode operation
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x0) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32h2/Kconfig.soc_caps.in

@@ -114,3 +114,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
 config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x0

components/esp_rom/esp32h2/esp_rom_caps.h

@@ -34,3 +34,4 @@
 #define ESP_ROM_NO_USB_SERIAL_OUTPUT_API    (1) // ROM does not export the usb-serial-jtag write char function
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
 #define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP     (1) // ROM supports the secure boot fast wakeup feature
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x0) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32h21/Kconfig.soc_caps.in

@@ -106,3 +106,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API
 config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x0

components/esp_rom/esp32h21/esp_rom_caps.h

@@ -32,3 +32,4 @@
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
 #define ESP_ROM_NO_USB_SERIAL_OUTPUT_API    (1) // ROM does not export the usb-serial-jtag write char function
 #define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x0) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32h4/Kconfig.soc_caps.in

@@ -70,3 +70,7 @@ config ESP_ROM_WDT_INIT_PATCH
 config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x2000

components/esp_rom/esp32h4/esp_rom_caps.h

@@ -23,3 +23,4 @@
 #define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
 #define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x2000) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32p4/Kconfig.soc_caps.in

@@ -82,3 +82,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
 config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x2000

components/esp_rom/esp32p4/esp_rom_caps.h

@@ -26,3 +26,4 @@
 #define ESP_ROM_CLIC_INT_TYPE_PATCH         (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt (old revisions)
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x2000) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32s2/Kconfig.soc_caps.in

@@ -66,3 +66,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
 config ESP_ROM_CONSOLE_OUTPUT_SECONDARY
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x1000

components/esp_rom/esp32s2/esp_rom_caps.h

@@ -23,3 +23,4 @@
 #define ESP_ROM_HAS_OUTPUT_TO_CHANNELS_FUNC (1) // ROM has ets_write_char, alias is esp_rom_output_to_channels
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_CONSOLE_OUTPUT_SECONDARY    (1) // The console output functions will also output to the USB-serial secondary console
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x1000) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32s3/Kconfig.soc_caps.in

@@ -126,3 +126,7 @@ config ESP_ROM_CONSOLE_OUTPUT_SECONDARY
 config ESP_ROM_HAS_REGI2C_IMPL
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x0

components/esp_rom/esp32s3/esp_rom_caps.h

@@ -37,3 +37,4 @@
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_CONSOLE_OUTPUT_SECONDARY    (1) // The console output functions will also output to the USB-serial secondary console
 #define ESP_ROM_HAS_REGI2C_IMPL             (1) // ROM has the implementation of REGI2C read/write functions
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x0) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/esp32s31/Kconfig.soc_caps.in

@@ -86,3 +86,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
 config ESP_ROM_PRINTS_LOCKUP_STATUS
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x2000

components/esp_rom/esp32s31/esp_rom_caps.h

@@ -28,3 +28,4 @@
 #define ESP_ROM_HAS_VERSION                 (1) // ROM has version/eco information
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_PRINTS_LOCKUP_STATUS        (1) // ROM bootloader already prints CPU lockup diagnostic status
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x2000) // Bootloader offset in flash determined by the ROM bootloader

components/esp_rom/linux/Kconfig.soc_caps.in

@@ -18,3 +18,7 @@ config ESP_ROM_HAS_ETS_PRINTF_BUG
 config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
     bool
     default y
+
+config ESP_ROM_BOOTLOADER_OFFSET_FLASH
+    hex
+    default 0x0

components/esp_rom/linux/esp_rom_caps.h

@@ -8,3 +8,4 @@
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (-1) // No USB_SERIAL_JTAG in the ROM, set -1 for Kconfig usage.
 #define ESP_ROM_HAS_ETS_PRINTF_BUG          (1)  // The build will include esp_rom_install_uart_printf, which is used for host tests.
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1)  // The Linux target has an implementation of esp_rom_output_putc.
+#define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x0) // Bootloader offset in flash determined by the ROM bootloader