feat(esp_security): suppoer s31 security clock management

components/esp_security/CMakeLists.txt

@@ -8,11 +8,10 @@ endif()
 set(srcs "")
 set(requires esp_hal_security)
 set(priv_requires esp_hw_support hal efuse)
-set(priv_includes "")
+set(priv_includes "src/${IDF_TARGET}")
 
 if(NOT non_os_build)
     list(APPEND srcs "src/init.c")
-    list(APPEND priv_includes "src/${IDF_TARGET}")
 
     if(CONFIG_SOC_HMAC_SUPPORTED)
         list(APPEND srcs "src/esp_hmac.c")
@@ -30,11 +29,12 @@ if(NOT non_os_build)
         list(APPEND srcs "src/esp_dpa_protection.c")
     endif()
 
-    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
+    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c"
+                    "src/${target}/esp_crypto_clk.c")
     list(APPEND priv_requires esp_system esp_timer)
 elseif(esp_tee_build)
-    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
+    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c"
-    list(APPEND includes "src/${IDF_TARGET}")
+                    "src/${target}/esp_crypto_clk.c")
 
     if(CONFIG_SOC_HMAC_SUPPORTED)
         list(APPEND srcs "src/esp_hmac.c")
@@ -44,7 +44,8 @@ elseif(esp_tee_build)
         list(APPEND srcs "src/esp_ds.c")
     endif()
 else()  # BOOTLOADER_BUILD
-    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
+    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c"
+                    "src/${target}/esp_crypto_clk.c")
 
     if(CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY)
         list(APPEND srcs "src/esp_key_mgr.c")

components/esp_security/src/esp32/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32/esp_crypto_clk.h

@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}

components/esp_security/src/esp32c2/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32c2/esp_crypto_clk.h

@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}

components/esp_security/src/esp32c3/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32c3/esp_crypto_clk.h

@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}

components/esp_security/src/esp32c5/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32c5/esp_crypto_clk.h

@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 480M SPLL clock

components/esp_security/src/esp32c6/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32c6/esp_crypto_clk.h

@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}

components/esp_security/src/esp32c61/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32c61/esp_crypto_clk.h

@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 480M SPLL clock

components/esp_security/src/esp32h2/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32h2/esp_crypto_clk.h

@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 96M PLL clock

components/esp_security/src/esp32h21/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32h21/esp_crypto_clk.h

@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 96M PLL clock

components/esp_security/src/esp32h4/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32h4/esp_crypto_clk.h

@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 96M PLL clock

components/esp_security/src/esp32p4/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32p4/esp_crypto_clk.h

@@ -8,6 +8,10 @@
 #include "esp_private/esp_clk_tree_common.h"
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 240M PLL clock

components/esp_security/src/esp32s2/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32s2/esp_crypto_clk.h

@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}

components/esp_security/src/esp32s3/esp_crypto_clk.c

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}

components/esp_security/src/esp32s3/esp_crypto_clk.h

@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}

components/esp_security/src/esp32s31/esp_crypto_clk.c

@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_crypto_clk.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/hp_sys_clkrst_struct.h"
+#if !NON_OS_BUILD
+#include "esp_private/critical_section.h"
+#endif
+
+#if !NON_OS_BUILD
+DEFINE_CRIT_SECTION_LOCK_STATIC(s_crypto_common_clk_mux);
+#endif
+static int s_crypto_common_clk_ref_cnt;
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+#if !NON_OS_BUILD
+    esp_os_enter_critical_safe(&s_crypto_common_clk_mux);
+#endif
+    if (enable) {
+        if (s_crypto_common_clk_ref_cnt++ == 0) {
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 1;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 1;
+        }
+    } else {
+        if (s_crypto_common_clk_ref_cnt > 0 && --s_crypto_common_clk_ref_cnt == 0) {
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 0;
+        }
+    }
+#if !NON_OS_BUILD
+    esp_os_exit_critical_safe(&s_crypto_common_clk_mux);
+#endif
+}

components/esp_security/src/esp32s31/esp_crypto_clk.h

@@ -1,15 +1,20 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include "soc/soc.h"
-#include "soc/hp_sys_clkrst_reg.h"
 
 #pragma once
 
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "soc/hp_sys_clkrst_reg.h"
+#include "soc/hp_sys_clkrst_struct.h"
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 240M PLL clock
     REG_SET_FIELD(HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL, 0x2);
 }
+
+void esp_crypto_common_clk_enable(bool enable);

components/esp_security/src/esp_crypto_periph_clk.c

@@ -8,6 +8,7 @@
 #include "esp_private/esp_crypto_lock_internal.h"
 #include "sdkconfig.h"
 #include "esp_crypto_periph_clk.h"
+#include "esp_crypto_clk.h"
 
 #if SOC_AES_SUPPORTED
 #include "hal/aes_ll.h"
@@ -48,6 +49,7 @@ int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused));
 void esp_crypto_aes_enable_periph_clk(bool enable)
 {
     AES_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         aes_ll_enable_bus_clock(enable);
         if (enable) {
             aes_ll_reset_register();
@@ -66,6 +68,7 @@ void esp_crypto_aes_enable_periph_clk(bool enable)
 void esp_crypto_sha_enable_periph_clk(bool enable)
 {
     SHA_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         sha_ll_enable_bus_clock(enable);
         if (enable) {
             sha_ll_reset_register();
@@ -84,6 +87,7 @@ void esp_crypto_sha_enable_periph_clk(bool enable)
 void esp_crypto_mpi_enable_periph_clk(bool enable)
 {
     MPI_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         mpi_ll_enable_bus_clock(enable);
         if (enable) {
             mpi_ll_power_up();
@@ -99,6 +103,7 @@ void esp_crypto_mpi_enable_periph_clk(bool enable)
 void esp_crypto_ecc_enable_periph_clk(bool enable)
 {
     ECC_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         ecc_ll_enable_bus_clock(enable);
         if (enable) {
             ecc_ll_power_up();
@@ -114,6 +119,7 @@ void esp_crypto_ecc_enable_periph_clk(bool enable)
 void esp_crypto_hmac_enable_periph_clk(bool enable)
 {
     HMAC_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         hmac_ll_enable_bus_clock(enable);
         if (enable) {
             hmac_ll_reset_register();
@@ -126,6 +132,7 @@ void esp_crypto_hmac_enable_periph_clk(bool enable)
 void esp_crypto_ds_enable_periph_clk(bool enable)
 {
     DS_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         ds_ll_enable_bus_clock(enable);
         if (enable) {
             ds_ll_reset_register();
@@ -138,6 +145,7 @@ void esp_crypto_ds_enable_periph_clk(bool enable)
 void esp_crypto_ecdsa_enable_periph_clk(bool enable)
 {
     ECDSA_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         ecdsa_ll_enable_bus_clock(enable);
         if (enable) {
             ecdsa_ll_reset_register();
@@ -150,6 +158,7 @@ void esp_crypto_ecdsa_enable_periph_clk(bool enable)
 void esp_crypto_key_mgr_enable_periph_clk(bool enable)
 {
     KEY_MANAGER_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         key_mgr_ll_power_up();
         key_mgr_ll_enable_bus_clock(enable);
         key_mgr_ll_enable_peripheral_clock(enable);