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refactor(hal_dma): move bitscrambler from hal component

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because bitscrambler can't live without DMA, it's highly binded with the
GDMA peripheral.
This commit is contained in:
morris
2025-11-27 16:06:52 +08:00
parent 88c6d19ad2
commit 69a76c5170
37 changed files with 30 additions and 79 deletions
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components/esp_hal_dma/esp32c2/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/esp32c3/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/esp32c5/include/hal/bitscrambler_ll.h
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/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <limits.h>
#include <stdlib.h>
#include <stdbool.h>
#include "soc/bitscrambler_struct.h"
#include "hal/bitscrambler_types.h"
#include "soc/pcr_struct.h"
#include "soc/hp_system_struct.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define BITSCRAMBLER_LL_GET_HW(num) (((num) == 0) ? (&BITSCRAMBLER) : NULL)
#define BITSCRAMBLER_LL_INST_LEN_WORDS 9 //length of one instruction in 32-bit words as defined by HW
/**
* @brief Select peripheral BitScrambler is attached to
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param peri Peripheral to select, should pick the value from bitscrambler_peri_select.h
*/
static inline void bitscrambler_ll_select_peripheral(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int peri)
{
if (dir == BITSCRAMBLER_DIR_TX) {
HP_SYSTEM.bitscrambler_peri_sel.bitscrambler_tx_sel = peri;
} else { // RX
HP_SYSTEM.bitscrambler_peri_sel.bitscrambler_rx_sel = peri;
}
}
/**
* @brief Enable the BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_enable(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
hw->ctrl[dir].ena = 1;
}
/**
* @brief Disable the BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_disable(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
hw->ctrl[dir].ena = 0;
}
/**
* @brief Write a word to the instruction memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param inst_idx Instruction to write to
* @param word_idx Word within the instruction to write to
* @param data Data to write
*/
static inline void bitscrambler_ll_instmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int inst_idx, int word_idx, uint32_t data)
{
hw->inst_cfg[dir].cfg0.inst_idx = inst_idx;
hw->inst_cfg[dir].cfg0.inst_pos = word_idx;
hw->inst_cfg[dir].cfg1.inst = data;
}
/**
* @brief Read a word from the instruction memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param inst_idx Instruction to write to
* @param word_idx Word within the instruction to write to
*
* @returns Word read from instruction memory
*/
static inline uint32_t bitscrambler_ll_instmem_read(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int inst_idx, int word_idx)
{
hw->inst_cfg[dir].cfg0.inst_idx = inst_idx;
hw->inst_cfg[dir].cfg0.inst_pos = word_idx;
return hw->inst_cfg[dir].cfg1.inst;
}
/**
* @brief Write a word to LUT memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param word_idx Word within the LUT to write to
* @param data Data to write
*/
static inline void bitscrambler_ll_lutmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int word_idx, uint32_t data)
{
hw->lut_cfg[dir].cfg0.lut_idx = word_idx;
hw->lut_cfg[dir].cfg1.lut = data;
}
/**
* @brief Set width of LUT memory (as seen by Bitscrambler, not by host)
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param width Width selection
*/
static inline void bitscrambler_ll_set_lut_width(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_lut_width_t width)
{
hw->lut_cfg[dir].cfg0.lut_mode = width;
}
/**
* @brief Get width of LUT memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline int bitscrambler_ll_get_lut_width(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
return hw->lut_cfg[dir].cfg0.lut_mode;
}
/**
* @brief Enable loopback mode, where the RX BitScrambler is disabled and the TX BitScrambler loops
* back to the receive DMA path to memory.
*
* @param hw BitScrambler hardware instance address.
* @param en True if loopback mode is enabled; false otherwise
*/
static inline void bitscrambler_ll_enable_loopback(bitscrambler_dev_t *hw, bool en)
{
hw->sys.loop_mode = en ? 1 : 0;
}
/**
* @brief Set condition-checking mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_cond_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_cond_mode_t mode)
{
hw->ctrl[dir].cond_mode = mode;
}
/**
* @brief Enable prefetch mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param en True to enable prefetch mode; false to disable
*/
static inline void bitscrambler_ll_enable_prefetch_on_reset(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bool en)
{
// 0: means do data prefetch on reset, 1: means no reset prefetch, user has to load the data manually in the assembly code
hw->ctrl[dir].fetch_mode = en ? 0 : 1;
}
/**
* @brief Set EOF mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_eof_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_eof_mode_t mode)
{
hw->ctrl[dir].eof_mode = mode;
}
/**
* @brief Set mode of dummy-reading after EOF
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_dummy_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_dummy_mode_t mode)
{
hw->ctrl[dir].rd_dummy = mode;
}
/**
* @brief Set halting mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_halt_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_halt_mode_t mode)
{
hw->ctrl[dir].halt_mode = mode;
}
/**
* @brief Set amount of bits to ignore after EOF
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param bitcount Number of bits to ignore
*/
static inline void bitscrambler_ll_set_tailing_bits(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int bitcount)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tail_bits[dir], tailing_bits, bitcount);
}
/**
* @brief Reset BitScrambler FIFO
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_reset_fifo(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
hw->ctrl[dir].fifo_rst = 1;
hw->ctrl[dir].fifo_rst = 0;
}
/**
* @brief Clear trace of EOF counts
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_clear_eof_trace(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
hw->state[dir].eof_trace_clr = 1;
hw->state[dir].eof_trace_clr = 0;
}
/**
* @brief Set state of BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param state One of BITSCRAMBLER_SET_STATE_[RUN|HALT|PAUSE]. Note the WAIT state cannot be set externally.
*/
static inline void bitscrambler_ll_set_state(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_set_state_t state)
{
hw->ctrl[dir].pause = (state == BITSCRAMBLER_SET_STATE_PAUSE) ? 1 : 0;
hw->ctrl[dir].halt = (state == BITSCRAMBLER_SET_STATE_HALT) ? 1 : 0;
}
/**
* @brief Return current BitScrambler state
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*
* @returns one of BITSCRAMBLER_STATE_* values
*/
static inline bitscrambler_state_t bitscrambler_ll_get_current_state(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
if (hw->state[dir].in_idle) {
return BITSCRAMBLER_STATE_IDLE;
}
if (hw->state[dir].in_run) {
return BITSCRAMBLER_STATE_RUN;
}
if (hw->state[dir].in_wait) {
return BITSCRAMBLER_STATE_WAIT;
}
if (hw->state[dir].in_pause) {
return BITSCRAMBLER_STATE_PAUSED;
}
return BITSCRAMBLER_STATE_UNKNOWN;
}
/**
* @brief Return if the bitscrambler FIFO is ready
*
* @note For TX, means the outfifo is not empty, then we can start the peripheral to transmit the data
* For RX, means the infifo is not full, then we can start the peripheral to receive the data
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @return true if FIFO is ready, false otherwise
*/
static inline bool bitscrambler_ll_is_fifo_ready(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
return hw->state[dir].fifo_empty;
}
/**
* @brief Enable the bus clock for BitScrambler module
*/
static inline void bitscrambler_ll_set_bus_clock_sys_enable(bool enable)
{
PCR.bs_conf.bs_clk_en = enable;
}
/**
* @brief Enable the bus clock for RX BitScrambler module
*/
static inline void bitscrambler_ll_set_bus_clock_rx_enable(bool enable)
{
// empty
}
/**
* @brief Enable the bus clock for TX BitScrambler module
*/
static inline void bitscrambler_ll_set_bus_clock_tx_enable(bool enable)
{
// empty
}
/**
* @brief Force power on the bitscrambler memory block, regardless of the outside PMU logic
*/
static inline void bitscrambler_ll_mem_force_power_on(void)
{
PCR.bs_pd_ctrl.bs_mem_force_pu = 1;
PCR.bs_pd_ctrl.bs_mem_force_pd = 0;
}
/**
* @brief Force power off the bitscrambler memory block, regardless of the outside PMU logic
*/
static inline void bitscrambler_ll_mem_force_power_off(void)
{
PCR.bs_pd_ctrl.bs_mem_force_pd = 1;
PCR.bs_pd_ctrl.bs_mem_force_pu = 0;
}
/**
* @brief Power control the bitscrambler memory block by the outside PMU logic
*/
static inline void bitscrambler_ll_mem_power_by_pmu(void)
{
PCR.bs_pd_ctrl.bs_mem_force_pd = 0;
PCR.bs_pd_ctrl.bs_mem_force_pu = 0;
}
/**
* @brief Reset the BitScrambler module
*/
static inline void bitscrambler_ll_reset_sys(void)
{
PCR.bs_conf.bs_rst_en = 1;
PCR.bs_conf.bs_rst_en = 0;
}
/**
* @brief Reset the BitScrambler RX module
*/
static inline void bitscrambler_ll_reset_rx(void)
{
PCR.bs_func_conf.bs_rx_rst_en = 1;
PCR.bs_func_conf.bs_rx_rst_en = 0;
}
/**
* @brief Reset the BitScrambler TX module
*/
static inline void bitscrambler_ll_reset_tx(void)
{
PCR.bs_func_conf.bs_tx_rst_en = 1;
PCR.bs_func_conf.bs_tx_rst_en = 0;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_dma/esp32c5/include/hal/bitscrambler_peri_select.h
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/*
* @brief BitScrambler attachment targets
* Note that these are the values written to HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG.
*/
#define SOC_BITSCRAMBLER_ATTACH_NONE -1
#define SOC_BITSCRAMBLER_ATTACH_GPSPI2 1
#define SOC_BITSCRAMBLER_ATTACH_UHCI 2
#define SOC_BITSCRAMBLER_ATTACH_I2S0 3
#define SOC_BITSCRAMBLER_ATTACH_AES 4
#define SOC_BITSCRAMBLER_ATTACH_SHA 5
#define SOC_BITSCRAMBLER_ATTACH_ADC 6
#define SOC_BITSCRAMBLER_ATTACH_PARL_IO 7
#define SOC_BITSCRAMBLER_ATTACH_MAX 7
components/esp_hal_dma/esp32c5/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (1)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/esp32c6/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/esp32c61/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (1)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/esp32h2/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/esp32h21/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/esp32h4/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI3 (0)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (1)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (4)
#define SOC_GDMA_TRIG_PERIPH_ASRC0 (5)
#define SOC_GDMA_TRIG_PERIPH_ASRC1 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI3_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ASRC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ASRC1_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/esp32p4/include/hal/bitscrambler_ll.h
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <limits.h>
#include <stdlib.h>
#include <stdbool.h>
#include "soc/bitscrambler_struct.h"
#include "hal/bitscrambler_types.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/hp_system_struct.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define BITSCRAMBLER_LL_GET_HW(num) (((num) == 0) ? (&BITSCRAMBLER) : NULL)
#define BITSCRAMBLER_LL_INST_LEN_WORDS 9 //length of one instruction in 32-bit words as defined by HW
/**
* @brief Select peripheral BitScrambler is attached to
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param peri Peripheral to select, should pick the value from bitscrambler_peri_select.h
*/
static inline void bitscrambler_ll_select_peripheral(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int peri)
{
if (dir == BITSCRAMBLER_DIR_TX) {
HP_SYSTEM.bitscrambler_peri_sel.bitscrambler_peri_tx_sel = peri;
} else { // RX
HP_SYSTEM.bitscrambler_peri_sel.bitscrambler_peri_rx_sel = peri;
}
}
/**
* @brief Enable the BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_enable(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
hw->ctrl[dir].ena = 1;
}
/**
* @brief Disable the BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_disable(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
hw->ctrl[dir].ena = 0;
}
/**
* @brief Write a word to the instruction memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param inst_idx Instruction to write to
* @param word_idx Word within the instruction to write to
* @param data Data to write
*/
static inline void bitscrambler_ll_instmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int inst_idx, int word_idx, uint32_t data)
{
hw->inst_cfg[dir].cfg0.inst_idx = inst_idx;
hw->inst_cfg[dir].cfg0.inst_pos = word_idx;
hw->inst_cfg[dir].cfg1.inst = data;
}
/**
* @brief Read a word from the instruction memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param inst_idx Instruction to write to
* @param word_idx Word within the instruction to write to
*
* @returns Word read from instruction memory
*/
static inline uint32_t bitscrambler_ll_instmem_read(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int inst_idx, int word_idx)
{
hw->inst_cfg[dir].cfg0.inst_idx = inst_idx;
hw->inst_cfg[dir].cfg0.inst_pos = word_idx;
return hw->inst_cfg[dir].cfg1.inst;
}
/**
* @brief Write a word to LUT memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param word_idx Word within the LUT to write to
* @param data Data to write
*/
static inline void bitscrambler_ll_lutmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int word_idx, uint32_t data)
{
hw->lut_cfg[dir].cfg0.lut_idx = word_idx;
hw->lut_cfg[dir].cfg1.lut = data;
}
/**
* @brief Set width of LUT memory (as seen by Bitscrambler, not by host)
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param width Width selection
*/
static inline void bitscrambler_ll_set_lut_width(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_lut_width_t width)
{
hw->lut_cfg[dir].cfg0.lut_mode = width;
}
/**
* @brief Get width of LUT memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline int bitscrambler_ll_get_lut_width(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
return hw->lut_cfg[dir].cfg0.lut_mode;
}
/**
* @brief Enable loopback mode, where the RX BitScrambler is disabled and the TX BitScrambler loops
* back to the receive DMA path to memory.
*
* @param hw BitScrambler hardware instance address.
* @param en True if loopback mode is enabled; false otherwise
*/
static inline void bitscrambler_ll_enable_loopback(bitscrambler_dev_t *hw, bool en)
{
hw->sys.loop_mode = en ? 1 : 0;
}
/**
* @brief Set condition-checking mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_cond_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_cond_mode_t mode)
{
hw->ctrl[dir].cond_mode = mode;
}
/**
* @brief Enable prefetch mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param en True to enable prefetch mode; false to disable
*/
static inline void bitscrambler_ll_enable_prefetch_on_reset(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bool en)
{
// 0: means do data prefetch on reset, 1: means no reset prefetch, user has to load the data manually in the assembly code
hw->ctrl[dir].fetch_mode = en ? 0 : 1;
}
/**
* @brief Set EOF mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_eof_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_eof_mode_t mode)
{
hw->ctrl[dir].eof_mode = mode;
}
/**
* @brief Set mode of dummy-reading after EOF
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_dummy_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_dummy_mode_t mode)
{
hw->ctrl[dir].rd_dummy = mode;
}
/**
* @brief Set halting mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_halt_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_halt_mode_t mode)
{
hw->ctrl[dir].halt_mode = mode;
}
/**
* @brief Set amount of bits to ignore after EOF
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param bitcount Number of bits to ignore
*/
static inline void bitscrambler_ll_set_tailing_bits(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int bitcount)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tail_bits[dir], tailing_bits, bitcount);
}
/**
* @brief Reset BitScrambler FIFO
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_reset_fifo(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
hw->ctrl[dir].fifo_rst = 1;
hw->ctrl[dir].fifo_rst = 0;
}
/**
* @brief Clear trace of EOF counts
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_clear_eof_trace(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
hw->state[dir].eof_trace_clr = 1;
hw->state[dir].eof_trace_clr = 0;
}
/**
* @brief Set state of BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param state One of BITSCRAMBLER_SET_STATE_[RUN|HALT|PAUSE]. Note the WAIT state cannot be set externally.
*/
static inline void bitscrambler_ll_set_state(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_set_state_t state)
{
hw->ctrl[dir].pause = (state == BITSCRAMBLER_SET_STATE_PAUSE) ? 1 : 0;
hw->ctrl[dir].halt = (state == BITSCRAMBLER_SET_STATE_HALT) ? 1 : 0;
}
/**
* @brief Return current BitScrambler state
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*
* @returns one of BITSCRAMBLER_STATE_* values
*/
static inline bitscrambler_state_t bitscrambler_ll_get_current_state(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
if (hw->state[dir].in_idle) {
return BITSCRAMBLER_STATE_IDLE;
}
if (hw->state[dir].in_run) {
return BITSCRAMBLER_STATE_RUN;
}
if (hw->state[dir].in_wait) {
return BITSCRAMBLER_STATE_WAIT;
}
if (hw->state[dir].in_pause) {
return BITSCRAMBLER_STATE_PAUSED;
}
return BITSCRAMBLER_STATE_UNKNOWN;
}
/**
* @brief Return if the bitscrambler FIFO is ready
*
* @note For TX, means the outfifo is not empty, then we can start the peripheral to transmit the data
* For RX, means the infifo is not full, then we can start the peripheral to receive the data
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @return true if FIFO is ready, false otherwise
*/
static inline bool bitscrambler_ll_is_fifo_ready(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
return hw->state[dir].fifo_empty;
}
/**
* @brief Enable the bus clock for BitScrambler module
*/
static inline void _bitscrambler_ll_set_bus_clock_sys_enable(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl1.reg_bitscrambler_sys_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define bitscrambler_ll_set_bus_clock_sys_enable(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_bitscrambler_ll_set_bus_clock_sys_enable(__VA_ARGS__); \
} while (0)
/**
* @brief Enable the bus clock for RX BitScrambler module
*/
static inline void _bitscrambler_ll_set_bus_clock_rx_enable(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl1.reg_bitscrambler_rx_sys_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define bitscrambler_ll_set_bus_clock_rx_enable(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_bitscrambler_ll_set_bus_clock_rx_enable(__VA_ARGS__); \
} while (0)
/**
* @brief Enable the bus clock for TX BitScrambler module
*/
static inline void _bitscrambler_ll_set_bus_clock_tx_enable(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl1.reg_bitscrambler_tx_sys_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define bitscrambler_ll_set_bus_clock_tx_enable(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_bitscrambler_ll_set_bus_clock_tx_enable(__VA_ARGS__); \
} while (0)
/**
* @brief Force power on the bitscrambler memory block, regardless of the outside PMU logic
*/
static inline void bitscrambler_ll_mem_force_power_on(void)
{
// empty
}
/**
* @brief Force power off the bitscrambler memory block, regardless of the outside PMU logic
*/
static inline void bitscrambler_ll_mem_force_power_off(void)
{
// empty
}
/**
* @brief Power control the bitscrambler memory block by the outside PMU logic
*/
static inline void bitscrambler_ll_mem_power_by_pmu(void)
{
// empty
}
/**
* @brief Reset the BitScrambler module
*/
static inline void _bitscrambler_ll_reset_sys(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define bitscrambler_ll_reset_sys(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_bitscrambler_ll_reset_sys(__VA_ARGS__); \
} while (0)
/**
* @brief Reset the BitScrambler RX module
*/
static inline void _bitscrambler_ll_reset_rx(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler_rx = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler_rx = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define bitscrambler_ll_reset_rx(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_bitscrambler_ll_reset_rx(__VA_ARGS__); \
} while (0)
/**
* @brief Reset the BitScrambler TX module
*/
static inline void _bitscrambler_ll_reset_tx(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler_tx = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler_tx = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define bitscrambler_ll_reset_tx(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_bitscrambler_ll_reset_tx(__VA_ARGS__); \
} while (0)
#ifdef __cplusplus
}
#endif
components/esp_hal_dma/esp32p4/include/hal/bitscrambler_peri_select.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/*
* @brief BitScrambler attachment targets
* Note that these are the values written to HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG.
*/
#define SOC_BITSCRAMBLER_ATTACH_NONE -1
#define SOC_BITSCRAMBLER_ATTACH_LCD_CAM 0
#define SOC_BITSCRAMBLER_ATTACH_GPSPI2 1
#define SOC_BITSCRAMBLER_ATTACH_GPSPI3 2
#define SOC_BITSCRAMBLER_ATTACH_PARL_IO 3
#define SOC_BITSCRAMBLER_ATTACH_AES 4
#define SOC_BITSCRAMBLER_ATTACH_SHA 5
#define SOC_BITSCRAMBLER_ATTACH_ADC 6
#define SOC_BITSCRAMBLER_ATTACH_I2S0 7
#define SOC_BITSCRAMBLER_ATTACH_I2S1 8
#define SOC_BITSCRAMBLER_ATTACH_I2S2 9
#define SOC_BITSCRAMBLER_ATTACH_I3C_MST 10
#define SOC_BITSCRAMBLER_ATTACH_UHCI 11
#define SOC_BITSCRAMBLER_ATTACH_RMT 12
#define SOC_BITSCRAMBLER_ATTACH_MAX 12
components/esp_hal_dma/esp32p4/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 -1
#define SOC_GDMA_TRIG_PERIPH_I3C0 0
#define SOC_GDMA_TRIG_PERIPH_UHCI0 2
#define SOC_GDMA_TRIG_PERIPH_I2S0 3
#define SOC_GDMA_TRIG_PERIPH_I2S1 4
#define SOC_GDMA_TRIG_PERIPH_I2S2 5
#define SOC_GDMA_TRIG_PERIPH_ADC0 8
#define SOC_GDMA_TRIG_PERIPH_RMT0 10
#define SOC_GDMA_TRIG_PERIPH_LCD0 0
#define SOC_GDMA_TRIG_PERIPH_CAM0 0
#define SOC_GDMA_TRIG_PERIPH_SPI2 1
#define SOC_GDMA_TRIG_PERIPH_SPI3 2
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 3
#define SOC_GDMA_TRIG_PERIPH_AES0 4
#define SOC_GDMA_TRIG_PERIPH_SHA0 5
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY -1
#define SOC_GDMA_BUS_AHB 0
#define SOC_GDMA_BUS_AXI 1
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S1_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_RMT0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I3C0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AXI
#define SOC_GDMA_TRIG_PERIPH_SPI3_BUS SOC_GDMA_BUS_AXI
#define SOC_GDMA_TRIG_PERIPH_LCD0_BUS SOC_GDMA_BUS_AXI
#define SOC_GDMA_TRIG_PERIPH_CAM0_BUS SOC_GDMA_BUS_AXI
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AXI
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AXI
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AXI
components/esp_hal_dma/esp32s3/include/hal/gdma_channel.h
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/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_SPI3 (1)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_I2S1 (4)
#define SOC_GDMA_TRIG_PERIPH_LCD0 (5)
#define SOC_GDMA_TRIG_PERIPH_CAM0 (5)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_RMT0 (9)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SPI3_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S1_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_LCD0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_CAM0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_RMT0_BUS SOC_GDMA_BUS_AHB
components/esp_hal_dma/include/hal/bitscrambler_types.h
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#if __has_include("hal/bitscrambler_peri_select.h")
#include "hal/bitscrambler_peri_select.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief BitScrambler transport direction
*/
typedef enum {
BITSCRAMBLER_DIR_TX = 0, /*!< Transmit, so mem to device (or mem to mem in loopback mode) */
BITSCRAMBLER_DIR_RX = 1 /*!< Receive, so device to memory */
} bitscrambler_direction_t;
/**
* @brief BitScrambler LUT (look up table) width
*/
typedef enum {
BITSCRAMBLER_LUT_WIDTH_8BIT = 0, /*!< 8-bit LUT */
BITSCRAMBLER_LUT_WIDTH_16BIT = 1, /*!< 16-bit LUT */
BITSCRAMBLER_LUT_WIDTH_32BIT = 2, /*!< 32-bit LUT */
} bitscrambler_lut_width_t;
/**
* @brief EOF signal generating mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_EOF_MODE_READ = 0, /*!< EOF is counted by reading the source FIFO */
BITSCRAMBLER_EOF_MODE_WRITE = 1, /*!< EOF is counted by writing the destination FIFO */
} bitscrambler_eof_mode_t;
/**
* @brief Condition mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_COND_MODE_LESSTHAN = 0, /*!< Use "<=" to generate the condition */
BITSCRAMBLER_COND_MODE_NOTEQUAL = 1, /*!< Use "!=" to generate the condition */
} bitscrambler_cond_mode_t;
/**
* @brief Halt mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_HALT_WAIT_WRITES = 0, /*!< Wait data write back */
BITSCRAMBLER_HALT_IGNORE_WRITES = 1, /*!< Ignore write data back */
} bitscrambler_halt_mode_t;
/**
* @brief Dummy mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_DUMMY_MODE_HALT = 0, /*!< Halt and wait the read data */
BITSCRAMBLER_DUMMY_MODE_DUMMY = 1, /*!< Ignore the read data */
} bitscrambler_dummy_mode_t;
/**
* @brief Commands to set the state of bitscrambler
*
* @note Pause->Run, bitscrambler can continue from the last instruction;
* Halt->Run, bitscrambler will start from the first instruction;
*/
typedef enum {
BITSCRAMBLER_SET_STATE_RUN, /*!< Run */
BITSCRAMBLER_SET_STATE_HALT, /*!< Halt */
BITSCRAMBLER_SET_STATE_PAUSE, /*!< Pause */
} bitscrambler_set_state_t;
/**
* @brief Status of bitscrambler
*/
typedef enum {
BITSCRAMBLER_STATE_IDLE, /*!< Idle (halt) */
BITSCRAMBLER_STATE_RUN, /*!< Running */
BITSCRAMBLER_STATE_WAIT, /*!< Waiting data write back */
BITSCRAMBLER_STATE_PAUSED, /*!< Paused */
BITSCRAMBLER_STATE_UNKNOWN /*!< Invalid, should never be returned */
} bitscrambler_state_t;
#ifdef __cplusplus
}
#endif
components/esp_hal_dma/include/hal/gdma_types.h
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enumeration of peripherals which have the DMA capability
* @note Some peripheral might not be available on certain chip, please refer to `soc_caps.h` for detail.
*/
typedef enum {
GDMA_TRIG_PERIPH_M2M, /*!< GDMA trigger peripheral: M2M */
GDMA_TRIG_PERIPH_UHCI, /*!< GDMA trigger peripheral: UHCI */
GDMA_TRIG_PERIPH_SPI, /*!< GDMA trigger peripheral: SPI */
GDMA_TRIG_PERIPH_I2S, /*!< GDMA trigger peripheral: I2S */
GDMA_TRIG_PERIPH_AES, /*!< GDMA trigger peripheral: AES */
GDMA_TRIG_PERIPH_SHA, /*!< GDMA trigger peripheral: SHA */
GDMA_TRIG_PERIPH_ADC, /*!< GDMA trigger peripheral: ADC */
GDMA_TRIG_PERIPH_DAC, /*!< GDMA trigger peripheral: DAC */
GDMA_TRIG_PERIPH_LCD, /*!< GDMA trigger peripheral: LCD */
GDMA_TRIG_PERIPH_CAM, /*!< GDMA trigger peripheral: CAM */
GDMA_TRIG_PERIPH_RMT, /*!< GDMA trigger peripheral: RMT */
GDMA_TRIG_PERIPH_PARLIO, /*!< GDMA trigger peripheral: PARLIO */
GDMA_TRIG_PERIPH_I3C, /*!< GDMA trigger peripheral: I3C */
} gdma_trigger_peripheral_t;
/**
* @brief Enumeration of GDMA channel direction
*/
typedef enum {
GDMA_CHANNEL_DIRECTION_TX, /*!< GDMA channel direction: TX */
GDMA_CHANNEL_DIRECTION_RX, /*!< GDMA channel direction: RX */
} gdma_channel_direction_t;
/**
* @brief GDMA channel events that supported by the ETM module
*/
typedef enum {
GDMA_ETM_EVENT_EOF, /*!< Event that the GDMA engine meets EOF descriptor */
GDMA_ETM_EVENT_MAX, /*!< Maximum number of events */
} gdma_etm_event_type_t;
/**
* @brief GDMA channel tasks that supported by the ETM module
*/
typedef enum {
GDMA_ETM_TASK_START, /*!< Start the GDMA machine */
GDMA_ETM_TASK_MAX, /*!< Maximum number of events */
} gdma_etm_task_type_t;
#ifdef __cplusplus
}
#endif