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feat(hal): disable P4 TG WDT clock by default

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This commit is contained in:
wuzhenghui
2026-06-15 10:31:06 +08:00
parent 85081d2414
commit 691dc44d6f
5 changed files with 27 additions and 13 deletions
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components/esp_hal_clock/esp32p4/include/hal/clk_gate_ll.h
+2 -2
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@@ -245,9 +245,9 @@ static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason,
REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN |
HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL20_REG, HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN |
HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN);
HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN | HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL21_REG, HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN |
HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN);
HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN | HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN);
REG_CLR_BIT(DSI_BRG_HOST_CTRL_REG, DSI_BRG_DSI_CFG_REF_CLK_EN);
REG_CLR_BIT(SDHOST_CLK_EDGE_SEL_REG, SDHOST_CCLK_EN);