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feat(ledc): add ETM support for LEDC peripheral

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Closes https://github.com/espressif/esp-idf/issues/11855
This commit is contained in:
Song Ruo Jing
2025-11-14 20:58:17 +08:00
parent ca9b6b9607
commit 68f9d729cf
49 changed files with 2070 additions and 21 deletions
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components/hal/esp32c2/include/hal/ledc_ll.h
+48
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@@ -20,10 +20,13 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_DUTY_NUM_CH0_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_DUTY_CYCLE_CH0_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_DUTY_SCALE_CH0_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
@@ -587,6 +590,51 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c3/include/hal/ledc_ll.h
+48
View File
@@ -21,10 +21,13 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_DUTY_NUM_LSCH0_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_DUTY_CYCLE_LSCH0_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_DUTY_SCALE_LSCH0_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_LSCH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
@@ -589,6 +592,51 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_rst = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c5/include/hal/ledc_ll.h
+155
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@@ -16,6 +16,7 @@
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "soc/soc_caps.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
@@ -23,14 +24,105 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_RANGE0_SCALE_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS
// Channel tasks: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = LEDC_TASK_DUTY_SCALE_UPDATE_CH0, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = LEDC_TASK_SIG_OUT_DIS_CH0, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = LEDC_TASK_OVF_CNT_RST_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = LEDC_TASK_GAMMA_RESTART_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = LEDC_TASK_GAMMA_PAUSE_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = LEDC_TASK_GAMMA_RESUME_CH0, \
}}[(group)][(task)] + (channel))
#define LEDC_LL_ETM_CHANNEL_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_CHANNEL_TASK_EN_BIT(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = BIT(LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = BIT(LEDC_TASK_SIG_OUT_DIS_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = BIT(LEDC_TASK_OVF_CNT_RST_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = BIT(LEDC_TASK_GAMMA_RESTART_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = BIT(LEDC_TASK_GAMMA_PAUSE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = BIT(LEDC_TASK_GAMMA_RESUME_CH0_EN_S), \
}}[(group)][(task)] << (channel))
// Channel events: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_EVENT_ID(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = LEDC_EVT_DUTY_CHNG_END_CH0, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = LEDC_EVT_OVF_CNT_PLS_CH0, \
}}[(group)][(event)] + (channel))
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_BIT(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = BIT(LEDC_EVT_DUTY_CHNG_END_CH0_EN_S), \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = BIT(LEDC_EVT_OVF_CNT_PLS_CH0_EN_S), \
}}[(group)][(event)] << (channel))
// Timer tasks: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_TASK_ID(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = LEDC_TASK_TIMER0_RST, \
[LEDC_TIMER_ETM_TASK_RESUME] = LEDC_TASK_TIMER0_RESUME, \
[LEDC_TIMER_ETM_TASK_PAUSE] = LEDC_TASK_TIMER0_PAUSE, \
}}[(group)][(task)] + (timer))
#define LEDC_LL_ETM_TIMER_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_TIMER_TASK_EN_BIT(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = BIT(LEDC_TASK_TIMER0_RST_EN_S), \
[LEDC_TIMER_ETM_TASK_RESUME] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
[LEDC_TIMER_ETM_TASK_PAUSE] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
}}[(group)][(task)] << (timer))
// Timer events: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_EVENT_ID(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = LEDC_EVT_TIME_OVF_TIMER0, \
}}[(group)][(event)] + (timer))
#define LEDC_LL_ETM_TIMER_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_TIMER_EVENT_EN_BIT(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = BIT(LEDC_EVT_TIME_OVF_TIMER0_EN_S), \
}}[(group)][(event)] << (timer))
/**
* @brief Enable peripheral register clock
*
@@ -587,6 +679,69 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable ETM event/task
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param reg_addr Register address to control the ETM event/task
* @param bit Bit position in the register
* @param enable Enable or disable the ETM event/task
*/
static inline void ledc_ll_etm_enable_evt_task(ledc_dev_t *hw, ledc_mode_t speed_mode, volatile uint32_t *reg_addr, uint32_t bit, bool enable)
{
if (enable) {
REG_SET_BIT(reg_addr, bit);
} else {
REG_CLR_BIT(reg_addr, bit);
}
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c6/include/hal/ledc_ll.h
+155
View File
@@ -17,6 +17,7 @@
#include "hal/assert.h"
#include "esp_rom_sys.h" //for sync issue workaround
#include "soc/soc_caps.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
@@ -24,10 +25,13 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_DUTY_NUM_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_DUTY_CYCLE_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_SCALE_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS
@@ -35,6 +39,94 @@ extern "C" {
#define LEDC_LL_GLOBAL_CLK_NC_BY_DEFAULT 1
#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST // The temporal global clock source to set to at least make the LEDC core clock on
// Channel tasks: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = LEDC_TASK_DUTY_SCALE_UPDATE_CH0, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = LEDC_TASK_SIG_OUT_DIS_CH0, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = LEDC_TASK_OVF_CNT_RST_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = LEDC_TASK_GAMMA_RESTART_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = LEDC_TASK_GAMMA_PAUSE_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = LEDC_TASK_GAMMA_RESUME_CH0, \
}}[(group)][(task)] + (channel))
#define LEDC_LL_ETM_CHANNEL_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_CHANNEL_TASK_EN_BIT(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = BIT(LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = BIT(LEDC_TASK_SIG_OUT_DIS_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = BIT(LEDC_TASK_OVF_CNT_RST_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = BIT(LEDC_TASK_GAMMA_RESTART_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = BIT(LEDC_TASK_GAMMA_PAUSE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = BIT(LEDC_TASK_GAMMA_RESUME_CH0_EN_S), \
}}[(group)][(task)] << (channel))
// Channel events: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_EVENT_ID(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = LEDC_EVT_DUTY_CHNG_END_CH0, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = LEDC_EVT_OVF_CNT_PLS_CH0, \
}}[(group)][(event)] + (channel))
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_BIT(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = BIT(LEDC_EVT_DUTY_CHNG_END_CH0_EN_S), \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = BIT(LEDC_EVT_OVF_CNT_PLS_CH0_EN_S), \
}}[(group)][(event)] << (channel))
// Timer tasks: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_TASK_ID(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = LEDC_TASK_TIMER0_RST, \
[LEDC_TIMER_ETM_TASK_RESUME] = LEDC_TASK_TIMER0_RESUME, \
[LEDC_TIMER_ETM_TASK_PAUSE] = LEDC_TASK_TIMER0_PAUSE, \
}}[(group)][(task)] + (timer))
#define LEDC_LL_ETM_TIMER_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_TIMER_TASK_EN_BIT(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = BIT(LEDC_TASK_TIMER0_RST_EN_S), \
[LEDC_TIMER_ETM_TASK_RESUME] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
[LEDC_TIMER_ETM_TASK_PAUSE] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
}}[(group)][(task)] << (timer))
// Timer events: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_EVENT_ID(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = LEDC_EVT_TIME_OVF_TIMER0, \
}}[(group)][(event)] + (timer))
#define LEDC_LL_ETM_TIMER_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_TIMER_EVENT_EN_BIT(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = BIT(LEDC_EVT_TIME_OVF_TIMER0_EN_S), \
}}[(group)][(event)] << (timer))
/**
* @brief Enable peripheral register clock
*
@@ -709,6 +801,69 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable ETM event/task
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param reg_addr Register address to control the ETM event/task
* @param bit Bit position in the register
* @param enable Enable or disable the ETM event/task
*/
static inline void ledc_ll_etm_enable_evt_task(ledc_dev_t *hw, ledc_mode_t speed_mode, volatile uint32_t *reg_addr, uint32_t bit, bool enable)
{
if (enable) {
REG_SET_BIT(reg_addr, bit);
} else {
REG_CLR_BIT(reg_addr, bit);
}
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c61/include/hal/ledc_ll.h
+157
View File
@@ -16,6 +16,7 @@
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "soc/soc_caps.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
@@ -23,14 +24,105 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_RANGE0_SCALE_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS
// Channel tasks: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = LEDC_TASK_DUTY_SCALE_UPDATE_CH0, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = LEDC_TASK_SIG_OUT_DIS_CH0, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = LEDC_TASK_OVF_CNT_RST_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = LEDC_TASK_GAMMA_RESTART_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = LEDC_TASK_GAMMA_PAUSE_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = LEDC_TASK_GAMMA_RESUME_CH0, \
}}[(group)][(task)] + (channel))
#define LEDC_LL_ETM_CHANNEL_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_CHANNEL_TASK_EN_BIT(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = BIT(LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = BIT(LEDC_TASK_SIG_OUT_DIS_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = BIT(LEDC_TASK_OVF_CNT_RST_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = BIT(LEDC_TASK_GAMMA_RESTART_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = BIT(LEDC_TASK_GAMMA_PAUSE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = BIT(LEDC_TASK_GAMMA_RESUME_CH0_EN_S), \
}}[(group)][(task)] << (channel))
// Channel events: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_EVENT_ID(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = LEDC_EVT_DUTY_CHNG_END_CH0, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = LEDC_EVT_OVF_CNT_PLS_CH0, \
}}[(group)][(event)] + (channel))
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_BIT(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = BIT(LEDC_EVT_DUTY_CHNG_END_CH0_EN_S), \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = BIT(LEDC_EVT_OVF_CNT_PLS_CH0_EN_S), \
}}[(group)][(event)] << (channel))
// Timer tasks: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_TASK_ID(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = LEDC_TASK_TIMER0_RST, \
[LEDC_TIMER_ETM_TASK_RESUME] = LEDC_TASK_TIMER0_RESUME, \
[LEDC_TIMER_ETM_TASK_PAUSE] = LEDC_TASK_TIMER0_PAUSE, \
}}[(group)][(task)] + (timer))
#define LEDC_LL_ETM_TIMER_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_TIMER_TASK_EN_BIT(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = BIT(LEDC_TASK_TIMER0_RST_EN_S), \
[LEDC_TIMER_ETM_TASK_RESUME] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
[LEDC_TIMER_ETM_TASK_PAUSE] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
}}[(group)][(task)] << (timer))
// Timer events: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_EVENT_ID(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = LEDC_EVT_TIME_OVF_TIMER0, \
}}[(group)][(event)] + (timer))
#define LEDC_LL_ETM_TIMER_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_TIMER_EVENT_EN_BIT(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = BIT(LEDC_EVT_TIME_OVF_TIMER0_EN_S), \
}}[(group)][(event)] << (timer))
/**
* @brief Enable peripheral register clock
*
@@ -587,6 +679,71 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable ETM event/task
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param reg_addr Register address to control the ETM event/task
* @param bit Bit position in the register
* @param enable Enable or disable the ETM event/task
*
* @return None
*/
static inline void ledc_ll_etm_enable_evt_task(ledc_dev_t *hw, ledc_mode_t speed_mode, volatile uint32_t *reg_addr, uint32_t bit, bool enable)
{
if (enable) {
REG_SET_BIT(reg_addr, bit);
} else {
REG_CLR_BIT(reg_addr, bit);
}
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32h2/include/hal/ledc_ll.h
+155
View File
@@ -17,6 +17,7 @@
#include "hal/assert.h"
#include "esp_rom_sys.h" //for sync issue workaround
#include "soc/soc_caps.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
@@ -24,14 +25,105 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_DUTY_NUM_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_DUTY_CYCLE_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_SCALE_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS
// Channel tasks: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = LEDC_TASK_DUTY_SCALE_UPDATE_CH0, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = LEDC_TASK_SIG_OUT_DIS_CH0, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = LEDC_TASK_OVF_CNT_RST_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = LEDC_TASK_GAMMA_RESTART_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = LEDC_TASK_GAMMA_PAUSE_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = LEDC_TASK_GAMMA_RESUME_CH0, \
}}[(group)][(task)] + (channel))
#define LEDC_LL_ETM_CHANNEL_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_CHANNEL_TASK_EN_BIT(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = BIT(LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = BIT(LEDC_TASK_SIG_OUT_DIS_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = BIT(LEDC_TASK_OVF_CNT_RST_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = BIT(LEDC_TASK_GAMMA_RESTART_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = BIT(LEDC_TASK_GAMMA_PAUSE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = BIT(LEDC_TASK_GAMMA_RESUME_CH0_EN_S), \
}}[(group)][(task)] << (channel))
// Channel events: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_EVENT_ID(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = LEDC_EVT_DUTY_CHNG_END_CH0, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = LEDC_EVT_OVF_CNT_PLS_CH0, \
}}[(group)][(event)] + (channel))
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_BIT(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = BIT(LEDC_EVT_DUTY_CHNG_END_CH0_EN_S), \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = BIT(LEDC_EVT_OVF_CNT_PLS_CH0_EN_S), \
}}[(group)][(event)] << (channel))
// Timer tasks: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_TASK_ID(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = LEDC_TASK_TIMER0_RST, \
[LEDC_TIMER_ETM_TASK_RESUME] = LEDC_TASK_TIMER0_RESUME, \
[LEDC_TIMER_ETM_TASK_PAUSE] = LEDC_TASK_TIMER0_PAUSE, \
}}[(group)][(task)] + (timer))
#define LEDC_LL_ETM_TIMER_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_TIMER_TASK_EN_BIT(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = BIT(LEDC_TASK_TIMER0_RST_EN_S), \
[LEDC_TIMER_ETM_TASK_RESUME] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
[LEDC_TIMER_ETM_TASK_PAUSE] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
}}[(group)][(task)] << (timer))
// Timer events: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_EVENT_ID(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = LEDC_EVT_TIME_OVF_TIMER0, \
}}[(group)][(event)] + (timer))
#define LEDC_LL_ETM_TIMER_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_TIMER_EVENT_EN_BIT(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = BIT(LEDC_EVT_TIME_OVF_TIMER0_EN_S), \
}}[(group)][(event)] << (timer))
/**
* @brief Enable peripheral register clock
*
@@ -706,6 +798,69 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable ETM event/task
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param reg_addr Register address to control the ETM event/task
* @param bit Bit position in the register
* @param enable Enable or disable the ETM event/task
*/
static inline void ledc_ll_etm_enable_evt_task(ledc_dev_t *hw, ledc_mode_t speed_mode, volatile uint32_t *reg_addr, uint32_t bit, bool enable)
{
if (enable) {
REG_SET_BIT(reg_addr, bit);
} else {
REG_CLR_BIT(reg_addr, bit);
}
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32h21/include/hal/ledc_ll.h
+157
View File
@@ -17,6 +17,7 @@
#include "hal/assert.h"
#include "esp_rom_sys.h" //for sync issue workaround
#include "soc/soc_caps.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
@@ -24,14 +25,105 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_DUTY_NUM_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_DUTY_CYCLE_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_SCALE_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS
// Channel tasks: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = LEDC_TASK_DUTY_SCALE_UPDATE_CH0, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = LEDC_TASK_SIG_OUT_DIS_CH0, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = LEDC_TASK_OVF_CNT_RST_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = LEDC_TASK_GAMMA_RESTART_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = LEDC_TASK_GAMMA_PAUSE_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = LEDC_TASK_GAMMA_RESUME_CH0, \
}}[(group)][(task)] + (channel))
#define LEDC_LL_ETM_CHANNEL_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_CHANNEL_TASK_EN_BIT(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = BIT(LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = BIT(LEDC_TASK_SIG_OUT_DIS_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = BIT(LEDC_TASK_OVF_CNT_RST_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = BIT(LEDC_TASK_GAMMA_RESTART_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = BIT(LEDC_TASK_GAMMA_PAUSE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = BIT(LEDC_TASK_GAMMA_RESUME_CH0_EN_S), \
}}[(group)][(task)] << (channel))
// Channel events: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_EVENT_ID(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = LEDC_EVT_DUTY_CHNG_END_CH0, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = LEDC_EVT_OVF_CNT_PLS_CH0, \
}}[(group)][(event)] + (channel))
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_BIT(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = BIT(LEDC_EVT_DUTY_CHNG_END_CH0_EN_S), \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = BIT(LEDC_EVT_OVF_CNT_PLS_CH0_EN_S), \
}}[(group)][(event)] << (channel))
// Timer tasks: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_TASK_ID(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = LEDC_TASK_TIMER0_RST, \
[LEDC_TIMER_ETM_TASK_RESUME] = LEDC_TASK_TIMER0_RESUME, \
[LEDC_TIMER_ETM_TASK_PAUSE] = LEDC_TASK_TIMER0_PAUSE, \
}}[(group)][(task)] + (timer))
#define LEDC_LL_ETM_TIMER_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_TIMER_TASK_EN_BIT(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = BIT(LEDC_TASK_TIMER0_RST_EN_S), \
[LEDC_TIMER_ETM_TASK_RESUME] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
[LEDC_TIMER_ETM_TASK_PAUSE] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
}}[(group)][(task)] << (timer))
// Timer events: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_EVENT_ID(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = LEDC_EVT_TIME_OVF_TIMER0, \
}}[(group)][(event)] + (timer))
#define LEDC_LL_ETM_TIMER_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_TIMER_EVENT_EN_BIT(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = BIT(LEDC_EVT_TIME_OVF_TIMER0_EN_S), \
}}[(group)][(event)] << (timer))
/**
* @brief Enable peripheral register clock
*
@@ -705,6 +797,71 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable ETM event/task
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param reg_addr Register address to control the ETM event/task
* @param bit Bit position in the register
* @param enable Enable or disable the ETM event/task
*
* @return None
*/
static inline void ledc_ll_etm_enable_evt_task(ledc_dev_t *hw, ledc_mode_t speed_mode, volatile uint32_t *reg_addr, uint32_t bit, bool enable)
{
if (enable) {
REG_SET_BIT(reg_addr, bit);
} else {
REG_CLR_BIT(reg_addr, bit);
}
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32h4/include/hal/ledc_ll.h
+157
View File
@@ -16,6 +16,7 @@
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "soc/soc_caps.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
@@ -23,14 +24,105 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_FADE_PARAM_DUTY_NUM_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_FADE_PARAM_DUTY_CYCLE_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_FADE_PARAM_SCALE_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS
// Channel tasks: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = LEDC_TASK_DUTY_SCALE_UPDATE_CH0, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = LEDC_TASK_SIG_OUT_DIS_CH0, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = LEDC_TASK_OVF_CNT_RST_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = LEDC_TASK_FADE_RESTART_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = LEDC_TASK_FADE_PAUSE_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = LEDC_TASK_FADE_RESUME_CH0, \
}}[(group)][(task)] + (channel))
#define LEDC_LL_ETM_CHANNEL_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_CHANNEL_TASK_EN_BIT(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = BIT(LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = BIT(LEDC_TASK_SIG_OUT_DIS_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = BIT(LEDC_TASK_OVF_CNT_RST_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = BIT(LEDC_TASK_FADE_RESTART_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = BIT(LEDC_TASK_FADE_PAUSE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = BIT(LEDC_TASK_FADE_RESUME_CH0_EN_S), \
}}[(group)][(task)] << (channel))
// Channel events: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_EVENT_ID(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = LEDC_EVT_DUTY_CHNG_END_CH0, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = LEDC_EVT_OVF_CNT_PLS_CH0, \
}}[(group)][(event)] + (channel))
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_BIT(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = BIT(LEDC_EVT_DUTY_CHNG_END_CH0_EN_S), \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = BIT(LEDC_EVT_OVF_CNT_PLS_CH0_EN_S), \
}}[(group)][(event)] << (channel))
// Timer tasks: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_TASK_ID(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = LEDC_TASK_TIMER0_RST, \
[LEDC_TIMER_ETM_TASK_RESUME] = LEDC_TASK_TIMER0_RESUME, \
[LEDC_TIMER_ETM_TASK_PAUSE] = LEDC_TASK_TIMER0_PAUSE, \
}}[(group)][(task)] + (timer))
#define LEDC_LL_ETM_TIMER_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_TIMER_TASK_EN_BIT(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = BIT(LEDC_TASK_TIMER0_RST_EN_S), \
[LEDC_TIMER_ETM_TASK_RESUME] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
[LEDC_TIMER_ETM_TASK_PAUSE] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
}}[(group)][(task)] << (timer))
// Timer events: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_EVENT_ID(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = LEDC_EVT_TIME_OVF_TIMER0, \
}}[(group)][(event)] + (timer))
#define LEDC_LL_ETM_TIMER_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_TIMER_EVENT_EN_BIT(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = BIT(LEDC_EVT_TIME_OVF_TIMER0_EN_S), \
}}[(group)][(event)] << (timer))
/**
* @brief Enable peripheral register clock
*
@@ -534,6 +626,71 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable ETM event/task
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param reg_addr Register address to control the ETM event/task
* @param bit Bit position in the register
* @param enable Enable or disable the ETM event/task
*
* @return None
*/
static inline void ledc_ll_etm_enable_evt_task(ledc_dev_t *hw, ledc_mode_t speed_mode, volatile uint32_t *reg_addr, uint32_t bit, bool enable)
{
if (enable) {
REG_SET_BIT(reg_addr, bit);
} else {
REG_CLR_BIT(reg_addr, bit);
}
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-5), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32p4/include/hal/ledc_ll.h
+172 -17
View File
@@ -16,6 +16,7 @@
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/soc_caps.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
@@ -23,14 +24,105 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_RANGE0_SCALE_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS
// Channel tasks: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = LEDC_TASK_DUTY_SCALE_UPDATE_CH0, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = LEDC_TASK_SIG_OUT_DIS_CH0, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = LEDC_TASK_OVF_CNT_RST_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = LEDC_TASK_GAMMA_RESTART_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = LEDC_TASK_GAMMA_PAUSE_CH0, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = LEDC_TASK_GAMMA_RESUME_CH0, \
}}[(group)][(task)] + (channel))
#define LEDC_LL_ETM_CHANNEL_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_CHANNEL_TASK_EN_BIT(group, channel, task) \
((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = BIT(LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = BIT(LEDC_TASK_SIG_OUT_DIS_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = BIT(LEDC_TASK_OVF_CNT_RST_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = BIT(LEDC_TASK_GAMMA_RESTART_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = BIT(LEDC_TASK_GAMMA_PAUSE_CH0_EN_S), \
[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = BIT(LEDC_TASK_GAMMA_RESUME_CH0_EN_S), \
}}[(group)][(task)] << (channel))
// Channel events: ID, enable register and bit
#define LEDC_LL_ETM_CHANNEL_EVENT_ID(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = LEDC_EVT_DUTY_CHNG_END_CH0, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = LEDC_EVT_OVF_CNT_PLS_CH0, \
}}[(group)][(event)] + (channel))
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_CHANNEL_EVENT_EN_BIT(group, channel, event) \
((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
[LEDC_CHANNEL_ETM_EVENT_FADE_END] = BIT(LEDC_EVT_DUTY_CHNG_END_CH0_EN_S), \
[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = BIT(LEDC_EVT_OVF_CNT_PLS_CH0_EN_S), \
}}[(group)][(event)] << (channel))
// Timer tasks: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_TASK_ID(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = LEDC_TASK_TIMER0_RST, \
[LEDC_TIMER_ETM_TASK_RESUME] = LEDC_TASK_TIMER0_RESUME, \
[LEDC_TIMER_ETM_TASK_PAUSE] = LEDC_TASK_TIMER0_PAUSE, \
}}[(group)][(task)] + (timer))
#define LEDC_LL_ETM_TIMER_TASK_EN_REG(group, task) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
[LEDC_TIMER_ETM_TASK_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG, \
}}[(group)][(task)])
#define LEDC_LL_ETM_TIMER_TASK_EN_BIT(group, timer, task) \
((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
[LEDC_TIMER_ETM_TASK_RST] = BIT(LEDC_TASK_TIMER0_RST_EN_S), \
[LEDC_TIMER_ETM_TASK_RESUME] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
[LEDC_TIMER_ETM_TASK_PAUSE] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
}}[(group)][(task)] << (timer))
// Timer events: ID, enable register and bit
#define LEDC_LL_ETM_TIMER_EVENT_ID(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = LEDC_EVT_TIME_OVF_TIMER0, \
}}[(group)][(event)] + (timer))
#define LEDC_LL_ETM_TIMER_EVENT_EN_REG(group, event) \
((volatile uint32_t *[1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG, \
}}[(group)][(event)])
#define LEDC_LL_ETM_TIMER_EVENT_EN_BIT(group, timer, event) \
((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
[LEDC_TIMER_ETM_EVENT_OVF] = BIT(LEDC_EVT_TIME_OVF_TIMER0_EN_S), \
}}[(group)][(event)] << (timer))
/**
* @brief Enable peripheral register clock
*
@@ -336,7 +428,7 @@ static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode,
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
*
* @return None
*/
@@ -350,7 +442,7 @@ static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_m
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param hpoint_val LEDC hpoint value(max: 0xfffff)
*
* @return None
@@ -365,7 +457,7 @@ static inline void ledc_ll_set_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, le
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff)
*
* @return None
@@ -380,7 +472,7 @@ static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, le
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)]
*
* @return None
@@ -395,7 +487,7 @@ static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_m
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param duty_val Pointer to accept the LEDC duty value
*
* @return None
@@ -410,7 +502,7 @@ static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param range Gamma fade range index, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
* @param dir LEDC duty change direction, increase or decrease
* @param cycle The duty cycles
@@ -436,7 +528,7 @@ static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t spee
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param range_num Total number of ranges (1 - SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX) of the fading configured
*
* @return None
@@ -451,7 +543,7 @@ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mo
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param range_num Pointer to accept fade range number
*
* @return None
@@ -466,7 +558,7 @@ static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mo
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param range Gamma fade range index to get, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
* @param dir Pointer to accept fade direction value
* @param cycle Pointer to accept fade cycle value
@@ -492,7 +584,7 @@ static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t spee
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param sig_out_en The output enable status
*
* @return None
@@ -508,7 +600,7 @@ static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
*
* @return None
*/
@@ -522,7 +614,7 @@ static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param idle_level The output idle level
*
* @return None
@@ -538,7 +630,7 @@ static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param fade_end_intr_en The fade end interrupt enable status
*
* @return None
@@ -555,7 +647,7 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param intr_status The fade end interrupt status
*
* @return None
@@ -572,7 +664,7 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
*
* @return None
*/
@@ -587,7 +679,7 @@ static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
*
* @return None
@@ -602,7 +694,7 @@ static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel_num LEDC channel index (0-5), select from ledc_channel_t
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param timer_sel Pointer to accept the LEDC timer index
*
* @return None
@@ -612,6 +704,69 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable ETM event/task
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param reg_addr Register address to control the ETM event/task
* @param bit Bit position in the register
* @param enable Enable or disable the ETM event/task
*/
static inline void ledc_ll_etm_enable_evt_task(ledc_dev_t *hw, ledc_mode_t speed_mode, volatile uint32_t *reg_addr, uint32_t bit, bool enable)
{
if (enable) {
REG_SET_BIT(reg_addr, bit);
} else {
REG_CLR_BIT(reg_addr, bit);
}
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32s2/include/hal/ledc_ll.h
+48
View File
@@ -21,10 +21,13 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_DUTY_NUM_LSCH0_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_DUTY_CYCLE_LSCH0_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_DUTY_SCALE_LSCH0_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_LSCH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
@@ -628,6 +631,51 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_rst = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32s3/include/hal/ledc_ll.h
+48
View File
@@ -21,10 +21,13 @@ extern "C" {
#define LEDC_LL_GET_HW() &LEDC
#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
#define LEDC_LL_DUTY_NUM_MAX (LEDC_DUTY_NUM_LSCH0_V)
#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_DUTY_CYCLE_LSCH0_V)
#define LEDC_LL_DUTY_SCALE_MAX (LEDC_DUTY_SCALE_LSCH0_V)
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V)
#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_LSCH0_V + 1)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
@@ -589,6 +592,51 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
/**
* @brief Enable or disable the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
* @param enable True to enable; false to disable
*
* @return None
*/
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
}
/**
* @brief Set the maximum timer overflow count for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow count
*
* @return None
*/
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
}
/**
* @brief Reset the timer overflow counter for the specified channel
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, low-speed mode only
* @param channel LEDC channel index (0-7), select from ledc_channel_t
*
* @return None
*/
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
{
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_rst = 1;
}
#ifdef __cplusplus
}
#endif
components/hal/include/hal/ledc_hal.h
+14 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -248,6 +248,19 @@ typedef struct {
*/
void ledc_hal_init(ledc_hal_context_t *hal, ledc_mode_t speed_mode);
#if LEDC_LL_CHANNEL_SUPPORT_OVF_CNT
/**
* @brief Configure the maximum timer overflow times for the LEDC channel
*
* @param hal Context of the HAL layer
* @param channel LEDC channel index, select from ledc_channel_t
* @param max_ovf_cnt The maximum timer overflow times. To disable the timer overflow count, set this parameter to 0.
*
* @return None
*/
void ledc_hal_channel_configure_maximum_timer_ovf_cnt(ledc_hal_context_t *hal, ledc_channel_t channel, uint32_t max_ovf_cnt);
#endif
/**
* @brief Update channel configure when select low speed mode
*
components/hal/include/hal/ledc_types.h
+51 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -139,6 +139,56 @@ typedef enum {
LEDC_FADE_MAX,
} ledc_fade_mode_t;
#if SOC_LEDC_SUPPORT_ETM
/**
* @brief LEDC channel related specific tasks that supported by the ETM module
*/
typedef enum {
LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE, /*!< Update newly configured scale for the fade on the channel */
LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS, /*!< Disable signal output on the channel */
LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST, /*!< Reset channel's timer overflow counter */
LEDC_CHANNEL_ETM_TASK_FADE_RESTART, /* Restart the last fade on the channel, the replay will start from last configured duty
(note that, for a single fade, the duty may be configured to a new value in ISR,
so it may not be the initial value you configured before fade) */
LEDC_CHANNEL_ETM_TASK_FADE_PAUSE, /*!< Pause fading on the channel */
LEDC_CHANNEL_ETM_TASK_FADE_RESUME, /*!< Resume fading on the channel */
LEDC_CHANNEL_ETM_TASK_MAX,
} ledc_channel_etm_task_type_t;
/**
* @brief LEDC timer related specific tasks that supported by the ETM module
*/
typedef enum {
LEDC_TIMER_ETM_TASK_RST, /*!< Reset the timer
When timer is reset, a timer overflow equivalent signal is sent to the channel, so any newly configured parameter is able to get updated
This is not the case on C6/H2/P4/C5/H4/H21, on such targets, no timer overflow equivalent signal is sent to the channel, i.e. newly configured parameter is not able to get updated when this ETM task is triggered */
LEDC_TIMER_ETM_TASK_RESUME, /*!< Resume the timer
Note that the ETM timer pause/resume task must be used in pair
Pause by ETM task and resume by calling `ledc_timer_resume` is not allowed, vice versa */
LEDC_TIMER_ETM_TASK_PAUSE, /*!< Pause the timer */
LEDC_TIMER_ETM_TASK_MAX,
} ledc_timer_etm_task_type_t;
/**
* @brief LEDC channel related specific events that supported by the ETM module
*/
typedef enum {
LEDC_CHANNEL_ETM_EVENT_FADE_END, /*!< Channel fading ended */
LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT, /*!< Channel has reached the maximum timer overflow count
The maximum overflow count value can be set with `ledc_channel_configure_maximum_timer_ovf_cnt` */
LEDC_CHANNEL_ETM_EVENT_MAX,
} ledc_channel_etm_event_type_t;
/**
* @brief LEDC timer related specific events that supported by the ETM module
*/
typedef enum {
LEDC_TIMER_ETM_EVENT_OVF, /*!< Timer overflow happened */
LEDC_TIMER_ETM_EVENT_MAX,
} ledc_timer_etm_event_type_t;
#endif
#ifdef __cplusplus
}
#endif
components/hal/ledc_hal.c
+14 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -63,3 +63,16 @@ void ledc_hal_get_fade_param(ledc_hal_context_t *hal, ledc_channel_t channel_num
ledc_ll_get_fade_param_range(hal->dev, hal->speed_mode, channel_num, range, dir, cycle, scale, step);
}
#endif
#if LEDC_LL_CHANNEL_SUPPORT_OVF_CNT
void ledc_hal_channel_configure_maximum_timer_ovf_cnt(ledc_hal_context_t *hal, ledc_channel_t channel, uint32_t max_ovf_cnt)
{
if (max_ovf_cnt == 0) {
ledc_ll_channel_enable_timer_ovt_cnt(hal->dev, hal->speed_mode, channel, false);
} else {
ledc_ll_channel_enable_timer_ovt_cnt(hal->dev, hal->speed_mode, channel, true);
ledc_ll_channel_set_maximum_timer_ovf_cnt(hal->dev, hal->speed_mode, channel, max_ovf_cnt);
ledc_ll_channel_reset_timer_ovf_cnt(hal->dev, hal->speed_mode, channel);
}
}
#endif