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fix(rtcio): RTC GPIO configuration should be written if LP IO clock exists

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This commit is contained in:
Song Ruo Jing
2026-03-13 11:22:37 +08:00
parent 9df5d023bc
commit 68ed9e912b
32 changed files with 248 additions and 156 deletions
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components/soc/esp32c2/register/soc/io_mux_reg.h
-2
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@@ -122,8 +122,6 @@
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 5
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32c3/register/soc/io_mux_reg.h
-2
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@@ -133,8 +133,6 @@
#define USB_INT_PHY0_DM_GPIO_NUM 18
#define USB_INT_PHY0_DP_GPIO_NUM 19
#define MAX_RTC_GPIO_NUM 5
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
components/soc/esp32c5/register/soc/io_mux_reg.h
-2
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@@ -133,8 +133,6 @@ extern "C" {
#define USB_INT_PHY0_DM_GPIO_NUM 13
#define USB_INT_PHY0_DP_GPIO_NUM 14
#define MAX_RTC_GPIO_NUM 6
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32c6/register/soc/io_mux_reg.h
-2
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@@ -139,8 +139,6 @@
#define USB_INT_PHY0_DM_GPIO_NUM 12
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 7
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32c61/register/soc/io_mux_reg.h
-2
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@@ -109,8 +109,6 @@ extern "C" {
#define USB_INT_PHY0_DM_GPIO_NUM 12
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 6
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32h2/register/soc/io_mux_reg.h
-2
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@@ -151,8 +151,6 @@
#define USB_INT_PHY0_DM_GPIO_NUM 26
#define USB_INT_PHY0_DP_GPIO_NUM 27
#define MAX_RTC_GPIO_NUM 14 // GPIO7~14 are the pads with LP function
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32h21/register/soc/io_mux_reg.h
-2
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@@ -144,8 +144,6 @@ extern "C" {
#define USB_INT_PHY0_DM_GPIO_NUM 17
#define USB_INT_PHY0_DP_GPIO_NUM 18
#define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32h4/register/soc/io_mux_reg.h
-2
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@@ -137,8 +137,6 @@ extern "C" {
#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 5
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32p4/register/hw_ver1/soc/io_mux_reg.h
-2
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@@ -175,8 +175,6 @@
#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 15
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
-2
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@@ -175,8 +175,6 @@
#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 15
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32s2/register/soc/io_mux_reg.h
-2
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@@ -143,8 +143,6 @@
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 21
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
components/soc/esp32s3/register/soc/io_mux_reg.h
-4
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@@ -151,10 +151,6 @@
#define SD_DATA3_GPIO_NUM 10
#define USB_INT_PHY0_DM_GPIO_NUM 19
#define USB_INT_PHY0_DP_GPIO_NUM 20
#define XTAL32K_P_GPIO_NUM 15
#define XTAL32K_N_GPIO_NUM 16
#define MAX_RTC_GPIO_NUM 21
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE