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fix(esp_system): fix rom secure boot fast wake feature for c5/c6/h2/h21

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This commit is contained in:
wuzhenghui
2026-01-12 18:11:59 +08:00
parent bb1bf75a83
commit 67a62f45ce
15 changed files with 97 additions and 10 deletions
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components/heap/port/esp32c5/memory_layout.c
+15 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,7 @@
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
#include "esp_rom_caps.h"
#if CONFIG_SECURE_ENABLE_TEE
#define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW)
@@ -73,6 +74,18 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH)
#endif
const soc_memory_region_t soc_memory_regions[] = {
#if CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW), SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
@@ -80,7 +93,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ SOC_DIRAM_DRAM_LOW, (APP_USABLE_DRAM_END - SOC_DIRAM_DRAM_LOW), SOC_MEMORY_TYPE_RAM, SOC_DIRAM_IRAM_LOW, false}, //D/IRAM, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ SOC_RTC_DATA_LOW, (SOC_RTC_DATA_HIGH - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
{ SOC_RTC_DATA_LOW, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
#endif
};
components/heap/port/esp32c6/memory_layout.c
+14 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,7 @@
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
#include "esp_rom_caps.h"
#if CONFIG_SECURE_ENABLE_TEE
#define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW)
@@ -71,6 +72,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH)
#endif
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory
@@ -78,7 +90,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_RAM, 0x40860000, false}, //D/IRAM level3, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
{ 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
#endif
};
components/heap/port/esp32h2/memory_layout.c
+14 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,7 @@
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
#include "esp_rom_caps.h"
#if CONFIG_SECURE_ENABLE_TEE
#define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW)
@@ -69,6 +70,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH)
#endif
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level 0
{ 0x40810000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40810000, false}, //D/IRAM level 1
@@ -77,7 +89,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level 4
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level 4
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
{ 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
#endif
};
components/heap/port/esp32h21/memory_layout.c
+14 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,7 +11,7 @@
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
#include "esp_rom_caps.h"
/**
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
@@ -65,6 +65,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH)
#endif
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level 0
{ 0x40810000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40810000, false}, //D/IRAM level 1
@@ -73,7 +84,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level 4
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level 4
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
{ 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
#endif
};