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fix(lp_io): w1ts/w1tc register access performance is improved

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by avoiding "read-modify-write" operation. The registers designed to be
write only.
This commit is contained in:
Song Ruo Jing
2025-08-13 21:24:19 +08:00
parent 130b83fee7
commit 67a2dfa293
7 changed files with 32 additions and 32 deletions
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components/hal/esp32c5/include/hal/rtc_io_ll.h
+5 -5
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@@ -115,7 +115,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/
static inline void rtcio_ll_output_enable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, out_enable_w1ts, BIT(rtcio_num));
LP_GPIO.enable_w1ts.val = BIT(rtcio_num);
}
/**
@@ -125,7 +125,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/
static inline void rtcio_ll_output_disable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, out_enable_w1tc, BIT(rtcio_num));
LP_GPIO.enable_w1tc.val = BIT(rtcio_num);
}
/**
@@ -137,9 +137,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{
if (level) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_data_w1ts, BIT(rtcio_num));
LP_GPIO.out_w1ts.val = BIT(rtcio_num);
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_data_w1tc, BIT(rtcio_num));
LP_GPIO.out_w1tc.val = BIT(rtcio_num);
}
}
@@ -450,7 +450,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/
static inline void rtcio_ll_clear_interrupt_status(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_intr_w1tc, 0xff);
LP_GPIO.status_w1tc.val = 0xFF;
}
#ifdef __cplusplus