mirror of
https://github.com/espressif/esp-idf.git
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feat(ppa): ESP32P4 ECO5 PPA related updates
PPA SRM engine added YUV422 and GRAY8 color mode support PPA SRM engine macro block size increased to 32x32 PPA Blending engine added YUV420, YUV422 and GRAY8 color mode support
This commit is contained in:
Song Ruo Jing
File diff suppressed because it is too large
Load Diff
@@ -43,10 +43,9 @@ extern "C" {
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#define PPA_CLUT_CONF_REG (DR_REG_PPA_BASE + 0xc)
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/** PPA_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0;
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* 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register
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* PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
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* memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
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* should be 01 to access sr clut and should be 10 to access blend0 clut and should be
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* 11 to access blend 1 clut in memory mode.
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* PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
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* memory mode to wr/rd blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
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* should be 01 to access blend0 clut and should be 10 to access blend1 clut in memory mode.
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*/
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#define PPA_APB_FIFO_MASK (BIT(0))
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#define PPA_APB_FIFO_MASK_M (PPA_APB_FIFO_MASK_V << PPA_APB_FIFO_MASK_S)
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@@ -225,7 +224,7 @@ extern "C" {
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#define PPA_BLEND_EOF_INT_CLR_V 0x00000001U
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#define PPA_BLEND_EOF_INT_CLR_S 1
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/** PPA_SR_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
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* Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
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* Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt.
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*/
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#define PPA_SR_PARAM_CFG_ERR_INT_CLR (BIT(2))
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#define PPA_SR_PARAM_CFG_ERR_INT_CLR_M (PPA_SR_PARAM_CFG_ERR_INT_CLR_V << PPA_SR_PARAM_CFG_ERR_INT_CLR_S)
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@@ -273,20 +272,20 @@ extern "C" {
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#define PPA_YUV_TX_RANGE_M (PPA_YUV_TX_RANGE_V << PPA_YUV_TX_RANGE_S)
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#define PPA_YUV_TX_RANGE_V 0x00000001U
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#define PPA_YUV_TX_RANGE_S 9
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/** PPA_YUV2RGB_PROTOCAL : R/W; bitpos: [10]; default: 0;
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/** PPA_YUV2RGB_PROTOCOL : R/W; bitpos: [10]; default: 0;
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* YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
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*/
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#define PPA_YUV2RGB_PROTOCAL (BIT(10))
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#define PPA_YUV2RGB_PROTOCAL_M (PPA_YUV2RGB_PROTOCAL_V << PPA_YUV2RGB_PROTOCAL_S)
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#define PPA_YUV2RGB_PROTOCAL_V 0x00000001U
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#define PPA_YUV2RGB_PROTOCAL_S 10
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/** PPA_RGB2YUV_PROTOCAL : R/W; bitpos: [11]; default: 0;
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#define PPA_YUV2RGB_PROTOCOL (BIT(10))
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#define PPA_YUV2RGB_PROTOCOL_M (PPA_YUV2RGB_PROTOCOL_V << PPA_YUV2RGB_PROTOCOL_S)
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#define PPA_YUV2RGB_PROTOCOL_V 0x00000001U
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#define PPA_YUV2RGB_PROTOCOL_S 10
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/** PPA_RGB2YUV_PROTOCOL : R/W; bitpos: [11]; default: 0;
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* RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
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*/
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#define PPA_RGB2YUV_PROTOCAL (BIT(11))
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#define PPA_RGB2YUV_PROTOCAL_M (PPA_RGB2YUV_PROTOCAL_V << PPA_RGB2YUV_PROTOCAL_S)
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#define PPA_RGB2YUV_PROTOCAL_V 0x00000001U
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#define PPA_RGB2YUV_PROTOCAL_S 11
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#define PPA_RGB2YUV_PROTOCOL (BIT(11))
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#define PPA_RGB2YUV_PROTOCOL_M (PPA_RGB2YUV_PROTOCOL_V << PPA_RGB2YUV_PROTOCOL_S)
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#define PPA_RGB2YUV_PROTOCOL_V 0x00000001U
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#define PPA_RGB2YUV_PROTOCOL_S 11
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/** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0;
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* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
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*/
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@@ -337,20 +336,20 @@ extern "C" {
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#define PPA_BLEND_TX_YUV_RANGE_M (PPA_BLEND_TX_YUV_RANGE_V << PPA_BLEND_TX_YUV_RANGE_S)
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#define PPA_BLEND_TX_YUV_RANGE_V 0x00000001U
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#define PPA_BLEND_TX_YUV_RANGE_S 13
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/** PPA_BLEND0_RX_YUV2RGB_PROTOCAL : R/W; bitpos: [14]; default: 0;
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/** PPA_BLEND0_RX_YUV2RGB_PROTOCOL : R/W; bitpos: [14]; default: 0;
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* YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709
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*/
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#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL (BIT(14))
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#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S)
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#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V 0x00000001U
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#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S 14
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/** PPA_BLEND_TX_RGB2YUV_PROTOCAL : R/W; bitpos: [15]; default: 0;
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#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL (BIT(14))
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#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S)
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#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V 0x00000001U
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#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S 14
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/** PPA_BLEND_TX_RGB2YUV_PROTOCOL : R/W; bitpos: [15]; default: 0;
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* RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709
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*/
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#define PPA_BLEND_TX_RGB2YUV_PROTOCAL (BIT(15))
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#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_M (PPA_BLEND_TX_RGB2YUV_PROTOCAL_V << PPA_BLEND_TX_RGB2YUV_PROTOCAL_S)
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#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_V 0x00000001U
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#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_S 15
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#define PPA_BLEND_TX_RGB2YUV_PROTOCOL (BIT(15))
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#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_M (PPA_BLEND_TX_RGB2YUV_PROTOCOL_V << PPA_BLEND_TX_RGB2YUV_PROTOCOL_S)
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#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_V 0x00000001U
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#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_S 15
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/** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0;
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* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
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*/
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@@ -554,7 +553,7 @@ extern "C" {
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#define PPA_BLEND1_RX_FIX_ALPHA_S 8
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/** PPA_BLEND0_RX_ALPHA_MOD : R/W; bitpos: [17:16]; default: 0;
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* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2:
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* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
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* Original alpha multiply with PPA_SR_BLEND0_ALPHA/256.
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*/
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#define PPA_BLEND0_RX_ALPHA_MOD 0x00000003U
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#define PPA_BLEND0_RX_ALPHA_MOD_M (PPA_BLEND0_RX_ALPHA_MOD_V << PPA_BLEND0_RX_ALPHA_MOD_S)
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@@ -562,7 +561,7 @@ extern "C" {
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#define PPA_BLEND0_RX_ALPHA_MOD_S 16
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/** PPA_BLEND1_RX_ALPHA_MOD : R/W; bitpos: [19:18]; default: 0;
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* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2:
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* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
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* Original alpha multiply with PPA_SR_BLEND1_ALPHA/256.
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*/
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#define PPA_BLEND1_RX_ALPHA_MOD 0x00000003U
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#define PPA_BLEND1_RX_ALPHA_MOD_M (PPA_BLEND1_RX_ALPHA_MOD_V << PPA_BLEND1_RX_ALPHA_MOD_S)
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@@ -91,12 +91,12 @@ typedef union {
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struct {
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/** sr_rx_cm : R/W; bitpos: [3:0]; default: 0;
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* The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1:
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* RGB888. 2: RGB565. 8: YUV420. others: Reserved.
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* RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved.
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*/
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uint32_t sr_rx_cm:4;
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/** sr_tx_cm : R/W; bitpos: [7:4]; default: 0;
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* The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888.
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* 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved.
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* 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved.
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*/
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uint32_t sr_tx_cm:4;
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/** yuv_rx_range : R/W; bitpos: [8]; default: 0;
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@@ -115,7 +115,11 @@ typedef union {
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* RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
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*/
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uint32_t rgb2yuv_protocol:1;
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uint32_t reserved_12:20;
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/** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0;
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* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
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*/
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uint32_t yuv422_rx_byte_order:2;
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uint32_t reserved_14:18;
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};
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uint32_t val;
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} ppa_sr_color_mode_reg_t;
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@@ -127,7 +131,7 @@ typedef union {
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struct {
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/** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0;
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* The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2:
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* RGB565. 3: Reserved. 4: L8. 5: L4.
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* RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY
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*/
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uint32_t blend0_rx_cm:4;
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/** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0;
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@@ -137,10 +141,30 @@ typedef union {
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uint32_t blend1_rx_cm:4;
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/** blend_tx_cm : R/W; bitpos: [11:8]; default: 0;
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* The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2:
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* RGB565. 3: Reserved..
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* RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY
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*/
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uint32_t blend_tx_cm:4;
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uint32_t reserved_12:20;
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/** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0;
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* YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range
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*/
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uint32_t blend0_rx_yuv_range:1;
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/** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0;
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* YUV output range when blend tx cm is yuv. 0: limit range. 1: full range
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*/
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uint32_t blend_tx_yuv_range:1;
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/** blend0_rx_yuv2rgb_protocol : R/W; bitpos: [14]; default: 0;
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* YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709
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*/
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uint32_t blend0_rx_yuv2rgb_protocol:1;
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/** blend_tx_rgb2yuv_protocol : R/W; bitpos: [15]; default: 0;
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* RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709
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*/
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uint32_t blend_tx_rgb2yuv_protocol:1;
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/** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0;
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* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
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*/
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uint32_t blend0_rx_yuv422_byte_order:2;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} ppa_blend_color_mode_reg_t;
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@@ -165,7 +189,11 @@ typedef union {
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* to improve efficient accessing external memory.
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*/
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uint32_t sr_macro_bk_ro_bypass:1;
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uint32_t reserved_3:29;
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/** sr_bk_size_sel : R/W; bitpos: [3]; default: 0;
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* sel srm pix_blk size, 0:32x32, 1:16x16
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*/
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uint32_t sr_bk_size_sel:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} ppa_sr_byte_order_reg_t;
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@@ -227,7 +255,12 @@ typedef union {
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* write 1 then write 0 to reset blending engine.
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*/
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uint32_t blend_rst:1;
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uint32_t reserved_5:27;
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/** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0;
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* unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and
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* ls_enc
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*/
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uint32_t blend_tx_inf_sel:2;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} ppa_blend_trans_mode_reg_t;
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@@ -263,13 +296,13 @@ typedef union {
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typedef union {
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struct {
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/** blend_hb : R/W; bitpos: [13:0]; default: 0;
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* The horizontal width of image block that would be filled in fix pixel filling mode.
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* The unit is pixel
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* The horizontal width of image block that would be filled in fix pixel filling mode
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* or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420
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*/
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uint32_t blend_hb:14;
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/** blend_vb : R/W; bitpos: [27:14]; default: 0;
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* The vertical width of image block that would be filled in fix pixel filling mode.
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* The unit is pixel
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* The vertical width of image block that would be filled in fix pixel filling mode or
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* blend mode. The unit is pixel. Must be even num when YUV420
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*/
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uint32_t blend_vb:14;
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uint32_t reserved_28:4;
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@@ -293,13 +326,13 @@ typedef union {
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*/
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uint32_t blend1_rx_fix_alpha:8;
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/** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0;
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* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
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* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
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* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2:
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* Original alpha multiply with PPA_BLEND0_FIX_ALPHA/256.
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*/
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uint32_t blend0_rx_alpha_mod:2;
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/** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0;
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* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
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* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
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* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2:
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* Original alpha multiply with PPA_BLEND1_FIX_ALPHA/256.
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*/
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uint32_t blend1_rx_alpha_mod:2;
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/** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0;
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@@ -612,7 +645,12 @@ typedef union {
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* PPA_SR_PARAM_ERR_ST_REG.
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*/
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uint32_t sr_param_cfg_err_int_raw:1;
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uint32_t reserved_3:29;
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/** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
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* The raw interrupt bit turns to high level when the configured blending coefficient
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* is wrong. User can check the reasons through register PPA_BLEND_ST_REG.
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*/
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uint32_t blend_param_cfg_err_int_raw:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} ppa_int_raw_reg_t;
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@@ -631,10 +669,14 @@ typedef union {
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*/
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uint32_t blend_eof_int_st:1;
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/** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0;
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* The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
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* The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt.
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*/
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uint32_t sr_param_cfg_err_int_st:1;
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uint32_t reserved_3:29;
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/** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0;
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* The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
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*/
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uint32_t blend_param_cfg_err_int_st:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} ppa_int_st_reg_t;
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@@ -653,10 +695,14 @@ typedef union {
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*/
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uint32_t blend_eof_int_ena:1;
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/** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0;
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* The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
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* The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt.
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*/
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uint32_t sr_param_cfg_err_int_ena:1;
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uint32_t reserved_3:29;
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/** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0;
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* The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
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*/
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uint32_t blend_param_cfg_err_int_ena:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} ppa_int_ena_reg_t;
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@@ -675,10 +721,14 @@ typedef union {
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*/
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uint32_t blend_eof_int_clr:1;
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/** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0;
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* Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
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* Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt.
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*/
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uint32_t sr_param_cfg_err_int_clr:1;
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uint32_t reserved_3:29;
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/** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0;
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* Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
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*/
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uint32_t blend_param_cfg_err_int_clr:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
|
||||
} ppa_int_clr_reg_t;
|
||||
@@ -712,7 +762,15 @@ typedef union {
|
||||
* 1: indicate the size of two image is different.
|
||||
*/
|
||||
uint32_t blend_size_diff_st:1;
|
||||
uint32_t reserved_1:31;
|
||||
/** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0;
|
||||
* Represents that x param is an odd num when enable yuv422 or yuv420
|
||||
*/
|
||||
uint32_t blend_yuv_x_scale_err_st:1;
|
||||
/** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0;
|
||||
* Represents that y param is an odd num when enable yuv420
|
||||
*/
|
||||
uint32_t blend_yuv_y_scale_err_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ppa_blend_st_reg_t;
|
||||
@@ -773,7 +831,7 @@ typedef union {
|
||||
uint32_t xdst_len_too_large_err_st:1;
|
||||
/** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0;
|
||||
* The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
|
||||
* yuv420 rx
|
||||
* yuv422 or yuv420 rx
|
||||
*/
|
||||
uint32_t x_yuv420_rx_scale_err_st:1;
|
||||
/** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0;
|
||||
@@ -783,7 +841,7 @@ typedef union {
|
||||
uint32_t y_yuv420_rx_scale_err_st:1;
|
||||
/** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0;
|
||||
* The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
|
||||
* yuv420 tx
|
||||
* yuv422 or yuv420 tx
|
||||
*/
|
||||
uint32_t x_yuv420_tx_scale_err_st:1;
|
||||
/** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0;
|
||||
@@ -841,13 +899,68 @@ typedef union {
|
||||
} ppa_eco_cell_ctrl_reg_t;
|
||||
|
||||
|
||||
/** Group: Debug Register */
|
||||
/** Type of debug_ctrl0 register
|
||||
* debug register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx
|
||||
* bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6:
|
||||
* blend output
|
||||
*/
|
||||
uint32_t dbg_replace_sel:3;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ppa_debug_ctrl0_reg_t;
|
||||
|
||||
/** Type of debug_ctrl1 register
|
||||
* debug register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dbg_replace_data : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the replace data
|
||||
*/
|
||||
uint32_t dbg_replace_data:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} ppa_debug_ctrl1_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration Register */
|
||||
/** Type of rgb2gray register
|
||||
* rgb2gray register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rgb2gray_b : R/W; bitpos: [7:0]; default: 85;
|
||||
* Configures the b parameter for rgb2gray
|
||||
*/
|
||||
uint32_t rgb2gray_b:8;
|
||||
/** rgb2gray_g : R/W; bitpos: [15:8]; default: 86;
|
||||
* Configures the g parameter for rgb2gray
|
||||
*/
|
||||
uint32_t rgb2gray_g:8;
|
||||
/** rgb2gray_r : R/W; bitpos: [23:16]; default: 85;
|
||||
* Configures the r parameter for rgb2gray
|
||||
*/
|
||||
uint32_t rgb2gray_r:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} ppa_rgb2gray_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of date register
|
||||
* PPA Version register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 36716609;
|
||||
/** date : R/W; bitpos: [31:0]; default: 539234848;
|
||||
* register version.
|
||||
*/
|
||||
uint32_t date:32;
|
||||
@@ -893,7 +1006,10 @@ typedef struct ppa_dev_t {
|
||||
volatile ppa_eco_high_reg_t eco_high;
|
||||
volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl;
|
||||
volatile ppa_sram_ctrl_reg_t sram_ctrl;
|
||||
uint32_t reserved_090[28];
|
||||
volatile ppa_debug_ctrl0_reg_t debug_ctrl0;
|
||||
volatile ppa_debug_ctrl1_reg_t debug_ctrl1;
|
||||
volatile ppa_rgb2gray_reg_t rgb2gray;
|
||||
uint32_t reserved_09c[25];
|
||||
volatile ppa_date_reg_t date;
|
||||
} ppa_dev_t;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user