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Merge branch 'feat/i2s_edma' into 'master'

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feat(i2s): supports DMA buffer in PSRAM

Closes IDF-15256, IDF-11059, and IDF-4471

See merge request espressif/esp-idf!51877
This commit is contained in:
morris
2026-09-03 16:14:03 +08:00
parent 7f1b8d002e bea9fd822c
commit 66d1b5f641
33 changed files with 757 additions and 162 deletions
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2
components/esp_driver_dma/include/esp_private/gdma.h
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@@ -202,7 +202,7 @@ esp_err_t gdma_disconnect(gdma_channel_handle_t dma_chan);
typedef struct {
uint32_t max_data_burst_size; /*!< Set the max burst size when DMA read/write the data buffer.
Set to 0 means to disable the data burst.
Other value must be power of 2, e.g., 4/8/16/32/64 */
Other values must be powers of 2 or supported by the selected GDMA bus. */
bool access_ext_mem; /*!< Set this if the DMA transfer will access external memory */
} gdma_transfer_config_t;

10
components/esp_driver_dma/src/gdma.c
View File

@@ -421,6 +421,9 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
return ESP_ERR_INVALID_ARG;
}
gdma_pair_t *pair = dma_chan->pair;
gdma_group_t *group = pair->group;
gdma_hal_context_t *hal = &group->hal;
uint32_t max_data_burst_size = config->max_data_burst_size;
size_t int_mem_alignment = 1;
size_t ext_enc_mem_alignment = 1;
@@ -443,8 +446,7 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
#endif
}
if (max_data_burst_size) {
// burst size must be power of 2
ESP_RETURN_ON_FALSE((max_data_burst_size & (max_data_burst_size - 1)) == 0, ESP_ERR_INVALID_ARG,
ESP_RETURN_ON_FALSE(gdma_hal_check_burst_size(hal, max_data_burst_size), ESP_ERR_INVALID_ARG,
TAG, "invalid max_data_burst_size: %"PRIu32, max_data_burst_size);
}
@@ -477,10 +479,6 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
ext_no_enc_mem_alignment = BIT(31);
}
gdma_pair_t *pair = dma_chan->pair;
gdma_group_t *group = pair->group;
gdma_hal_context_t *hal = &group->hal;
// always enable descriptor burst as the descriptor is always word aligned and is in the internal SRAM
bool en_desc_burst = true;
gdma_hal_enable_burst(hal, pair->pair_id, dma_chan->direction, en_data_burst, en_desc_burst);

77
components/esp_driver_dma/test_apps/dma/main/test_gdma.c
View File

@@ -921,3 +921,80 @@ TEST_CASE("GDMA interrupt priority configuration", "[GDMA]")
TEST_ESP_OK(gdma_del_channel(tx_chan));
TEST_ESP_OK(gdma_del_channel(rx_chan));
}
#if SOC_HAS(AHB_GDMA) || SOC_HAS(LP_AHB_GDMA) || SOC_HAS(AXI_GDMA)
typedef esp_err_t (*gdma_new_channel_func_t)(const gdma_channel_alloc_config_t *config,
gdma_channel_handle_t *ret_tx_chan,
gdma_channel_handle_t *ret_rx_chan);
static void test_gdma_burst_size_validation(gdma_new_channel_func_t new_channel,
size_t unsupported_burst_size,
size_t invalid_psram_burst_size)
{
gdma_channel_handle_t tx_chan = NULL;
gdma_channel_alloc_config_t channel_config = {};
TEST_ESP_OK(new_channel(&channel_config, &tx_chan, NULL));
gdma_transfer_config_t transfer_config = {
.max_data_burst_size = 16,
.access_ext_mem = false,
};
TEST_ESP_OK(gdma_config_transfer(tx_chan, &transfer_config));
transfer_config.max_data_burst_size = 3;
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, gdma_config_transfer(tx_chan, &transfer_config));
if (unsupported_burst_size) {
transfer_config.max_data_burst_size = unsupported_burst_size;
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, gdma_config_transfer(tx_chan, &transfer_config));
}
if (invalid_psram_burst_size) {
transfer_config.access_ext_mem = true;
transfer_config.max_data_burst_size = invalid_psram_burst_size;
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, gdma_config_transfer(tx_chan, &transfer_config));
}
TEST_ESP_OK(gdma_del_channel(tx_chan));
}
#endif // SOC_HAS(AHB_GDMA) || SOC_HAS(LP_AHB_GDMA) || SOC_HAS(AXI_GDMA)
#if SOC_HAS(AHB_GDMA) || SOC_HAS(LP_AHB_GDMA)
TEST_CASE("GDMA rejects invalid AHB burst sizes", "[GDMA]")
{
#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
const size_t unsupported_burst_size = 8;
#else
const size_t unsupported_burst_size = 0;
#endif
#if SOC_HAS(AHB_GDMA)
#if GDMA_LL_GET(AHB_PSRAM_CAPABLE)
test_gdma_burst_size_validation(gdma_new_ahb_channel, unsupported_burst_size,
GDMA_LL_MAX_BURST_SIZE_PSRAM * 2);
#else
test_gdma_burst_size_validation(gdma_new_ahb_channel, unsupported_burst_size, 0);
#endif
#endif // SOC_HAS(AHB_GDMA)
#if SOC_HAS(LP_AHB_GDMA)
#if GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE)
test_gdma_burst_size_validation(gdma_new_lp_ahb_channel, unsupported_burst_size,
GDMA_LL_MAX_BURST_SIZE_PSRAM * 2);
#else
test_gdma_burst_size_validation(gdma_new_lp_ahb_channel, unsupported_burst_size, 0);
#endif
#endif // SOC_HAS(LP_AHB_GDMA)
}
#endif // SOC_HAS(AHB_GDMA) || SOC_HAS(LP_AHB_GDMA)
#if SOC_HAS(AXI_GDMA)
TEST_CASE("GDMA rejects invalid AXI burst sizes", "[GDMA]")
{
#if GDMA_LL_GET(AXI_PSRAM_CAPABLE)
test_gdma_burst_size_validation(gdma_new_axi_channel, 4, GDMA_LL_MAX_BURST_SIZE_PSRAM * 2);
#else
test_gdma_burst_size_validation(gdma_new_axi_channel, 4, 0);
#endif // GDMA_LL_GET(AXI_PSRAM_CAPABLE)
}
#endif // SOC_HAS(AXI_GDMA)