From 669be4a6647de0d9999ccaa1e9b4c672408dfcbc Mon Sep 17 00:00:00 2001 From: armando Date: Wed, 6 May 2026 10:43:35 +0800 Subject: [PATCH] fix(psram): enable psram power xpd --- .../esp32s31/include/hal/psram_ctrlr_ll.h | 16 ++++++++++++++++ .../esp_psram/device/esp_psram_impl_ap_oct.c | 2 ++ 2 files changed, 18 insertions(+) diff --git a/components/esp_hal_mspi/esp32s31/include/hal/psram_ctrlr_ll.h b/components/esp_hal_mspi/esp32s31/include/hal/psram_ctrlr_ll.h index bfeff96fdce..c963e228bbd 100644 --- a/components/esp_hal_mspi/esp32s31/include/hal/psram_ctrlr_ll.h +++ b/components/esp_hal_mspi/esp32s31/include/hal/psram_ctrlr_ll.h @@ -18,6 +18,7 @@ #include "hal/assert.h" #include "hal/misc.h" #include "hal/config.h" +#include "soc/pmu_reg.h" #include "soc/spi_mem_s_struct.h" #include "soc/spi_mem_s_reg.h" #include "soc/spi1_mem_s_reg.h" @@ -61,6 +62,21 @@ extern "C" { #define PSRAM_CTRLR_LL_INTR_EVENT_SUPPORTED 1 #define PSRAM_CTRLR_LL_DEDICATED_LDO 1 +/** + * @brief Enable PSRAM power + * + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_power(bool en) +{ + if (en) { + REG_SET_BIT(PMU_PSRAM_CFG_REG, PMU_PSRAM_XPD); + } else { + REG_CLR_BIT(PMU_PSRAM_CFG_REG, PMU_PSRAM_XPD); + } +} + /** * @brief Set PSRAM write cmd * diff --git a/components/esp_psram/device/esp_psram_impl_ap_oct.c b/components/esp_psram/device/esp_psram_impl_ap_oct.c index 90721a66bdb..8d70ece8676 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_oct.c +++ b/components/esp_psram/device/esp_psram_impl_ap_oct.c @@ -413,6 +413,8 @@ static void s_configure_psram_ecc(void) esp_err_t esp_psram_impl_enable(void) { + psram_ctrlr_ll_enable_power(true); + #if PSRAM_CTRLR_LL_DEDICATED_LDO esp_psram_power_cfg_t config = { .voltage_mv = CONFIG_SPIRAM_LDO_VOLTAGE_DOMAIN,