From 647dea9395a80c0c63d9bea99fc9c871c52fe38c Mon Sep 17 00:00:00 2001
From: "Michael (XIAO Xufeng)" <xiaoxufeng@espressif.com>
Date: Thu, 10 Sep 2020 10:37:58 +0800
Subject: [PATCH] soc: combine xxx_caps.h into one soc_caps.h

During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
---
 .../src/bootloader_flash_config_esp32.c       |   3 +-
 .../src/bootloader_flash_config_esp32s2.c     |   2 +-
 .../src/bootloader_flash_config_esp32s3.c     |   2 +-
 .../bootloader_support/src/bootloader_mem.c   |   4 +-
 components/driver/adc_common.c                |   1 +
 components/driver/esp32/touch_sensor.c        |  12 +-
 components/driver/esp32s2/touch_sensor.c      |   3 +-
 components/driver/gpio.c                      |  33 ++-
 components/driver/i2c.c                       |  26 +-
 components/driver/i2s.c                       |  35 +--
 components/driver/include/driver/gpio.h       |  10 +-
 components/driver/include/driver/i2c.h        |   2 +-
 components/driver/include/driver/i2s.h        |   2 +-
 components/driver/include/driver/mcpwm.h      |   1 -
 components/driver/include/driver/rmt.h        |   2 +-
 components/driver/include/driver/sigmadelta.h |   2 +-
 .../driver/include/driver/spi_slave_hd.h      |   2 +-
 components/driver/include/driver/twai.h       |   1 -
 components/driver/include/driver/uart.h       |   7 +-
 components/driver/pcnt.c                      |   4 +-
 components/driver/sdmmc_host.c                |   3 +-
 components/driver/spi_bus_lock.c              |   2 +-
 components/driver/spi_slave.c                 |  25 +-
 components/driver/test/test_pcnt.c            |   4 +-
 components/driver/touch_sensor_common.c       |   1 +
 components/driver/twai.c                      |   4 +-
 components/driver/uart.c                      |  26 +-
 components/esp32/spiram_psram.c               |   4 +-
 components/esp32s2/spiram_psram.c             |   6 +-
 components/esp32s3/spiram_psram.c             |   2 +-
 components/esp_common/include/esp_bit_defs.h  |  33 +++
 components/esp_rom/include/esp32/rom/gpio.h   |   2 +-
 components/esp_rom/include/esp_rom_gpio.h     |   1 +
 components/esp_system/sleep_modes.c           |   4 +-
 components/hal/adc_hal.c                      |   1 +
 components/hal/cpu_hal.c                      |   2 +-
 components/hal/esp32/adc_hal.c                |   1 +
 .../hal/esp32/include/hal/adc_hal_conf.h      |  31 +++
 components/hal/esp32/include/hal/can_types.h  |   2 +-
 components/hal/esp32/include/hal/cpu_ll.h     |   2 +-
 components/hal/esp32/include/hal/gpio_ll.h    |  10 +-
 components/hal/esp32/include/hal/i2c_ll.h     |  12 +-
 components/hal/esp32/include/hal/mcpwm_ll.h   |   2 +-
 components/hal/esp32/include/hal/mpu_ll.h     |   2 +-
 components/hal/esp32/include/hal/rmt_ll.h     |   2 +-
 components/hal/esp32/include/hal/rtc_io_ll.h  |   4 +-
 .../hal/esp32/include/hal/touch_sensor_ll.h   |   2 +-
 components/hal/esp32/include/hal/twai_ll.h    |   6 +-
 components/hal/esp32/include/hal/uart_ll.h    |  21 +-
 components/hal/esp32/touch_sensor_hal.c       |   4 +-
 components/hal/esp32s2/adc_hal.c              |   1 +
 components/hal/esp32s2/cp_dma_hal.c           |   1 +
 .../esp32s2/include/hal/adc_hal_conf.h}       |  17 +-
 components/hal/esp32s2/include/hal/cpu_ll.h   |   2 +-
 components/hal/esp32s2/include/hal/gpio_ll.h  |   5 +-
 components/hal/esp32s2/include/hal/i2c_ll.h   |   8 +-
 components/hal/esp32s2/include/hal/mpu_ll.h   |   2 +-
 components/hal/esp32s2/include/hal/rmt_ll.h   |   2 +-
 .../hal/esp32s2/include/hal/rtc_io_ll.h       |   4 +-
 .../hal/esp32s2/include/hal/touch_sensor_ll.h |  14 +-
 components/hal/esp32s2/include/hal/uart_ll.h  |  11 +-
 components/hal/esp32s2/systimer_hal.c         |   2 +-
 components/hal/esp32s2/touch_sensor_hal.c     |   5 +-
 .../hal/esp32s3/include/hal/adc_hal_conf.h    |  31 +++
 components/hal/esp32s3/include/hal/cpu_ll.h   |   2 +-
 components/hal/esp32s3/include/hal/gdma_ll.h  |   2 +-
 components/hal/esp32s3/include/hal/gpio_ll.h  |   5 +-
 components/hal/esp32s3/include/hal/i2c_ll.h   |  12 +-
 components/hal/esp32s3/include/hal/mcpwm_ll.h |   2 +-
 components/hal/esp32s3/include/hal/mpu_ll.h   |   2 +-
 components/hal/esp32s3/include/hal/rmt_ll.h   |   2 +-
 .../hal/esp32s3/include/hal/rtc_io_ll.h       |   2 +-
 .../hal/esp32s3/include/hal/touch_sensor_ll.h |  14 +-
 components/hal/esp32s3/include/hal/twai_ll.h  |   2 +-
 components/hal/esp32s3/include/hal/uart_ll.h  |   8 +-
 components/hal/esp32s3/systimer_hal.c         |   2 +-
 components/hal/esp32s3/touch_sensor_hal.c     |   4 +-
 components/hal/include/hal/adc_types.h        |   2 +-
 components/hal/include/hal/brownout_hal.h     |   2 +-
 components/hal/include/hal/cpu_hal.h          |   2 +-
 components/hal/include/hal/dac_types.h        |   2 +-
 components/hal/include/hal/gpio_hal.h         |   2 +-
 components/hal/include/hal/gpio_types.h       |  15 +-
 components/hal/include/hal/i2c_types.h        |   2 +-
 components/hal/include/hal/i2s_hal.h          |   2 +-
 components/hal/include/hal/i2s_types.h        |   2 +-
 components/hal/include/hal/ledc_types.h       |   2 +-
 components/hal/include/hal/rmt_hal.h          |   2 +-
 components/hal/include/hal/rmt_types.h        |   2 +-
 components/hal/include/hal/rtc_io_hal.h       |  50 ++--
 components/hal/include/hal/sigmadelta_types.h |  21 +-
 components/hal/include/hal/spi_slave_hal.h    |   4 +-
 components/hal/include/hal/spi_types.h        |   4 +-
 components/hal/include/hal/systimer_types.h   |   2 +-
 components/hal/include/hal/timer_hal.h        |   2 +-
 components/hal/include/hal/timer_types.h      |   2 +-
 .../hal/include/hal/touch_sensor_types.h      |  10 +-
 components/hal/include/hal/twai_types.h       |   9 +-
 components/hal/include/hal/uart_types.h       |   2 +-
 components/hal/include/hal/wdt_hal.h          |   2 +-
 components/hal/mpu_hal.c                      |   2 +-
 components/hal/spi_flash_hal.c                |   2 +-
 components/hal/twai_hal.c                     |   4 +-
 components/soc/soc/esp32/gpio_periph.c        |   4 +-
 .../soc/soc/esp32/include/soc/adc_caps.h      |  31 ---
 .../soc/soc/esp32/include/soc/can_caps.h      |  33 ---
 .../soc/soc/esp32/include/soc/can_periph.h    |   2 +-
 .../soc/soc/esp32/include/soc/dac_caps.h      |  22 --
 .../soc/soc/esp32/include/soc/gpio_caps.h     |  51 ----
 .../include/soc/gpio_pins.h}                  |   5 +-
 .../soc/soc/esp32/include/soc/i2c_caps.h      |  36 ---
 .../soc/soc/esp32/include/soc/i2s_caps.h      |  37 ---
 .../soc/soc/esp32/include/soc/mcpwm_caps.h    |  22 --
 .../soc/soc/esp32/include/soc/mpu_caps.h      |  21 --
 .../soc/soc/esp32/include/soc/rmt_caps.h      |  26 --
 .../soc/soc/esp32/include/soc/rtc_io_caps.h   |  21 --
 .../soc/esp32/include/soc/sigmadelta_caps.h   |  37 ---
 .../soc/soc/esp32/include/soc/soc_caps.h      | 245 +++++++++++++++++-
 .../include/soc/soc_pins.h}                   |  14 +-
 .../include/soc/{spi_caps.h => spi_pins.h}    |  17 --
 .../soc/esp32/include/soc/timer_group_caps.h  |  15 --
 .../soc/esp32/include/soc/touch_sensor_caps.h |  29 ---
 .../soc/soc/esp32/include/soc/twai_caps.h     |  29 ---
 .../soc/soc/esp32/include/soc/uart_caps.h     |  33 ---
 components/soc/soc/esp32/rtc_io_periph.c      |   4 +-
 components/soc/soc/esp32s2/gpio_periph.c      |   4 +-
 .../soc/soc/esp32s2/include/soc/adc_caps.h    |  31 ---
 .../soc/soc/esp32s2/include/soc/dac_caps.h    |  22 --
 .../soc/soc/esp32s2/include/soc/gpio_caps.h   |  48 ----
 .../include/soc/gpio_pins.h}                  |   4 +-
 .../soc/soc/esp32s2/include/soc/i2c_caps.h    |  36 ---
 .../soc/soc/esp32s2/include/soc/i2s_caps.h    |  30 ---
 .../soc/soc/esp32s2/include/soc/mpu_caps.h    |  21 --
 .../soc/soc/esp32s2/include/soc/pcnt_caps.h   |  27 --
 .../soc/soc/esp32s2/include/soc/rmt_caps.h    |  30 ---
 .../soc/soc/esp32s2/include/soc/rtc_io_caps.h |  18 --
 .../soc/esp32s2/include/soc/sigmadelta_caps.h |  37 ---
 .../soc/soc/esp32s2/include/soc/soc_caps.h    | 205 ++++++++++++++-
 .../include/soc/soc_pins.h}                   |  23 +-
 .../soc/soc/esp32s2/include/soc/spi_caps.h    |  59 -----
 .../soc/soc/esp32s2/include/soc/spi_pins.h    |  19 +-
 .../soc/esp32s2/include/soc/systimer_caps.h   |  21 --
 .../esp32s2/include/soc/timer_group_caps.h    |  17 --
 ...ouch_sensor_caps.h => touch_sensor_pins.h} |  11 +-
 .../soc/soc/esp32s2/include/soc/twai_caps.h   |  26 --
 .../soc/soc/esp32s2/include/soc/uart_caps.h   |  32 ---
 .../soc/soc/esp32s2/include/soc/usb_caps.h    |  17 --
 .../soc/soc/esp32s2/include/soc/usb_periph.h  |   2 +-
 components/soc/soc/esp32s2/rtc_io_periph.c    |   4 +-
 components/soc/soc/esp32s2/usb_periph.c       |   2 +-
 components/soc/soc/esp32s3/gpio_periph.c      |   4 +-
 .../soc/soc/esp32s3/include/soc/adc_caps.h    |  16 --
 .../soc/soc/esp32s3/include/soc/gpio_caps.h   |  23 +-
 .../include/soc/gpio_pins.h}                  |   8 +-
 .../soc/soc/esp32s3/include/soc/i2c_caps.h    |   5 +-
 .../soc/soc/esp32s3/include/soc/i2s_caps.h    |  11 +-
 .../soc/soc/esp32s3/include/soc/rtc_io_caps.h |   4 +-
 .../soc/esp32s3/include/soc/sigmadelta_caps.h |  12 -
 .../soc/soc/esp32s3/include/soc/soc_caps.h    |  67 ++++-
 .../include/soc/soc_pins.h}                   |  19 +-
 .../soc/soc/esp32s3/include/soc/spi_caps.h    |  22 +-
 .../soc/soc/esp32s3/include/soc/spi_pins.h    |  10 +-
 .../esp32s3/include/soc/touch_sensor_caps.h   |   3 +-
 .../soc/soc/esp32s3/include/soc/twai_caps.h   |   4 +-
 .../soc/soc/esp32s3/include/soc/uart_caps.h   |   6 +-
 components/soc/soc/esp32s3/rtc_io_periph.c    |   4 +-
 components/soc/soc/include/soc/adc_periph.h   |   4 +-
 components/soc/soc/include/soc/dac_periph.h   |   2 +-
 components/soc/soc/include/soc/gpio_periph.h  |   6 +-
 components/soc/soc/include/soc/i2c_periph.h   |   2 +-
 components/soc/soc/include/soc/i2s_periph.h   |   2 +-
 components/soc/soc/include/soc/ledc_periph.h  |   2 +-
 .../soc/soc/include/soc/rtc_io_periph.h       |   7 +-
 components/soc/soc/include/soc/rtc_periph.h   |   2 +-
 .../soc/soc/include/soc/sdio_slave_periph.h   |   2 +-
 components/soc/soc/include/soc/sdmmc_periph.h |   2 +-
 components/soc/soc/include/soc/spi_periph.h   |   3 +-
 .../soc/soc/include/soc/touch_sensor_periph.h |   2 +-
 components/soc/soc/include/soc/twai_periph.h  |   2 +-
 components/soc/soc/include/soc/uart_periph.h  |   2 +-
 .../peripherals/sdio/host/main/app_main.c     |   2 +-
 .../nvs_rw_blob/main/nvs_blob_example_main.c  |   2 +-
 182 files changed, 1047 insertions(+), 1387 deletions(-)
 create mode 100644 components/hal/esp32/include/hal/adc_hal_conf.h
 rename components/{soc/soc/esp32/include/soc/cpu_caps.h => hal/esp32s2/include/hal/adc_hal_conf.h} (55%)
 create mode 100644 components/hal/esp32s3/include/hal/adc_hal_conf.h
 delete mode 100644 components/soc/soc/esp32/include/soc/adc_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/can_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/dac_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/gpio_caps.h
 rename components/soc/soc/{esp32s2/include/soc/ledc_caps.h => esp32/include/soc/gpio_pins.h} (88%)
 delete mode 100644 components/soc/soc/esp32/include/soc/i2c_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/i2s_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/mcpwm_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/mpu_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/rmt_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/rtc_io_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/sigmadelta_caps.h
 rename components/soc/soc/{esp32s2/include/soc/cpu_caps.h => esp32/include/soc/soc_pins.h} (61%)
 rename components/soc/soc/esp32/include/soc/{spi_caps.h => spi_pins.h} (71%)
 delete mode 100644 components/soc/soc/esp32/include/soc/timer_group_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/touch_sensor_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/twai_caps.h
 delete mode 100644 components/soc/soc/esp32/include/soc/uart_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/adc_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/dac_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/gpio_caps.h
 rename components/soc/soc/{esp32/include/soc/ledc_caps.h => esp32s2/include/soc/gpio_pins.h} (88%)
 delete mode 100644 components/soc/soc/esp32s2/include/soc/i2c_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/i2s_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/mpu_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/pcnt_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/rmt_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/rtc_io_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/sigmadelta_caps.h
 rename components/soc/soc/{esp32/include/soc/brownout_caps.h => esp32s2/include/soc/soc_pins.h} (61%)
 delete mode 100644 components/soc/soc/esp32s2/include/soc/spi_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/systimer_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/timer_group_caps.h
 rename components/soc/soc/esp32s2/include/soc/{touch_sensor_caps.h => touch_sensor_pins.h} (70%)
 delete mode 100644 components/soc/soc/esp32s2/include/soc/twai_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/uart_caps.h
 delete mode 100644 components/soc/soc/esp32s2/include/soc/usb_caps.h
 rename components/soc/soc/{esp32/include/soc/pcnt_caps.h => esp32s3/include/soc/gpio_pins.h} (86%)
 rename components/soc/soc/{esp32s2/include/soc/brownout_caps.h => esp32s3/include/soc/soc_pins.h} (61%)

diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32.c b/components/bootloader_support/src/bootloader_flash_config_esp32.c
index e6a491731c4..538ed38b633 100644
--- a/components/bootloader_support/src/bootloader_flash_config_esp32.c
+++ b/components/bootloader_support/src/bootloader_flash_config_esp32.c
@@ -23,7 +23,8 @@
 #include "soc/gpio_periph.h"
 #include "soc/efuse_reg.h"
 #include "soc/spi_reg.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
+#include "soc/soc_pins.h"
 #include "flash_qio_mode.h"
 #include "bootloader_common.h"
 #include "bootloader_flash_config.h"
diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32s2.c b/components/bootloader_support/src/bootloader_flash_config_esp32s2.c
index a8c40d1658c..cc487a40f58 100644
--- a/components/bootloader_support/src/bootloader_flash_config_esp32s2.c
+++ b/components/bootloader_support/src/bootloader_flash_config_esp32s2.c
@@ -21,7 +21,7 @@
 #include "soc/efuse_reg.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "flash_qio_mode.h"
 #include "bootloader_flash_config.h"
 #include "bootloader_common.h"
diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32s3.c b/components/bootloader_support/src/bootloader_flash_config_esp32s3.c
index d62a850b3b2..ea913e8c706 100644
--- a/components/bootloader_support/src/bootloader_flash_config_esp32s3.c
+++ b/components/bootloader_support/src/bootloader_flash_config_esp32s3.c
@@ -21,7 +21,7 @@
 #include "soc/efuse_reg.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "flash_qio_mode.h"
 #include "bootloader_flash_config.h"
 #include "bootloader_common.h"
diff --git a/components/bootloader_support/src/bootloader_mem.c b/components/bootloader_support/src/bootloader_mem.c
index e5a2218cc91..50d22ff2306 100644
--- a/components/bootloader_support/src/bootloader_mem.c
+++ b/components/bootloader_support/src/bootloader_mem.c
@@ -18,7 +18,7 @@
 #include "hal/cpu_hal.h"
 #include "hal/mpu_hal.h"
 #include "hal/mpu_types.h"
-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"
 #include "bootloader_mem.h"
 #include "xt_instr_macros.h"
 #include "xtensa/config/specreg.h"
@@ -28,7 +28,7 @@ static inline void cpu_configure_region_protection(void)
     /* Currently, the only supported chips esp32 and esp32s2
      * have the same configuration. Move this to the port layer once
      * more chips with different configurations are supported.
-     * 
+     *
      * Both chips have the address space divided into 8 regions, 512MB each.
      */
     const int illegal_regions[] = {0, 4, 5, 6, 7}; // 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
diff --git a/components/driver/adc_common.c b/components/driver/adc_common.c
index 109c9cabfcc..6e0feb763d9 100644
--- a/components/driver/adc_common.c
+++ b/components/driver/adc_common.c
@@ -32,6 +32,7 @@
 #include "hal/adc_types.h"
 #include "hal/adc_hal.h"
 #include "hal/dac_hal.h"
+#include "hal/adc_hal_conf.h"
 
 #define ADC_CHECK_RET(fun_ret) ({                  \
     if (fun_ret != ESP_OK) {                                \
diff --git a/components/driver/esp32/touch_sensor.c b/components/driver/esp32/touch_sensor.c
index f04c039f85b..9f61299944e 100644
--- a/components/driver/esp32/touch_sensor.c
+++ b/components/driver/esp32/touch_sensor.c
@@ -187,9 +187,9 @@ esp_err_t touch_pad_get_trigger_source(touch_trigger_src_t *src)
 
 esp_err_t touch_pad_set_group_mask(uint16_t set1_mask, uint16_t set2_mask, uint16_t en_mask)
 {
-    TOUCH_CHECK((set1_mask <= SOC_TOUCH_SENSOR_BIT_MASK_MAX), "touch set1 bitmask error", ESP_ERR_INVALID_ARG);
-    TOUCH_CHECK((set2_mask <= SOC_TOUCH_SENSOR_BIT_MASK_MAX), "touch set2 bitmask error", ESP_ERR_INVALID_ARG);
-    TOUCH_CHECK((en_mask <= SOC_TOUCH_SENSOR_BIT_MASK_MAX), "touch work_en bitmask error", ESP_ERR_INVALID_ARG);
+    TOUCH_CHECK((set1_mask <= TOUCH_PAD_BIT_MASK_ALL), "touch set1 bitmask error", ESP_ERR_INVALID_ARG);
+    TOUCH_CHECK((set2_mask <= TOUCH_PAD_BIT_MASK_ALL), "touch set2 bitmask error", ESP_ERR_INVALID_ARG);
+    TOUCH_CHECK((en_mask <= TOUCH_PAD_BIT_MASK_ALL), "touch work_en bitmask error", ESP_ERR_INVALID_ARG);
 
     TOUCH_ENTER_CRITICAL();
     touch_hal_set_group_mask(set1_mask, set2_mask);
@@ -211,9 +211,9 @@ esp_err_t touch_pad_get_group_mask(uint16_t *set1_mask, uint16_t *set2_mask, uin
 
 esp_err_t touch_pad_clear_group_mask(uint16_t set1_mask, uint16_t set2_mask, uint16_t en_mask)
 {
-    TOUCH_CHECK((set1_mask <= SOC_TOUCH_SENSOR_BIT_MASK_MAX), "touch set1 bitmask error", ESP_ERR_INVALID_ARG);
-    TOUCH_CHECK((set2_mask <= SOC_TOUCH_SENSOR_BIT_MASK_MAX), "touch set2 bitmask error", ESP_ERR_INVALID_ARG);
-    TOUCH_CHECK((en_mask <= SOC_TOUCH_SENSOR_BIT_MASK_MAX), "touch work_en bitmask error", ESP_ERR_INVALID_ARG);
+    TOUCH_CHECK((set1_mask <= TOUCH_PAD_BIT_MASK_ALL), "touch set1 bitmask error", ESP_ERR_INVALID_ARG);
+    TOUCH_CHECK((set2_mask <= TOUCH_PAD_BIT_MASK_ALL), "touch set2 bitmask error", ESP_ERR_INVALID_ARG);
+    TOUCH_CHECK((en_mask <= TOUCH_PAD_BIT_MASK_ALL), "touch work_en bitmask error", ESP_ERR_INVALID_ARG);
 
     TOUCH_ENTER_CRITICAL();
     touch_hal_clear_channel_mask(en_mask);
diff --git a/components/driver/esp32s2/touch_sensor.c b/components/driver/esp32s2/touch_sensor.c
index f9aa9baca14..44faa510f67 100644
--- a/components/driver/esp32s2/touch_sensor.c
+++ b/components/driver/esp32s2/touch_sensor.c
@@ -17,6 +17,7 @@
 #include <ctype.h>
 #include "esp_log.h"
 #include "sys/lock.h"
+#include "soc/soc_pins.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/xtensa_api.h"
 #include "freertos/semphr.h"
@@ -53,7 +54,7 @@ static const char *TOUCH_TAG = "TOUCH_SENSOR";
         TOUCH_CHECK(channel < SOC_TOUCH_SENSOR_NUM && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \
         TOUCH_CHECK(channel != SOC_TOUCH_DENOISE_CHANNEL, "TOUCH0 is internal denoise channel", ESP_ERR_INVALID_ARG); \
     } while (0);
-#define TOUCH_CH_MASK_CHECK(mask) TOUCH_CHECK((mask <= SOC_TOUCH_SENSOR_BIT_MASK_MAX), "touch channel bitmask error", ESP_ERR_INVALID_ARG)
+#define TOUCH_CH_MASK_CHECK(mask) TOUCH_CHECK((mask <= TOUCH_PAD_BIT_MASK_ALL), "touch channel bitmask error", ESP_ERR_INVALID_ARG)
 #define TOUCH_INTR_MASK_CHECK(mask) TOUCH_CHECK(mask & TOUCH_PAD_INTR_MASK_ALL, "intr mask error", ESP_ERR_INVALID_ARG)
 #define TOUCH_PARAM_CHECK_STR(s)           ""s" parameter error"
 
diff --git a/components/driver/gpio.c b/components/driver/gpio.c
index 06759ca74ce..99bb7bec8bc 100644
--- a/components/driver/gpio.c
+++ b/components/driver/gpio.c
@@ -24,7 +24,7 @@
 #include "esp_ipc.h"
 #endif
 
-#include "soc/gpio_caps.h"
+#include "soc/soc_caps.h"
 #include "soc/gpio_periph.h"
 #include "esp_log.h"
 #include "hal/gpio_hal.h"
@@ -76,7 +76,7 @@ esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pullup_en(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -91,7 +91,7 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pullup_dis(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -106,7 +106,7 @@ esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pulldown_en(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -121,7 +121,7 @@ esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pulldown_dis(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -302,26 +302,23 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
     uint8_t pu_en = 0;
     uint8_t pd_en = 0;
 
-    if (pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) {
+    if (pGPIOConfig->pin_bit_mask == 0 ||
+        pGPIOConfig->pin_bit_mask & ~SOC_GPIO_VALID_GPIO_MASK) {
         ESP_LOGE(GPIO_TAG, "GPIO_PIN mask error ");
         return ESP_ERR_INVALID_ARG;
     }
 
-    if ((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) {
-        if(GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_pin_mask)) {
-            ESP_LOGE(GPIO_TAG, "GPIO can only be used as input mode");
-            return ESP_ERR_INVALID_ARG;
-        }
+    if (pGPIOConfig->mode & GPIO_MODE_DEF_OUTPUT &&
+        pGPIOConfig->pin_bit_mask & ~SOC_GPIO_VALID_OUTPUT_GPIO_MASK) {
+        ESP_LOGE(GPIO_TAG, "GPIO can only be used as input mode");
+        return ESP_ERR_INVALID_ARG;
     }
 
     do {
         io_reg = GPIO_PIN_MUX_REG[io_num];
 
         if (((gpio_pin_mask >> io_num) & BIT(0))) {
-            if (!io_reg) {
-                ESP_LOGE(GPIO_TAG, "IO%d is not a valid GPIO", io_num);
-                return ESP_ERR_INVALID_ARG;
-            }
+            assert(io_reg != (intptr_t)NULL);
 
             if (rtc_gpio_is_valid_gpio(io_num)) {
                 rtc_gpio_deinit(io_num);
@@ -568,7 +565,7 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng
     GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG);
     esp_err_t ret = ESP_OK;
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_set_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -585,7 +582,7 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
     GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG);
     esp_err_t ret = ESP_OK;
 
-    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_get_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
@@ -646,7 +643,7 @@ void gpio_deep_sleep_hold_dis(void)
     portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
 }
 
-#if GPIO_SUPPORTS_FORCE_HOLD
+#if SOC_GPIO_SUPPORT_FORCE_HOLD
 
 esp_err_t gpio_force_hold_all()
 {
diff --git a/components/driver/i2c.c b/components/driver/i2c.c
index 25a68907dc4..93f050459b0 100644
--- a/components/driver/i2c.c
+++ b/components/driver/i2c.c
@@ -155,7 +155,7 @@ typedef struct {
     i2c_hal_context_t hal;      /*!< I2C hal context */
     portMUX_TYPE spinlock;
     bool hw_enabled;
-#if !I2C_SUPPORT_HW_CLR_BUS
+#if !SOC_I2C_SUPPORT_HW_CLR_BUS
     int scl_io_num;
     int sda_io_num;
 #endif
@@ -304,8 +304,8 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
     }
     i2c_hw_enable(i2c_num);
     //Disable I2C interrupt.
-    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
-    i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
+    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
+    i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
     //hook isr handler
     i2c_isr_register(i2c_num, i2c_isr_handler_default, p_i2c_obj[i2c_num], intr_alloc_flags, &p_i2c_obj[i2c_num]->intr_handle);
     //Enable I2C slave rx interrupt
@@ -364,7 +364,7 @@ esp_err_t i2c_driver_delete(i2c_port_t i2c_num)
     I2C_CHECK(p_i2c_obj[i2c_num] != NULL, I2C_DRIVER_ERR_STR, ESP_FAIL);
 
     i2c_obj_t *p_i2c = p_i2c_obj[i2c_num];
-    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
+    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
     esp_intr_free(p_i2c->intr_handle);
     p_i2c->intr_handle = NULL;
 
@@ -516,7 +516,7 @@ esp_err_t i2c_get_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t *tx_trans_mode,
  **/
 static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
 {
-#if !I2C_SUPPORT_HW_CLR_BUS
+#if !SOC_I2C_SUPPORT_HW_CLR_BUS
     const int scl_half_period = I2C_CLR_BUS_HALF_PERIOD_US; // use standard 100kHz data rate
     int i = 0;
     int scl_io = i2c_context[i2c_num].scl_io_num;
@@ -554,7 +554,7 @@ static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
  **/
 static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num)
 {
-#if !I2C_SUPPORT_HW_FSM_RST
+#if !SOC_I2C_SUPPORT_HW_FSM_RST
     int scl_low_period, scl_high_period;
     int scl_start_hold, scl_rstart_setup;
     int scl_stop_hold, scl_stop_setup;
@@ -575,8 +575,8 @@ static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num)
     i2c_hw_enable(i2c_num);
 
     i2c_hal_master_init(&(i2c_context[i2c_num].hal), i2c_num);
-    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
-    i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
+    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
+    i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
     i2c_hal_set_scl_timing(&(i2c_context[i2c_num].hal), scl_high_period, scl_low_period);
     i2c_hal_set_start_timing(&(i2c_context[i2c_num].hal), scl_rstart_setup, scl_start_hold);
     i2c_hal_set_stop_timing(&(i2c_context[i2c_num].hal), scl_stop_setup, scl_stop_hold);
@@ -603,8 +603,8 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
     }
     i2c_hw_enable(i2c_num);
     I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock));
-    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
-    i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
+    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
+    i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
     if (i2c_conf->mode == I2C_MODE_SLAVE) {  //slave mode
         i2c_hal_slave_init(&(i2c_context[i2c_num].hal), i2c_num);
         i2c_hal_set_slave_addr(&(i2c_context[i2c_num].hal), i2c_conf->slave.slave_addr, i2c_conf->slave.addr_10bit_en);
@@ -805,7 +805,7 @@ esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num, bool s
             gpio_set_pull_mode(scl_io_num, GPIO_FLOATING);
         }
     }
-#if !I2C_SUPPORT_HW_CLR_BUS
+#if !SOC_I2C_SUPPORT_HW_CLR_BUS
     i2c_context[i2c_num].scl_io_num = scl_io_num;
     i2c_context[i2c_num].sda_io_num = sda_io_num;
 #endif
@@ -1155,8 +1155,8 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle,
     i2c_reset_rx_fifo(i2c_num);
     // These two interrupts some times can not be cleared when the FSM gets stuck.
     // so we disable them when these two interrupt occurs and re-enable them here.
-    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
-    i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK);
+    i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
+    i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK);
     //start send commands, at most 32 bytes one time, isr handler will process the remaining commands.
     i2c_master_cmd_begin_static(i2c_num);
 
diff --git a/components/driver/i2s.c b/components/driver/i2s.c
index 85bcc8c8eeb..36de066df03 100644
--- a/components/driver/i2s.c
+++ b/components/driver/i2s.c
@@ -54,6 +54,11 @@ static const char* I2S_TAG = "I2S";
 #define I2S_FULL_DUPLEX_SLAVE_MODE_MASK   (I2S_MODE_TX | I2S_MODE_RX | I2S_MODE_SLAVE)
 #define I2S_FULL_DUPLEX_MASTER_MODE_MASK  (I2S_MODE_TX | I2S_MODE_RX | I2S_MODE_MASTER)
 
+//TODO: Refactor to put this logic into LL
+#define I2S_AD_BCK_FACTOR                 (2)
+#define I2S_PDM_BCK_FACTOR                (64)
+#define I2S_BASE_CLK                      (2*APB_CLK_FREQ)
+
 /**
  * @brief DMA buffer object
  *
@@ -112,7 +117,7 @@ static inline void gpio_matrix_out_check(uint32_t gpio, uint32_t signal_idx, boo
     //if pin = -1, do not need to configure
     if (gpio != -1) {
         PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
-        gpio_set_direction(gpio, GPIO_MODE_DEF_OUTPUT);
+        gpio_set_direction(gpio, GPIO_MODE_OUTPUT);
         esp_rom_gpio_connect_out_signal(gpio, signal_idx, out_inv, oen_inv);
     }
 }
@@ -122,7 +127,7 @@ static inline void gpio_matrix_in_check(uint32_t gpio, uint32_t signal_idx, bool
     if (gpio != -1) {
         PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
         //Set direction, for some GPIOs, the input function are not enabled as default.
-        gpio_set_direction(gpio, GPIO_MODE_DEF_INPUT);
+        gpio_set_direction(gpio, GPIO_MODE_INPUT);
         esp_rom_gpio_connect_in_signal(gpio, signal_idx, inv);
     }
 }
@@ -190,8 +195,8 @@ static float i2s_apll_get_fi2s(int bits_per_sample, int sdm0, int sdm1, int sdm2
     }
 #endif
     float fout = f_xtal * (sdm2 + sdm1 / 256.0f + sdm0 / 65536.0f + 4);
-    if (fout < APLL_MIN_FREQ || fout > APLL_MAX_FREQ) {
-        return APLL_MAX_FREQ;
+    if (fout < SOC_I2S_APLL_MIN_FREQ || fout > SOC_I2S_APLL_MAX_FREQ) {
+        return SOC_I2S_APLL_MAX_FREQ;
     }
     float fpll = fout / (2 * (odir+2)); //== fi2s (N=1, b=0, a=1)
     return fpll/2;
@@ -236,7 +241,7 @@ static esp_err_t i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm
     int _odir, _sdm0, _sdm1, _sdm2;
     float avg;
     float min_rate, max_rate, min_diff;
-    if (rate/bits_per_sample/2/8 < APLL_I2S_MIN_RATE) {
+    if (rate/bits_per_sample/2/8 < SOC_I2S_APLL_MIN_RATE) {
         return ESP_ERR_INVALID_ARG;
     }
 
@@ -244,7 +249,7 @@ static esp_err_t i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm
     *sdm1 = 0;
     *sdm2 = 0;
     *odir = 0;
-    min_diff = APLL_MAX_FREQ;
+    min_diff = SOC_I2S_APLL_MAX_FREQ;
 
     for (_sdm2 = 4; _sdm2 < 9; _sdm2 ++) {
         max_rate = i2s_apll_get_fi2s(bits_per_sample, 255, 255, _sdm2, 0);
@@ -255,7 +260,7 @@ static esp_err_t i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm
             *sdm2 = _sdm2;
         }
     }
-    min_diff = APLL_MAX_FREQ;
+    min_diff = SOC_I2S_APLL_MAX_FREQ;
     for (_odir = 0; _odir < 32; _odir ++) {
         max_rate = i2s_apll_get_fi2s(bits_per_sample, 255, 255, *sdm2, _odir);
         min_rate = i2s_apll_get_fi2s(bits_per_sample, 0, 0, *sdm2, _odir);
@@ -265,7 +270,7 @@ static esp_err_t i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm
             *odir = _odir;
         }
     }
-    min_diff = APLL_MAX_FREQ;
+    min_diff = SOC_I2S_APLL_MAX_FREQ;
     for (_sdm2 = 4; _sdm2 < 9; _sdm2 ++) {
         max_rate = i2s_apll_get_fi2s(bits_per_sample, 255, 255, _sdm2, *odir);
         min_rate = i2s_apll_get_fi2s(bits_per_sample, 0, 0, _sdm2, *odir);
@@ -276,7 +281,7 @@ static esp_err_t i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm
         }
     }
 
-    min_diff = APLL_MAX_FREQ;
+    min_diff = SOC_I2S_APLL_MAX_FREQ;
     for (_sdm1 = 0; _sdm1 < 256; _sdm1 ++) {
         max_rate = i2s_apll_get_fi2s(bits_per_sample, 255, _sdm1, *sdm2, *odir);
         min_rate = i2s_apll_get_fi2s(bits_per_sample, 0, _sdm1, *sdm2, *odir);
@@ -287,7 +292,7 @@ static esp_err_t i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm
         }
     }
 
-    min_diff = APLL_MAX_FREQ;
+    min_diff = SOC_I2S_APLL_MAX_FREQ;
     for (_sdm0 = 0; _sdm0 < 256; _sdm0 ++) {
         avg = i2s_apll_get_fi2s(bits_per_sample, _sdm0, *sdm1, *sdm2, *odir);
         if (abs(avg - rate) < min_diff) {
@@ -501,7 +506,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
         //Avoid spurious interrupt
         return;
     }
-    
+
     i2s_event_t i2s_event;
     int dummy;
 
@@ -922,7 +927,7 @@ esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config,
         }
         memset(p_i2s_obj[i2s_num], 0, sizeof(i2s_obj_t));
 
-        portMUX_TYPE i2s_spinlock_unlocked[1] = {portMUX_INITIALIZER_UNLOCKED}; 
+        portMUX_TYPE i2s_spinlock_unlocked[1] = {portMUX_INITIALIZER_UNLOCKED};
         for (int x = 0; x < I2S_NUM_MAX; x++) {
             i2s_spinlock[x] = i2s_spinlock_unlocked[0];
         }
@@ -1036,7 +1041,7 @@ esp_err_t i2s_write(i2s_port_t i2s_num, const void *src, size_t size, size_t *by
     int bytes_can_write;
     *bytes_written = 0;
     I2S_CHECK((i2s_num < I2S_NUM_MAX), "i2s_num error", ESP_ERR_INVALID_ARG);
-    I2S_CHECK((size < I2S_MAX_BUFFER_SIZE), "size is too large", ESP_ERR_INVALID_ARG);
+    I2S_CHECK((size < SOC_I2S_MAX_BUFFER_SIZE), "size is too large", ESP_ERR_INVALID_ARG);
     I2S_CHECK((p_i2s_obj[i2s_num]->tx), "tx NULL", ESP_ERR_INVALID_ARG);
     xSemaphoreTake(p_i2s_obj[i2s_num]->tx->mux, (portTickType)portMAX_DELAY);
 #ifdef CONFIG_PM_ENABLE
@@ -1105,7 +1110,7 @@ esp_err_t i2s_write_expand(i2s_port_t i2s_num, const void *src, size_t size, siz
     *bytes_written = 0;
     I2S_CHECK((i2s_num < I2S_NUM_MAX), "i2s_num error", ESP_ERR_INVALID_ARG);
     I2S_CHECK((size > 0), "size must greater than zero", ESP_ERR_INVALID_ARG);
-    I2S_CHECK((aim_bits * size < I2S_MAX_BUFFER_SIZE), "size is too large", ESP_ERR_INVALID_ARG);
+    I2S_CHECK((aim_bits * size < SOC_I2S_MAX_BUFFER_SIZE), "size is too large", ESP_ERR_INVALID_ARG);
     I2S_CHECK((aim_bits >= src_bits), "aim_bits mustn't be less than src_bits", ESP_ERR_INVALID_ARG);
     I2S_CHECK((p_i2s_obj[i2s_num]->tx), "tx NULL", ESP_ERR_INVALID_ARG);
     if (src_bits < I2S_BITS_PER_SAMPLE_8BIT || aim_bits < I2S_BITS_PER_SAMPLE_8BIT) {
@@ -1167,7 +1172,7 @@ esp_err_t i2s_read(i2s_port_t i2s_num, void *dest, size_t size, size_t *bytes_re
     *bytes_read = 0;
     dest_byte = (char *)dest;
     I2S_CHECK((i2s_num < I2S_NUM_MAX), "i2s_num error", ESP_ERR_INVALID_ARG);
-    I2S_CHECK((size < I2S_MAX_BUFFER_SIZE), "size is too large", ESP_ERR_INVALID_ARG);
+    I2S_CHECK((size < SOC_I2S_MAX_BUFFER_SIZE), "size is too large", ESP_ERR_INVALID_ARG);
     I2S_CHECK((p_i2s_obj[i2s_num]->rx), "rx NULL", ESP_ERR_INVALID_ARG);
     xSemaphoreTake(p_i2s_obj[i2s_num]->rx->mux, (portTickType)portMAX_DELAY);
 #ifdef CONFIG_PM_ENABLE
diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h
index bc3c56cd089..28a5337e2e1 100644
--- a/components/driver/include/driver/gpio.h
+++ b/components/driver/include/driver/gpio.h
@@ -19,6 +19,7 @@
 #include <esp_bit_defs.h>
 #include "esp_attr.h"
 #include "esp_intr_alloc.h"
+#include "soc/soc_caps.h"
 #include "soc/gpio_periph.h"
 #include "hal/gpio_types.h"
 
@@ -40,6 +41,13 @@
 extern "C" {
 #endif
 
+#define GPIO_PIN_COUNT                      (SOC_GPIO_PIN_COUNT)
+/// Check whether it is a valid GPIO number
+#define GPIO_IS_VALID_GPIO(gpio_num)        (((1ULL << (gpio_num)) & SOC_GPIO_VALID_GPIO_MASK) != 0)
+/// Check whether it can be a valid GPIO number of output mode
+#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)
+
+
 typedef intr_handle_t gpio_isr_handle_t;
 
 /**
@@ -419,7 +427,7 @@ void gpio_iomux_in(uint32_t gpio_num, uint32_t signal_idx);
   */
 void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv);
 
-#if GPIO_SUPPORTS_FORCE_HOLD
+#if SOC_GPIO_SUPPORT_FORCE_HOLD
 /**
   * @brief Force hold digital and rtc gpio pad.
   * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
diff --git a/components/driver/include/driver/i2c.h b/components/driver/include/driver/i2c.h
index 8a1084c2bf6..3cd9f3b74db 100644
--- a/components/driver/include/driver/i2c.h
+++ b/components/driver/include/driver/i2c.h
@@ -29,8 +29,8 @@ extern "C" {
 #include "freertos/queue.h"
 #include "freertos/ringbuf.h"
 #include "driver/gpio.h"
+#include "soc/soc_caps.h"
 #include "hal/i2c_types.h"
-#include "soc/i2c_caps.h"
 
 #define I2C_APB_CLK_FREQ  APB_CLK_FREQ /*!< I2C source clock is APB clock, 80MHz */
 
diff --git a/components/driver/include/driver/i2s.h b/components/driver/include/driver/i2s.h
index 01bc1472bc6..e5968ad3f71 100644
--- a/components/driver/include/driver/i2s.h
+++ b/components/driver/include/driver/i2s.h
@@ -20,7 +20,7 @@
 #include "freertos/semphr.h"
 #include "soc/i2s_periph.h"
 #include "soc/rtc_periph.h"
-#include "soc/i2s_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/i2s_hal.h"
 #include "hal/i2s_types.h"
 #include "driver/periph_ctrl.h"
diff --git a/components/driver/include/driver/mcpwm.h b/components/driver/include/driver/mcpwm.h
index 7f5b71feaa4..1021ad58d6d 100644
--- a/components/driver/include/driver/mcpwm.h
+++ b/components/driver/include/driver/mcpwm.h
@@ -26,7 +26,6 @@
 #include "driver/periph_ctrl.h"
 #include "esp_intr_alloc.h"
 #include "hal/mcpwm_types.h"
-#include "soc/mcpwm_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/driver/include/driver/rmt.h b/components/driver/include/driver/rmt.h
index 4fb9730a9e6..4764a976e5b 100644
--- a/components/driver/include/driver/rmt.h
+++ b/components/driver/include/driver/rmt.h
@@ -21,10 +21,10 @@ extern "C" {
 #include <stdbool.h>
 #include <stdint.h>
 #include "esp_err.h"
+#include "soc/soc_caps.h"
 #include "driver/gpio.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/ringbuf.h"
-#include "soc/rmt_caps.h"
 #include "soc/rmt_struct.h"
 #include "hal/rmt_types.h"
 
diff --git a/components/driver/include/driver/sigmadelta.h b/components/driver/include/driver/sigmadelta.h
index 6a6aa487ac6..d7e7eef122c 100644
--- a/components/driver/include/driver/sigmadelta.h
+++ b/components/driver/include/driver/sigmadelta.h
@@ -14,8 +14,8 @@
 #pragma once
 
 #include <esp_types.h>
+#include "soc/soc_caps.h"
 #include "soc/sigmadelta_periph.h"
-#include "soc/sigmadelta_caps.h"
 #include "driver/gpio.h"
 #include "hal/sigmadelta_types.h"
 
diff --git a/components/driver/include/driver/spi_slave_hd.h b/components/driver/include/driver/spi_slave_hd.h
index f096f34c6c8..cea9cd2a9c2 100644
--- a/components/driver/include/driver/spi_slave_hd.h
+++ b/components/driver/include/driver/spi_slave_hd.h
@@ -15,7 +15,7 @@
 #pragma once
 
 #include "esp_types.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "freertos/FreeRTOS.h"
 
 #include "hal/spi_types.h"
diff --git a/components/driver/include/driver/twai.h b/components/driver/include/driver/twai.h
index ef240a383d8..b1919c7f7f8 100644
--- a/components/driver/include/driver/twai.h
+++ b/components/driver/include/driver/twai.h
@@ -28,7 +28,6 @@ extern "C" {
 #include "esp_intr_alloc.h"
 #include "esp_err.h"
 #include "gpio.h"
-#include "soc/twai_caps.h"
 #include "hal/twai_types.h"
 
 /* -------------------- Default initializers and flags ---------------------- */
diff --git a/components/driver/include/driver/uart.h b/components/driver/include/driver/uart.h
index 7be0fb024d4..45564a0a9a8 100644
--- a/components/driver/include/driver/uart.h
+++ b/components/driver/include/driver/uart.h
@@ -20,6 +20,7 @@ extern "C" {
 
 #include "esp_err.h"
 #include "esp_intr_alloc.h"
+#include "soc/soc_caps.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "freertos/xtensa_api.h"
@@ -27,7 +28,6 @@ extern "C" {
 #include "freertos/queue.h"
 #include "freertos/ringbuf.h"
 #include "hal/uart_types.h"
-#include "soc/uart_caps.h"
 
 // Valid UART port number
 #define UART_NUM_0             (0) /*!< UART port 0 */
@@ -39,6 +39,9 @@ extern "C" {
 
 #define UART_PIN_NO_CHANGE      (-1)         /*!< Constant for uart_set_pin function which indicates that UART pin should not be changed */
 
+#define UART_FIFO_LEN           SOC_UART_FIFO_LEN       ///< Length of the UART HW FIFO
+#define UART_BITRATE_MAX        SOC_UART_BITRATE_MAX    ///< Maximum configurable bitrate
+
 /**
  * @brief UART interrupt configuration parameters for uart_intr_config function
  */
@@ -224,7 +227,7 @@ esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t* baudrate);
  * @brief Set UART line inverse mode
  *
  * @param uart_num  UART port number, the max port number is (UART_NUM_MAX -1).
- * @param inverse_mask Choose the wires that need to be inverted. Using the ORred mask of `uart_signal_inv_t` 
+ * @param inverse_mask Choose the wires that need to be inverted. Using the ORred mask of `uart_signal_inv_t`
  *
  * @return
  *     - ESP_OK   Success
diff --git a/components/driver/pcnt.c b/components/driver/pcnt.c
index 960037dcd35..8557e2f5625 100644
--- a/components/driver/pcnt.c
+++ b/components/driver/pcnt.c
@@ -12,6 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+#include "soc/soc_caps.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "freertos/xtensa_api.h"
@@ -19,7 +20,6 @@
 #include "driver/pcnt.h"
 #include "driver/periph_ctrl.h"
 #include "hal/pcnt_hal.h"
-#include "soc/pcnt_caps.h"
 #include "esp_rom_gpio.h"
 
 #define PCNT_CHANNEL_ERR_STR  "PCNT CHANNEL ERROR"
@@ -287,7 +287,7 @@ static void IRAM_ATTR pcnt_intr_service(void *arg)
     uint32_t status;
     pcnt_port_t pcnt_port = (pcnt_port_t)arg;
     pcnt_hal_get_intr_status(&(p_pcnt_obj[pcnt_port]->hal), &status);
-    
+
     while (status) {
         int unit = __builtin_ffs(status) - 1;
         status &= ~(1 << unit);
diff --git a/components/driver/sdmmc_host.c b/components/driver/sdmmc_host.c
index 4253a8797fa..93c2b3dceda 100644
--- a/components/driver/sdmmc_host.c
+++ b/components/driver/sdmmc_host.c
@@ -17,8 +17,9 @@
 #include <sys/param.h>
 #include "esp_log.h"
 #include "esp_intr_alloc.h"
+#include "soc/soc_caps.h"
+#include "soc/soc_pins.h"
 #include "soc/gpio_periph.h"
-#include "soc/gpio_caps.h"
 #include "esp_rom_gpio.h"
 #include "esp_rom_sys.h"
 #include "driver/gpio.h"
diff --git a/components/driver/spi_bus_lock.c b/components/driver/spi_bus_lock.c
index ec6e924054b..bb4f18444cf 100644
--- a/components/driver/spi_bus_lock.c
+++ b/components/driver/spi_bus_lock.c
@@ -18,7 +18,7 @@
 #include "sdkconfig.h"
 #include "spi_common_internal.h"
 #include "esp_intr_alloc.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "stdatomic.h"
 #include "esp_log.h"
 #include <strings.h>
diff --git a/components/driver/spi_slave.c b/components/driver/spi_slave.c
index dbb332cc355..fa970689dcb 100644
--- a/components/driver/spi_slave.c
+++ b/components/driver/spi_slave.c
@@ -13,29 +13,30 @@
 // limitations under the License.
 
 #include <string.h>
-#include "sdkconfig.h"
-#include <hal/spi_ll.h>
-#include <hal/spi_slave_hal.h>
-#include <soc/lldesc.h>
-#include "driver/spi_common_internal.h"
-#include "driver/spi_slave.h"
-#include "soc/spi_periph.h"
-#include "soc/gpio_caps.h"
 #include "esp_types.h"
 #include "esp_attr.h"
 #include "esp_intr_alloc.h"
 #include "esp_log.h"
 #include "esp_err.h"
 #include "esp_pm.h"
+#include "esp_heap_caps.h"
+#include "esp_rom_gpio.h"
+#include "esp_rom_sys.h"
+#include "soc/lldesc.h"
+#include "soc/soc_caps.h"
+#include "soc/spi_periph.h"
+#include "soc/soc_memory_layout.h"
+#include "hal/spi_ll.h"
+#include "hal/spi_slave_hal.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "freertos/xtensa_api.h"
 #include "freertos/task.h"
-#include "soc/soc_memory_layout.h"
+#include "sdkconfig.h"
+
 #include "driver/gpio.h"
-#include "esp_heap_caps.h"
-#include "esp_rom_gpio.h"
-#include "esp_rom_sys.h"
+#include "driver/spi_common_internal.h"
+#include "driver/spi_slave.h"
 #include "hal/spi_slave_hal.h"
 
 static const char *SPI_TAG = "spi_slave";
diff --git a/components/driver/test/test_pcnt.c b/components/driver/test/test_pcnt.c
index a0feba6245b..ebb3effed51 100644
--- a/components/driver/test/test_pcnt.c
+++ b/components/driver/test/test_pcnt.c
@@ -21,7 +21,7 @@
 #include "esp_attr.h"
 #include "esp_log.h"
 #include "soc/gpio_periph.h"
-#include "soc/gpio_caps.h"
+#include "soc/soc_caps.h"
 #include "unity.h"
 #include "esp_rom_gpio.h"
 
@@ -606,7 +606,7 @@ TEST_CASE("PCNT interrupt method test(control IO is low)", "[pcnt][timeout=120]"
     TEST_ESP_OK(pcnt_counter_clear(PCNT_UNIT_0));
 
     pcnt_evt_queue = xQueueCreate(10, sizeof(uint32_t));
-    
+
     pcnt_isr_handle_t pcnt_isr_service;
     TEST_ESP_OK(pcnt_isr_register(pcnt_intr_handler, NULL, 0, &pcnt_isr_service));
     TEST_ESP_OK(pcnt_intr_enable(PCNT_UNIT_0));
diff --git a/components/driver/touch_sensor_common.c b/components/driver/touch_sensor_common.c
index 6063dad4bb9..a59ad928c8f 100644
--- a/components/driver/touch_sensor_common.c
+++ b/components/driver/touch_sensor_common.c
@@ -18,6 +18,7 @@
 #include "esp_types.h"
 #include "esp_log.h"
 #include "sys/lock.h"
+#include "soc/soc_pins.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/xtensa_api.h"
 #include "freertos/semphr.h"
diff --git a/components/driver/twai.c b/components/driver/twai.c
index 984d373d1d7..c56c1b776be 100644
--- a/components/driver/twai.c
+++ b/components/driver/twai.c
@@ -373,9 +373,9 @@ esp_err_t twai_driver_install(const twai_general_config_t *g_config, const twai_
     TWAI_CHECK(g_config->tx_io >= 0 && g_config->tx_io < GPIO_NUM_MAX, ESP_ERR_INVALID_ARG);
     TWAI_CHECK(g_config->rx_io >= 0 && g_config->rx_io < GPIO_NUM_MAX, ESP_ERR_INVALID_ARG);
 #if (CONFIG_ESP32_REV_MIN >= 2)
-    TWAI_CHECK(t_config->brp >= TWAI_BRP_MIN && t_config->brp <= TWAI_BRP_MAX_ECO, ESP_ERR_INVALID_ARG);
+    TWAI_CHECK(t_config->brp >= SOC_TWAI_BRP_MIN && t_config->brp <= SOC_TWAI_BRP_MAX_ECO, ESP_ERR_INVALID_ARG);
 #else
-    TWAI_CHECK(t_config->brp >= TWAI_BRP_MIN && t_config->brp <= TWAI_BRP_MAX, ESP_ERR_INVALID_ARG);
+    TWAI_CHECK(t_config->brp >= SOC_TWAI_BRP_MIN && t_config->brp <= SOC_TWAI_BRP_MAX, ESP_ERR_INVALID_ARG);
 #endif
 #ifndef CONFIG_TWAI_ISR_IN_IRAM
     TWAI_CHECK(!(g_config->intr_flags & ESP_INTR_FLAG_IRAM), ESP_ERR_INVALID_ARG);
diff --git a/components/driver/uart.c b/components/driver/uart.c
index 81a85a263bb..47a4081e66c 100644
--- a/components/driver/uart.c
+++ b/components/driver/uart.c
@@ -61,7 +61,7 @@ static const char* UART_TAG = "uart";
 #define UART_CLKDIV_FRAG_BIT_WIDTH      (3)
 #define UART_TX_IDLE_NUM_DEFAULT        (0)
 #define UART_PATTERN_DET_QLEN_DEFAULT   (10)
-#define UART_MIN_WAKEUP_THRESH          (SOC_UART_MIN_WAKEUP_THRESH)
+#define UART_MIN_WAKEUP_THRESH          (UART_LL_MIN_WAKEUP_THRESH)
 
 #define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \
                             | (UART_INTR_RXFIFO_TOUT) \
@@ -118,7 +118,7 @@ typedef struct {
     int rx_cur_remain;                  /*!< Data number that waiting to be read out in ring buffer item*/
     uint8_t* rx_ptr;                    /*!< pointer to the current data in ring buffer*/
     uint8_t* rx_head_ptr;               /*!< pointer to the head of RX item*/
-    uint8_t rx_data_buf[UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
+    uint8_t rx_data_buf[SOC_UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
     uint8_t rx_stash_len;               /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */
     uart_pat_rb_t rx_pattern_pos;
 
@@ -265,8 +265,8 @@ esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask)
 esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable,  uint8_t rx_thresh_xon,  uint8_t rx_thresh_xoff)
 {
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
-    UART_CHECK((rx_thresh_xon < UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL);
-    UART_CHECK((rx_thresh_xoff < UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL);
+    UART_CHECK((rx_thresh_xon < SOC_UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL);
+    UART_CHECK((rx_thresh_xoff < SOC_UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL);
     uart_sw_flowctrl_t sw_flow_ctl = {
         .xon_char = XON,
         .xoff_char = XOFF,
@@ -282,7 +282,7 @@ esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable,  uint8_t rx_t
 esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh)
 {
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
-    UART_CHECK((rx_thresh < UART_FIFO_LEN), "rx flow thresh error", ESP_FAIL);
+    UART_CHECK((rx_thresh < SOC_UART_FIFO_LEN), "rx flow thresh error", ESP_FAIL);
     UART_CHECK((flow_ctrl < UART_HW_FLOWCTRL_MAX), "hw_flowctrl mode error", ESP_FAIL);
     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
     uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), flow_ctrl, rx_thresh);
@@ -522,7 +522,7 @@ esp_err_t uart_disable_tx_intr(uart_port_t uart_num)
 esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh)
 {
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
-    UART_CHECK((thresh < UART_FIFO_LEN), "empty intr threshold error", ESP_FAIL);
+    UART_CHECK((thresh < SOC_UART_FIFO_LEN), "empty intr threshold error", ESP_FAIL);
     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
     uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), thresh);
@@ -622,7 +622,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
 {
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
     UART_CHECK((uart_config), "param null", ESP_FAIL);
-    UART_CHECK((uart_config->rx_flow_ctrl_thresh < UART_FIFO_LEN), "rx flow thresh error", ESP_FAIL);
+    UART_CHECK((uart_config->rx_flow_ctrl_thresh < SOC_UART_FIFO_LEN), "rx flow thresh error", ESP_FAIL);
     UART_CHECK((uart_config->flow_ctrl < UART_HW_FLOWCTRL_MAX), "hw_flowctrl mode error", ESP_FAIL);
     UART_CHECK((uart_config->data_bits < UART_DATA_BITS_MAX), "data bit error", ESP_FAIL);
     uart_module_enable(uart_num);
@@ -644,7 +644,7 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_
 {
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
     UART_CHECK((intr_conf), "param null", ESP_FAIL);
-    uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_MASK);
+    uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
     if(intr_conf->intr_enable_mask & UART_INTR_RXFIFO_TOUT) {
         uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), intr_conf->rx_timeout_thresh);
@@ -962,7 +962,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
                 // then postpone interrupt processing for next interrupt
                 uart_event.type = UART_EVENT_MAX;
             } else {
-                // Workaround for RS485: If the RS485 half duplex mode is active 
+                // Workaround for RS485: If the RS485 half duplex mode is active
                 // and transmitter is in idle state then reset received buffer and reset RTS pin
                 // skip this behavior for other UART modes
                 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
@@ -1281,8 +1281,8 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
 {
     esp_err_t r;
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
-    UART_CHECK((rx_buffer_size > UART_FIFO_LEN), "uart rx buffer length error", ESP_FAIL);
-    UART_CHECK((tx_buffer_size > UART_FIFO_LEN) || (tx_buffer_size == 0), "uart tx buffer length error", ESP_FAIL);
+    UART_CHECK((rx_buffer_size > SOC_UART_FIFO_LEN), "uart rx buffer length error", ESP_FAIL);
+    UART_CHECK((tx_buffer_size > SOC_UART_FIFO_LEN) || (tx_buffer_size == 0), "uart tx buffer length error", ESP_FAIL);
 #if CONFIG_UART_ISR_IN_IRAM
     if ((intr_alloc_flags & ESP_INTR_FLAG_IRAM) == 0) {
         ESP_LOGI(UART_TAG, "ESP_INTR_FLAG_IRAM flag not set while CONFIG_UART_ISR_IN_IRAM is enabled, flag updated");
@@ -1354,8 +1354,8 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
         .txfifo_empty_intr_thresh = UART_EMPTY_THRESH_DEFAULT,
     };
     uart_module_enable(uart_num);
-    uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_MASK);
-    uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_MASK);
+    uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
+    uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
     r=uart_isr_register(uart_num, uart_rx_intr_handler_default, p_uart_obj[uart_num], intr_alloc_flags, &p_uart_obj[uart_num]->intr_handle);
     if (r!=ESP_OK) goto err;
     r=uart_intr_config(uart_num, &uart_intr);
diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c
index 07269ac2ec7..a94883d9868 100644
--- a/components/esp32/spiram_psram.c
+++ b/components/esp32/spiram_psram.c
@@ -31,7 +31,7 @@
 #include "esp_rom_efuse.h"
 #include "soc/dport_reg.h"
 #include "soc/efuse_periph.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "driver/gpio.h"
 #include "driver/spi_common_internal.h"
 #include "driver/periph_ctrl.h"
@@ -972,7 +972,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
         ESP_EARLY_LOGE(TAG, "PSRAM 2T mode and SPIRAM bank switching can not enabled meanwhile. Please read the help text for SPIRAM_2T_MODE in the project configuration menu.");
         abort();
 #endif
-        /* Note: 2T mode command should not be sent twice, 
+        /* Note: 2T mode command should not be sent twice,
            otherwise psram would get back to normal mode. */
         if (psram_2t_mode_check(PSRAM_SPI_1) != ESP_OK) {
             psram_2t_mode_enable(PSRAM_SPI_1);
diff --git a/components/esp32s2/spiram_psram.c b/components/esp32s2/spiram_psram.c
index 959f5335d3d..a467bb1c068 100644
--- a/components/esp32s2/spiram_psram.c
+++ b/components/esp32s2/spiram_psram.c
@@ -31,7 +31,7 @@
 #include "esp_rom_efuse.h"
 #include "soc/dport_reg.h"
 #include "soc/efuse_periph.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "soc/io_mux_reg.h"
 #include "soc/apb_ctrl_reg.h"
 #include "soc/efuse_reg.h"
@@ -61,7 +61,7 @@ static const char* TAG = "psram";
 #define PSRAM_RESET                0x99
 #define PSRAM_SET_BURST_LEN        0xC0
 #define PSRAM_DEVICE_ID            0x9F
-// ID 
+// ID
 #define PSRAM_ID_KGD_M          0xff
 #define PSRAM_ID_KGD_S             8
 #define PSRAM_ID_KGD            0x5d
@@ -215,7 +215,7 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
     _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
         dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
     esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
-    
+
     WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
     WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
     WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
diff --git a/components/esp32s3/spiram_psram.c b/components/esp32s3/spiram_psram.c
index cdc2089a8c4..6674e01686d 100644
--- a/components/esp32s3/spiram_psram.c
+++ b/components/esp32s3/spiram_psram.c
@@ -32,7 +32,7 @@
 #include "esp_rom_efuse.h"
 #include "soc/dport_reg.h"
 #include "soc/efuse_periph.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "soc/io_mux_reg.h"
 #include "soc/apb_ctrl_reg.h"
 #include "soc/efuse_reg.h"
diff --git a/components/esp_common/include/esp_bit_defs.h b/components/esp_common/include/esp_bit_defs.h
index d9d464e2ce1..6c1600b69bc 100644
--- a/components/esp_common/include/esp_bit_defs.h
+++ b/components/esp_common/include/esp_bit_defs.h
@@ -49,6 +49,39 @@
 #define BIT0     0x00000001
 //}}
 
+#define BIT63    (0x80000000ULL << 32)
+#define BIT62    (0x40000000ULL << 32)
+#define BIT61    (0x20000000ULL << 32)
+#define BIT60    (0x10000000ULL << 32)
+#define BIT59    (0x08000000ULL << 32)
+#define BIT58    (0x04000000ULL << 32)
+#define BIT57    (0x02000000ULL << 32)
+#define BIT56    (0x01000000ULL << 32)
+#define BIT55    (0x00800000ULL << 32)
+#define BIT54    (0x00400000ULL << 32)
+#define BIT53    (0x00200000ULL << 32)
+#define BIT52    (0x00100000ULL << 32)
+#define BIT51    (0x00080000ULL << 32)
+#define BIT50    (0x00040000ULL << 32)
+#define BIT49    (0x00020000ULL << 32)
+#define BIT48    (0x00010000ULL << 32)
+#define BIT47    (0x00008000ULL << 32)
+#define BIT46    (0x00004000ULL << 32)
+#define BIT45    (0x00002000ULL << 32)
+#define BIT44    (0x00001000ULL << 32)
+#define BIT43    (0x00000800ULL << 32)
+#define BIT42    (0x00000400ULL << 32)
+#define BIT41    (0x00000200ULL << 32)
+#define BIT40    (0x00000100ULL << 32)
+#define BIT39    (0x00000080ULL << 32)
+#define BIT38    (0x00000040ULL << 32)
+#define BIT37    (0x00000020ULL << 32)
+#define BIT36    (0x00000010ULL << 32)
+#define BIT35    (0x00000008ULL << 32)
+#define BIT34    (0x00000004ULL << 32)
+#define BIT33    (0x00000002ULL << 32)
+#define BIT32    (0x00000001ULL << 32)
+
 #ifndef __ASSEMBLER__
 #ifndef BIT
 #define BIT(nr)                 (1UL << (nr))
diff --git a/components/esp_rom/include/esp32/rom/gpio.h b/components/esp_rom/include/esp32/rom/gpio.h
index d9b3c298553..ef6e3c512a7 100644
--- a/components/esp_rom/include/esp32/rom/gpio.h
+++ b/components/esp_rom/include/esp32/rom/gpio.h
@@ -24,7 +24,7 @@
 
 #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
 #include "soc/gpio_reg.h"
-#include "soc/gpio_caps.h"
+#include "soc/soc_caps.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/components/esp_rom/include/esp_rom_gpio.h b/components/esp_rom/include/esp_rom_gpio.h
index fc5f0d22ae6..ce4bb765168 100644
--- a/components/esp_rom/include/esp_rom_gpio.h
+++ b/components/esp_rom/include/esp_rom_gpio.h
@@ -20,6 +20,7 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "soc/gpio_pins.h"  //for GPIO_MATRIX_CONST_ONE_INPUT, GPIO_MATRIX_CONST_ZERO_INPUT
 
 /**
  * @brief Configure IO Pad as General Purpose IO,
diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c
index ea264197280..4a22c2486f8 100644
--- a/components/esp_system/sleep_modes.c
+++ b/components/esp_system/sleep_modes.c
@@ -32,7 +32,7 @@
 #include "soc/cpu.h"
 #include "soc/rtc.h"
 #include "soc/dport_reg.h"
-#include "soc/uart_caps.h"
+#include "soc/soc_caps.h"
 
 #include "hal/wdt_hal.h"
 #include "hal/rtc_io_hal.h"
@@ -587,7 +587,7 @@ static void touch_wakeup_prepare(void)
 {
     touch_pad_sleep_channel_t slp_config;
     touch_pad_fsm_stop();
-    touch_pad_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_pad_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
     touch_pad_sleep_channel_get_info(&slp_config);
     touch_pad_set_channel_mask(BIT(slp_config.touch_num));
     touch_pad_fsm_start();
diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c
index f1d08100d71..b2fa310e094 100644
--- a/components/hal/adc_hal.c
+++ b/components/hal/adc_hal.c
@@ -13,6 +13,7 @@
 // limitations under the License.
 
 #include "hal/adc_hal.h"
+#include "hal/adc_hal_conf.h"
 
 void adc_hal_init(void)
 {
diff --git a/components/hal/cpu_hal.c b/components/hal/cpu_hal.c
index 8873d1271d7..8d98ebf665a 100644
--- a/components/hal/cpu_hal.c
+++ b/components/hal/cpu_hal.c
@@ -21,7 +21,7 @@
 #include "hal/cpu_hal.h"
 #include "hal/cpu_types.h"
 
-#include "soc/cpu_caps.h"
+#include "soc/soc_caps.h"
 
 
 #if SOC_CPU_BREAKPOINTS_NUM > 0
diff --git a/components/hal/esp32/adc_hal.c b/components/hal/esp32/adc_hal.c
index 8a066314016..a772b822016 100644
--- a/components/hal/esp32/adc_hal.c
+++ b/components/hal/esp32/adc_hal.c
@@ -15,6 +15,7 @@
 // The HAL layer for ADC (common part)
 
 #include "hal/adc_hal.h"
+#include "hal/adc_hal_conf.h"
 #include "hal/adc_types.h"
 
 void adc_hal_digi_init(void)
diff --git a/components/hal/esp32/include/hal/adc_hal_conf.h b/components/hal/esp32/include/hal/adc_hal_conf.h
new file mode 100644
index 00000000000..dd0e64dfef7
--- /dev/null
+++ b/components/hal/esp32/include/hal/adc_hal_conf.h
@@ -0,0 +1,31 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_ADC1_DATA_INVERT_DEFAULT    (1)
+#define SOC_ADC2_DATA_INVERT_DEFAULT    (1)
+
+#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
+
+#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
+#define SOC_ADC_FSM_START_WAIT_DEFAULT      (SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT)
+#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
+#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (2)
+
+#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
+
+#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
+
+#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT    (16)
\ No newline at end of file
diff --git a/components/hal/esp32/include/hal/can_types.h b/components/hal/esp32/include/hal/can_types.h
index 2c65d2130f9..4af81894f43 100644
--- a/components/hal/esp32/include/hal/can_types.h
+++ b/components/hal/esp32/include/hal/can_types.h
@@ -38,7 +38,7 @@ extern "C" {
 #define CAN_MSG_FLAG_SELF               TWAI_MSG_FLAG_SELF
 #define CAN_MSG_FLAG_DLC_NON_COMP       TWAI_MSG_FLAG_DLC_NON_COMP
 
-#if (TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
+#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
 #define CAN_TIMING_CONFIG_12_5KBITS()   TWAI_TIMING_CONFIG_12_5KBITS()
 #define CAN_TIMING_CONFIG_16KBITS()     TWAI_TIMING_CONFIG_16KBITS()
 #define CAN_TIMING_CONFIG_20KBITS()     TWAI_TIMING_CONFIG_20KBITS()
diff --git a/components/hal/esp32/include/hal/cpu_ll.h b/components/hal/esp32/include/hal/cpu_ll.h
index 8034dbf1a43..121e5791859 100644
--- a/components/hal/esp32/include/hal/cpu_ll.h
+++ b/components/hal/esp32/include/hal/cpu_ll.h
@@ -17,7 +17,7 @@
 
 #include "esp_attr.h"
 
-#include "soc/cpu_caps.h"
+#include "soc/soc_caps.h"
 
 #include "xt_instr_macros.h"
 #include "xtensa/config/specreg.h"
diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h
index d428fb3eab2..289be9849c7 100644
--- a/components/hal/esp32/include/hal/gpio_ll.h
+++ b/components/hal/esp32/include/hal/gpio_ll.h
@@ -35,6 +35,12 @@ extern "C" {
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
 
+#define GPIO_LL_APP_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_APP_CPU_NMI_INTR_ENA  (BIT(1))
+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(2))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(3))
+#define GPIO_LL_SDIO_EXT_INTR_ENA     (BIT(4))
+
 /**
   * @brief Enable pull-up on GPIO.
   *
@@ -147,9 +153,9 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
     if (core_id == 0) {
-        hw->pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+        hw->pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
     } else {
-        hw->pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA;     //enable pro cpu intr
+        hw->pin[gpio_num].int_ena = GPIO_LL_APP_CPU_INTR_ENA;     //enable pro cpu intr
     }
 }
 
diff --git a/components/hal/esp32/include/hal/i2c_ll.h b/components/hal/esp32/include/hal/i2c_ll.h
index a670a66d83f..7795c8cf722 100644
--- a/components/hal/esp32/include/hal/i2c_ll.h
+++ b/components/hal/esp32/include/hal/i2c_ll.h
@@ -22,6 +22,8 @@
 extern "C" {
 #endif
 
+#define I2C_LL_INTR_MASK          (0x3fff) /*!< I2C all interrupt bitmap */
+
 /**
  * @brief I2C hardware cmd register filed.
  */
@@ -42,7 +44,7 @@ typedef union {
  * @brief I2C interrupt event
  */
 typedef enum {
-    I2C_INTR_EVENT_ERR,        
+    I2C_INTR_EVENT_ERR,
     I2C_INTR_EVENT_ARBIT_LOST,   /*!< I2C arbition lost event */
     I2C_INTR_EVENT_NACK,         /*!< I2C NACK event */
     I2C_INTR_EVENT_TOUT,         /*!< I2C time out event */
@@ -329,7 +331,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
  */
 static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 {
-    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;    
+    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;
 }
 
 /**
@@ -342,7 +344,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
  */
 static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
 {
-    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;    
+    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;
 }
 
 /**
@@ -533,7 +535,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
     uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
     for(int i = 0; i < len; i++) {
         WRITE_PERI_REG(fifo_addr, ptr[i]);
-    }   
+    }
 }
 
 /**
@@ -549,7 +551,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for(int i = 0; i < len; i++) {
         ptr[i] = hw->fifo_data.data;
-    }   
+    }
 }
 
 /**
diff --git a/components/hal/esp32/include/hal/mcpwm_ll.h b/components/hal/esp32/include/hal/mcpwm_ll.h
index 6be08f26bef..d31a810b2f8 100644
--- a/components/hal/esp32/include/hal/mcpwm_ll.h
+++ b/components/hal/esp32/include/hal/mcpwm_ll.h
@@ -22,10 +22,10 @@
 
 #pragma once
 
+#include "soc/soc_caps.h"
 #include <soc/mcpwm_periph.h>
 #include "soc/mcpwm_periph.h"
 #include "hal/mcpwm_types.h"
-#include "soc/mcpwm_caps.h"
 #include "hal/hal_defs.h"
 
 #include "esp_types.h"
diff --git a/components/hal/esp32/include/hal/mpu_ll.h b/components/hal/esp32/include/hal/mpu_ll.h
index bb849f66a95..08c230cdfc1 100644
--- a/components/hal/esp32/include/hal/mpu_ll.h
+++ b/components/hal/esp32/include/hal/mpu_ll.h
@@ -14,7 +14,7 @@
 
 #include <stdint.h>
 
-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"
 
 #include "xt_instr_macros.h"
 
diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h
index 5cc30ca56ca..ebae2587d86 100644
--- a/components/hal/esp32/include/hal/rmt_ll.h
+++ b/components/hal/esp32/include/hal/rmt_ll.h
@@ -19,7 +19,7 @@ extern "C" {
 
 #include <stdbool.h>
 #include "soc/rmt_struct.h"
-#include "soc/rmt_caps.h"
+#include "soc/soc_caps.h"
 
 #define RMT_LL_HW_BASE  (&RMT)
 #define RMT_LL_MEM_BASE (&RMTMEM)
diff --git a/components/hal/esp32/include/hal/rtc_io_ll.h b/components/hal/esp32/include/hal/rtc_io_ll.h
index 9162464a1aa..284e1f3ac11 100644
--- a/components/hal/esp32/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32/include/hal/rtc_io_ll.h
@@ -25,6 +25,8 @@
 #include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"
 
+#define RTCIO_LL_PIN_FUNC     0
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -58,7 +60,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
         SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
         //0:RTC FUNCTION 1,2,3:Reserved
-        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func);
+        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
     } else if (func == RTCIO_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
     }
diff --git a/components/hal/esp32/include/hal/touch_sensor_ll.h b/components/hal/esp32/include/hal/touch_sensor_ll.h
index 4016d4f566f..b65120b684a 100644
--- a/components/hal/esp32/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32/include/hal/touch_sensor_ll.h
@@ -62,7 +62,7 @@ static inline void touch_ll_set_meas_time(uint16_t meas_time)
     //touch sensor measure time= meas_cycle / 8Mhz
     SENS.sar_touch_ctrl1.touch_meas_delay = meas_time;
     //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT;
+    SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX;
 }
 
 /**
diff --git a/components/hal/esp32/include/hal/twai_ll.h b/components/hal/esp32/include/hal/twai_ll.h
index c02d2388f65..e04e4c0786a 100644
--- a/components/hal/esp32/include/hal/twai_ll.h
+++ b/components/hal/esp32/include/hal/twai_ll.h
@@ -331,7 +331,7 @@ static inline uint32_t twai_ll_get_and_clear_intrs(twai_dev_t *hw)
  */
 static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
 {
-#if (CONFIG_ESP32_REV_MIN >= 2)
+#if TWAI_BRP_DIV_SUPPORTED
     //ESP32 Rev 2 or later has brp div field. Need to mask it out
     hw->interrupt_enable_reg.val = (hw->interrupt_enable_reg.val & 0x10) | intr_mask;
 #else
@@ -357,8 +357,8 @@ static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
  */
 static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling)
 {
-#if (CONFIG_ESP32_REV_MIN >= 2)
-    if (brp > TWAI_BRP_DIV_THRESH) {
+#if TWAI_BRP_DIV_SUPPORTED
+    if (brp > SOC_TWAI_BRP_DIV_THRESH) {
         //Need to set brp_div bit
         hw->interrupt_enable_reg.brp_div = 1;
         brp /= 2;
diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h
index a6997d9f3f2..905c149c481 100644
--- a/components/hal/esp32/include/hal/uart_ll.h
+++ b/components/hal/esp32/include/hal/uart_ll.h
@@ -17,21 +17,24 @@
 
 
 #pragma once
-#include "hal/uart_types.h"
 #include "soc/uart_periph.h"
+#include "hal/uart_types.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 // The default fifo depth
-#define UART_LL_FIFO_DEF_LEN  (UART_FIFO_LEN)
+#define UART_LL_FIFO_DEF_LEN  (SOC_UART_FIFO_LEN)
 // Get UART hardware instance with giving uart num
 #define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (((num) == 1) ? (&UART1) : (&UART2)))
 
 // The timeout calibration factor when using ref_tick
 #define UART_LL_TOUT_REF_FACTOR_DEFAULT (8)
 
+#define UART_LL_MIN_WAKEUP_THRESH (2)
+#define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
+
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1<<0),
@@ -250,8 +253,8 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
     uint32_t fifo_cnt = hw->status.rxfifo_cnt;
     typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status;
     uint32_t len = 0;
-    
-    // When using DPort to read fifo, fifo_cnt is not credible, we need to calculate the real cnt based on the fifo read and write pointer. 
+
+    // When using DPort to read fifo, fifo_cnt is not credible, we need to calculate the real cnt based on the fifo read and write pointer.
     // When using AHB to read FIFO, we can use fifo_cnt to indicate the data length in fifo.
     if (rx_status.wr_addr > rx_status.rd_addr) {
         len = rx_status.wr_addr - rx_status.rd_addr;
@@ -286,12 +289,12 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
  */
 static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
 {
-    //workaround for hardware issue, when UART stop bit set as 2-bit mode. 
+    //workaround for hardware issue, when UART stop bit set as 2-bit mode.
     if(stop_bit == UART_STOP_BITS_2)  {
         hw->rs485_conf.dl1_en = 1;
         hw->conf0.stop_bit_num = 0x1;
     } else {
-        hw->rs485_conf.dl1_en = 0;   
+        hw->rs485_conf.dl1_en = 0;
         hw->conf0.stop_bit_num = stop_bit;
     }
 }
@@ -306,7 +309,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
  */
 static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
 {
-    //workaround for hardware issue, when UART stop bit set as 2-bit mode. 
+    //workaround for hardware issue, when UART stop bit set as 2-bit mode.
     if(hw->rs485_conf.dl1_en == 1 && hw->conf0.stop_bit_num == 0x1) {
         *stop_bit = UART_STOP_BITS_2;
     } else {
@@ -573,7 +576,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
  */
 static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
 {
-    hw->sleep_conf.active_threshold = wakeup_thrd  - SOC_UART_MIN_WAKEUP_THRESH;
+    hw->sleep_conf.active_threshold = wakeup_thrd  - UART_LL_MIN_WAKEUP_THRESH;
 }
 
 /**
@@ -715,7 +718,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
  */
 static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
 {
-    return hw->sleep_conf.active_threshold + SOC_UART_MIN_WAKEUP_THRESH;
+    return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
 }
 
 /**
diff --git a/components/hal/esp32/touch_sensor_hal.c b/components/hal/esp32/touch_sensor_hal.c
index 49ecdcff760..38d71c12548 100644
--- a/components/hal/esp32/touch_sensor_hal.c
+++ b/components/hal/esp32/touch_sensor_hal.c
@@ -20,8 +20,8 @@
 void touch_hal_init(void)
 {
     touch_ll_intr_disable();
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    touch_ll_clear_group_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX, SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
+    touch_ll_clear_group_mask(TOUCH_PAD_BIT_MASK_ALL, TOUCH_PAD_BIT_MASK_ALL);
     touch_ll_set_trigger_mode(TOUCH_TRIGGER_MODE_DEFAULT);
     touch_ll_set_trigger_source(TOUCH_TRIGGER_SOURCE_DEFAULT);
     touch_ll_clear_trigger_status_mask();
diff --git a/components/hal/esp32s2/adc_hal.c b/components/hal/esp32s2/adc_hal.c
index bd4029860cb..5f3e3d2a48f 100644
--- a/components/hal/esp32s2/adc_hal.c
+++ b/components/hal/esp32s2/adc_hal.c
@@ -16,6 +16,7 @@
 
 #include "hal/adc_hal.h"
 #include "hal/adc_types.h"
+#include "hal/adc_hal_conf.h"
 
 /*---------------------------------------------------------------
                     Digital controller setting
diff --git a/components/hal/esp32s2/cp_dma_hal.c b/components/hal/esp32s2/cp_dma_hal.c
index 38995f380a7..c841cc518a5 100644
--- a/components/hal/esp32s2/cp_dma_hal.c
+++ b/components/hal/esp32s2/cp_dma_hal.c
@@ -12,6 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+#include "soc/soc_caps.h"
 #include "hal/cp_dma_hal.h"
 #include "hal/cp_dma_ll.h"
 
diff --git a/components/soc/soc/esp32/include/soc/cpu_caps.h b/components/hal/esp32s2/include/hal/adc_hal_conf.h
similarity index 55%
rename from components/soc/soc/esp32/include/soc/cpu_caps.h
rename to components/hal/esp32s2/include/hal/adc_hal_conf.h
index fbfd780bd49..2a219911d8d 100644
--- a/components/soc/soc/esp32/include/soc/cpu_caps.h
+++ b/components/hal/esp32s2/include/hal/adc_hal_conf.h
@@ -14,7 +14,18 @@
 
 #pragma once
 
-#define SOC_CPU_BREAKPOINTS_NUM         2
-#define SOC_CPU_WATCHPOINTS_NUM         2
+#define SOC_ADC1_DATA_INVERT_DEFAULT    (0)
+#define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
 
-#define SOC_CPU_WATCHPOINT_SIZE         64 // bytes
\ No newline at end of file
+#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
+
+#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
+#define SOC_ADC_FSM_START_WAIT_DEFAULT      (5)
+#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
+#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (3)
+
+#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
+
+#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
+
+#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT    (2)
\ No newline at end of file
diff --git a/components/hal/esp32s2/include/hal/cpu_ll.h b/components/hal/esp32s2/include/hal/cpu_ll.h
index 4e8a2e38131..f0a6df04fb2 100644
--- a/components/hal/esp32s2/include/hal/cpu_ll.h
+++ b/components/hal/esp32s2/include/hal/cpu_ll.h
@@ -16,7 +16,7 @@
 
 #include "esp_attr.h"
 
-#include "soc/cpu_caps.h"
+#include "soc/soc_caps.h"
 
 #include "xt_instr_macros.h"
 #include "xtensa/config/specreg.h"
diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h
index 9fa745d8c97..5eae452f8e5 100644
--- a/components/hal/esp32s2/include/hal/gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/gpio_ll.h
@@ -35,6 +35,9 @@ extern "C" {
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
 
+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+
 /**
   * @brief Enable pull-up on GPIO.
   *
@@ -147,7 +150,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
     if (core_id == 0) {
-        GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+        GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
     }
 }
 
diff --git a/components/hal/esp32s2/include/hal/i2c_ll.h b/components/hal/esp32s2/include/hal/i2c_ll.h
index 66a375ae1ef..7ec14e70033 100644
--- a/components/hal/esp32s2/include/hal/i2c_ll.h
+++ b/components/hal/esp32s2/include/hal/i2c_ll.h
@@ -22,6 +22,8 @@
 extern "C" {
 #endif
 
+#define I2C_LL_INTR_MASK          (0x1ffff) /*!< I2C all interrupt bitmap */
+
 /**
  * @brief I2C hardware cmd register filed.
  */
@@ -42,7 +44,7 @@ typedef union {
  * @brief I2C interrupt event
  */
 typedef enum {
-    I2C_INTR_EVENT_ERR,        
+    I2C_INTR_EVENT_ERR,
     I2C_INTR_EVENT_ARBIT_LOST,   /*!< I2C arbition lost event */
     I2C_INTR_EVENT_NACK,         /*!< I2C NACK event */
     I2C_INTR_EVENT_TOUT,         /*!< I2C time out event */
@@ -540,7 +542,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
     uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
     for(int i = 0; i < len; i++) {
         WRITE_PERI_REG(fifo_addr, ptr[i]);
-    }   
+    }
 }
 
 /**
@@ -557,7 +559,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
     uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
     for(int i = 0; i < len; i++) {
         ptr[i] = READ_PERI_REG(fifo_addr);
-    }   
+    }
 }
 
 /**
diff --git a/components/hal/esp32s2/include/hal/mpu_ll.h b/components/hal/esp32s2/include/hal/mpu_ll.h
index bb849f66a95..08c230cdfc1 100644
--- a/components/hal/esp32s2/include/hal/mpu_ll.h
+++ b/components/hal/esp32s2/include/hal/mpu_ll.h
@@ -14,7 +14,7 @@
 
 #include <stdint.h>
 
-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"
 
 #include "xt_instr_macros.h"
 
diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h
index bda304f5e80..a79db2c6cbf 100644
--- a/components/hal/esp32s2/include/hal/rmt_ll.h
+++ b/components/hal/esp32s2/include/hal/rmt_ll.h
@@ -18,8 +18,8 @@ extern "C" {
 #endif
 
 #include <stdbool.h>
+#include "soc/soc_caps.h"
 #include "soc/rmt_struct.h"
-#include "soc/rmt_caps.h"
 
 #define RMT_LL_HW_BASE  (&RMT)
 #define RMT_LL_MEM_BASE (&RMTMEM)
diff --git a/components/hal/esp32s2/include/hal/rtc_io_ll.h b/components/hal/esp32s2/include/hal/rtc_io_ll.h
index 82b67ea8343..65bfe92a2ef 100644
--- a/components/hal/esp32s2/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32s2/include/hal/rtc_io_ll.h
@@ -25,6 +25,8 @@
 #include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"
 
+#define RTCIO_LL_PIN_FUNC     0
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -59,7 +61,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
         SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
         //0:RTC FUNCTION 1,2,3:Reserved
-        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func);
+        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
     } else if (func == RTCIO_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
         SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
diff --git a/components/hal/esp32s2/include/hal/touch_sensor_ll.h b/components/hal/esp32s2/include/hal/touch_sensor_ll.h
index a287a07c782..4b7137c271f 100644
--- a/components/hal/esp32s2/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32s2/include/hal/touch_sensor_ll.h
@@ -48,7 +48,7 @@ static inline void touch_ll_set_meas_times(uint16_t meas_time)
     //The times of charge and discharge in each measure process of touch channels.
     RTCCNTL.touch_ctrl1.touch_meas_num = meas_time;
     //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT; //wait volt stable
+    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX; //wait volt stable
 }
 
 /**
@@ -345,8 +345,8 @@ static inline void touch_ll_get_threshold(touch_pad_t touch_num, uint32_t *thres
  */
 static inline void touch_ll_set_channel_mask(uint16_t enable_mask)
 {
-    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  |= (enable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    SENS.sar_touch_conf.touch_outen |= (enable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  |= (enable_mask & TOUCH_PAD_BIT_MASK_ALL);
+    SENS.sar_touch_conf.touch_outen |= (enable_mask & TOUCH_PAD_BIT_MASK_ALL);
 }
 
 /**
@@ -359,7 +359,7 @@ static inline void touch_ll_get_channel_mask(uint16_t *enable_mask)
 {
     *enable_mask = SENS.sar_touch_conf.touch_outen \
                    & RTCCNTL.touch_scan_ctrl.touch_scan_pad_map \
-                   & SOC_TOUCH_SENSOR_BIT_MASK_MAX;
+                   & TOUCH_PAD_BIT_MASK_ALL;
 }
 
 /**
@@ -370,8 +370,8 @@ static inline void touch_ll_get_channel_mask(uint16_t *enable_mask)
  */
 static inline void touch_ll_clear_channel_mask(uint16_t disable_mask)
 {
-    SENS.sar_touch_conf.touch_outen &= ~(disable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  &= ~(disable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    SENS.sar_touch_conf.touch_outen &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
 }
 
 /**
@@ -659,7 +659,7 @@ static inline void touch_ll_reset_benchmark(touch_pad_t touch_num)
     /* Clear touch channels to initialize the channel value (benchmark, raw_data).
      */
     if (touch_num == TOUCH_PAD_MAX) {
-        SENS.sar_touch_chn_st.touch_channel_clr = SOC_TOUCH_SENSOR_BIT_MASK_MAX;
+        SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_ALL;
     } else {
         SENS.sar_touch_chn_st.touch_channel_clr = (1U << touch_num);
     }
diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h
index 9ab67aacf19..76d20093ecd 100644
--- a/components/hal/esp32s2/include/hal/uart_ll.h
+++ b/components/hal/esp32s2/include/hal/uart_ll.h
@@ -25,10 +25,13 @@ extern "C" {
 #endif
 
 // The default fifo depth
-#define UART_LL_FIFO_DEF_LEN  (UART_FIFO_LEN)
+#define UART_LL_FIFO_DEF_LEN  (SOC_UART_FIFO_LEN)
 // Get UART hardware instance with giving uart num
 #define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))
 
+#define UART_LL_MIN_WAKEUP_THRESH (2)
+#define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
+
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1<<0),
@@ -247,7 +250,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
  * @return None.
  */
 static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
-{ 
+{
     hw->conf0.stop_bit_num = stop_bit;
 }
 
@@ -523,7 +526,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
  */
 static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
 {
-    hw->sleep_conf.active_threshold = wakeup_thrd - SOC_UART_MIN_WAKEUP_THRESH;
+    hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
 }
 
 /**
@@ -665,7 +668,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
  */
 static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
 {
-    return hw->sleep_conf.active_threshold + SOC_UART_MIN_WAKEUP_THRESH;
+    return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
 }
 
 /**
diff --git a/components/hal/esp32s2/systimer_hal.c b/components/hal/esp32s2/systimer_hal.c
index 10d85a2495e..f51580393d9 100644
--- a/components/hal/esp32s2/systimer_hal.c
+++ b/components/hal/esp32s2/systimer_hal.c
@@ -14,10 +14,10 @@
 
 #include <sys/param.h>
 #include <assert.h>
+#include "soc/soc_caps.h"
 #include "hal/systimer_hal.h"
 #include "hal/systimer_ll.h"
 #include "hal/systimer_types.h"
-#include "soc/systimer_caps.h"
 #include "soc/rtc.h"
 
 #define SYSTIMER_TICKS_PER_US (80) // Number of timer ticks per microsecond
diff --git a/components/hal/esp32s2/touch_sensor_hal.c b/components/hal/esp32s2/touch_sensor_hal.c
index 094731890a3..a14d8e46ac3 100644
--- a/components/hal/esp32s2/touch_sensor_hal.c
+++ b/components/hal/esp32s2/touch_sensor_hal.c
@@ -14,13 +14,14 @@
 
 // The HAL layer for Touch Sensor (common part)
 
+#include "soc/soc_pins.h"
 #include "hal/touch_sensor_hal.h"
 #include "hal/touch_sensor_types.h"
 
 void touch_hal_init(void)
 {
     touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
     touch_ll_clear_trigger_status_mask();
     touch_ll_set_meas_times(TOUCH_PAD_MEASURE_CYCLE_DEFAULT);
     touch_ll_set_sleep_time(TOUCH_PAD_SLEEP_CYCLE_DEFAULT);
@@ -41,7 +42,7 @@ void touch_hal_deinit(void)
     touch_ll_sleep_reset_benchmark();
     touch_ll_stop_fsm();
     touch_ll_clkgate(false);
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
     touch_ll_clear_trigger_status_mask();
     touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
     touch_ll_timeout_disable();
diff --git a/components/hal/esp32s3/include/hal/adc_hal_conf.h b/components/hal/esp32s3/include/hal/adc_hal_conf.h
new file mode 100644
index 00000000000..bc4f552c00d
--- /dev/null
+++ b/components/hal/esp32s3/include/hal/adc_hal_conf.h
@@ -0,0 +1,31 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_ADC1_DATA_INVERT_DEFAULT    (0)
+#define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
+
+#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
+
+#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
+#define SOC_ADC_FSM_START_WAIT_DEFAULT      (5)
+#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
+#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (2)
+
+#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
+
+#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
+
+#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT     (1)
\ No newline at end of file
diff --git a/components/hal/esp32s3/include/hal/cpu_ll.h b/components/hal/esp32s3/include/hal/cpu_ll.h
index 180b615c71d..1e4f1c44d28 100644
--- a/components/hal/esp32s3/include/hal/cpu_ll.h
+++ b/components/hal/esp32s3/include/hal/cpu_ll.h
@@ -15,7 +15,7 @@
 
 #include <stdint.h>
 
-#include "soc/cpu_caps.h"
+#include "soc/soc_caps.h"
 
 #include "xt_instr_macros.h"
 #include "xtensa/config/specreg.h"
diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h
index 376f88a3ea5..662f1128756 100644
--- a/components/hal/esp32s3/include/hal/gdma_ll.h
+++ b/components/hal/esp32s3/include/hal/gdma_ll.h
@@ -19,9 +19,9 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "soc/soc_caps.h"
 #include "soc/gdma_struct.h"
 #include "soc/gdma_reg.h"
-#include "soc/gdma_caps.h"
 
 #define GDMA_LL_EVENT_TX_L3_FIFO_UDF (1<<17)
 #define GDMA_LL_EVENT_TX_L3_FIFO_OVF (1<<16)
diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h
index 3a9b48ca0fb..36f91c0ee6e 100644
--- a/components/hal/esp32s3/include/hal/gpio_ll.h
+++ b/components/hal/esp32s3/include/hal/gpio_ll.h
@@ -35,6 +35,9 @@ extern "C" {
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
 
+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+
 /**
   * @brief Enable pull-up on GPIO.
   *
@@ -147,7 +150,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
     if (core_id == 0) {
-        GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+        GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
     }
 }
 
diff --git a/components/hal/esp32s3/include/hal/i2c_ll.h b/components/hal/esp32s3/include/hal/i2c_ll.h
index a670a66d83f..7795c8cf722 100644
--- a/components/hal/esp32s3/include/hal/i2c_ll.h
+++ b/components/hal/esp32s3/include/hal/i2c_ll.h
@@ -22,6 +22,8 @@
 extern "C" {
 #endif
 
+#define I2C_LL_INTR_MASK          (0x3fff) /*!< I2C all interrupt bitmap */
+
 /**
  * @brief I2C hardware cmd register filed.
  */
@@ -42,7 +44,7 @@ typedef union {
  * @brief I2C interrupt event
  */
 typedef enum {
-    I2C_INTR_EVENT_ERR,        
+    I2C_INTR_EVENT_ERR,
     I2C_INTR_EVENT_ARBIT_LOST,   /*!< I2C arbition lost event */
     I2C_INTR_EVENT_NACK,         /*!< I2C NACK event */
     I2C_INTR_EVENT_TOUT,         /*!< I2C time out event */
@@ -329,7 +331,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
  */
 static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 {
-    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;    
+    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;
 }
 
 /**
@@ -342,7 +344,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
  */
 static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
 {
-    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;    
+    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;
 }
 
 /**
@@ -533,7 +535,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
     uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
     for(int i = 0; i < len; i++) {
         WRITE_PERI_REG(fifo_addr, ptr[i]);
-    }   
+    }
 }
 
 /**
@@ -549,7 +551,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for(int i = 0; i < len; i++) {
         ptr[i] = hw->fifo_data.data;
-    }   
+    }
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/mcpwm_ll.h b/components/hal/esp32s3/include/hal/mcpwm_ll.h
index 22c24af75ce..250d1ff7cd4 100644
--- a/components/hal/esp32s3/include/hal/mcpwm_ll.h
+++ b/components/hal/esp32s3/include/hal/mcpwm_ll.h
@@ -22,10 +22,10 @@
 
 #pragma once
 
+#include "soc/soc_caps.h"
 #include <soc/mcpwm_periph.h>
 #include "soc/mcpwm_periph.h"
 #include "hal/mcpwm_types.h"
-#include "soc/mcpwm_caps.h"
 #include "hal/hal_defs.h"
 
 #include "esp_types.h"
diff --git a/components/hal/esp32s3/include/hal/mpu_ll.h b/components/hal/esp32s3/include/hal/mpu_ll.h
index bb849f66a95..08c230cdfc1 100644
--- a/components/hal/esp32s3/include/hal/mpu_ll.h
+++ b/components/hal/esp32s3/include/hal/mpu_ll.h
@@ -14,7 +14,7 @@
 
 #include <stdint.h>
 
-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"
 
 #include "xt_instr_macros.h"
 
diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h
index 779279e3602..7b0c05cbfde 100644
--- a/components/hal/esp32s3/include/hal/rmt_ll.h
+++ b/components/hal/esp32s3/include/hal/rmt_ll.h
@@ -20,7 +20,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/rmt_struct.h"
-#include "soc/rmt_caps.h"
+#include "soc/soc_caps.h"
 
 #define RMT_LL_HW_BASE  (&RMT)
 #define RMT_LL_MEM_BASE (&RMTMEM)
diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/hal/esp32s3/include/hal/rtc_io_ll.h
index d1051d2c04d..2d5c64fe915 100644
--- a/components/hal/esp32s3/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h
@@ -59,7 +59,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
         SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
         //0:RTC FUNCTION 1,2,3:Reserved
-        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func);
+        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
     } else if (func == RTCIO_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
         // SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
diff --git a/components/hal/esp32s3/include/hal/touch_sensor_ll.h b/components/hal/esp32s3/include/hal/touch_sensor_ll.h
index 8c4af7774ca..04c7a5e9d1e 100644
--- a/components/hal/esp32s3/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32s3/include/hal/touch_sensor_ll.h
@@ -48,7 +48,7 @@ static inline void touch_ll_set_meas_times(uint16_t meas_time)
     //The times of charge and discharge in each measure process of touch channels.
     RTCCNTL.touch_ctrl1.touch_meas_num = meas_time;
     //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT; //wait volt stable
+    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX; //wait volt stable
 }
 
 /**
@@ -345,8 +345,8 @@ static inline void touch_ll_get_threshold(touch_pad_t touch_num, uint32_t *thres
  */
 static inline void touch_ll_set_channel_mask(uint16_t enable_mask)
 {
-    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  |= (enable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    SENS.sar_touch_conf.touch_outen |= (enable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  |= (enable_mask & TOUCH_PAD_BIT_MASK_ALL);
+    SENS.sar_touch_conf.touch_outen |= (enable_mask & TOUCH_PAD_BIT_MASK_ALL);
 }
 
 /**
@@ -359,7 +359,7 @@ static inline void touch_ll_get_channel_mask(uint16_t *enable_mask)
 {
     *enable_mask = SENS.sar_touch_conf.touch_outen \
                    & RTCCNTL.touch_scan_ctrl.touch_scan_pad_map \
-                   & SOC_TOUCH_SENSOR_BIT_MASK_MAX;
+                   & TOUCH_PAD_BIT_MASK_ALL;
 }
 
 /**
@@ -370,8 +370,8 @@ static inline void touch_ll_get_channel_mask(uint16_t *enable_mask)
  */
 static inline void touch_ll_clear_channel_mask(uint16_t disable_mask)
 {
-    SENS.sar_touch_conf.touch_outen &= ~(disable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  &= ~(disable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    SENS.sar_touch_conf.touch_outen &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
 }
 
 /**
@@ -659,7 +659,7 @@ static inline void touch_ll_reset_benchmark(touch_pad_t touch_num)
     /* Clear touch channels to initialize the channel value (benchmark, raw_data).
      */
     if (touch_num == TOUCH_PAD_MAX) {
-        SENS.sar_touch_chn_st.touch_channel_clr = SOC_TOUCH_SENSOR_BIT_MASK_MAX;
+        SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_ALL;
     } else {
         SENS.sar_touch_chn_st.touch_channel_clr = (1U << touch_num);
     }
diff --git a/components/hal/esp32s3/include/hal/twai_ll.h b/components/hal/esp32s3/include/hal/twai_ll.h
index 68dae5130e4..f34cd34f811 100644
--- a/components/hal/esp32s3/include/hal/twai_ll.h
+++ b/components/hal/esp32s3/include/hal/twai_ll.h
@@ -363,7 +363,7 @@ static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
 static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling)
 {
 #ifdef TWAI_BRP_DIV_SUPPORTED
-    if (brp > TWAI_BRP_DIV_THRESH) {
+    if (brp > SOC_TWAI_BRP_DIV_THRESH) {
         //Need to set brp_div bit
         hw->interrupt_enable_reg.brp_div = 1;
         brp /= 2;
diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h
index 5908d2b54d4..a3accc04805 100644
--- a/components/hal/esp32s3/include/hal/uart_ll.h
+++ b/components/hal/esp32s3/include/hal/uart_ll.h
@@ -25,10 +25,12 @@ extern "C" {
 #endif
 
 // The default fifo depth
-#define UART_LL_FIFO_DEF_LEN  (UART_FIFO_LEN)
+#define UART_LL_FIFO_DEF_LEN  (SOC_UART_FIFO_LEN)
 // Get UART hardware instance with giving uart num
 #define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))
 
+#define UART_LL_MIN_WAKEUP_THRESH (2)
+#define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 // Define UART interrupts
 typedef enum {
@@ -521,7 +523,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
  */
 static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
 {
-    hw->sleep_conf.active_threshold = wakeup_thrd - SOC_UART_MIN_WAKEUP_THRESH;
+    hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
 }
 
 /**
@@ -663,7 +665,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
  */
 static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
 {
-    return hw->sleep_conf.active_threshold + SOC_UART_MIN_WAKEUP_THRESH;
+    return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
 }
 
 /**
diff --git a/components/hal/esp32s3/systimer_hal.c b/components/hal/esp32s3/systimer_hal.c
index 1f615f8e4f9..10d73e0239d 100644
--- a/components/hal/esp32s3/systimer_hal.c
+++ b/components/hal/esp32s3/systimer_hal.c
@@ -13,10 +13,10 @@
 // limitations under the License.
 
 #include <sys/param.h>
+#include "soc/soc_caps.h"
 #include "hal/systimer_hal.h"
 #include "hal/systimer_ll.h"
 #include "hal/systimer_types.h"
-#include "soc/systimer_caps.h"
 #include "hal/clk_gate_ll.h"
 
 #define SYSTIMER_TICKS_PER_US  (16) // Systimer clock source is fixed to 16MHz
diff --git a/components/hal/esp32s3/touch_sensor_hal.c b/components/hal/esp32s3/touch_sensor_hal.c
index bc5d441491d..4f8f4d85dcc 100644
--- a/components/hal/esp32s3/touch_sensor_hal.c
+++ b/components/hal/esp32s3/touch_sensor_hal.c
@@ -20,7 +20,7 @@
 void touch_hal_init(void)
 {
     touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
     touch_ll_clear_trigger_status_mask();
     touch_ll_set_meas_times(TOUCH_PAD_MEASURE_CYCLE_DEFAULT);
     touch_ll_set_sleep_time(TOUCH_PAD_SLEEP_CYCLE_DEFAULT);
@@ -41,7 +41,7 @@ void touch_hal_deinit(void)
     touch_ll_sleep_reset_benchmark();
     touch_ll_stop_fsm();
     touch_ll_clkgate(false);
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
     touch_ll_clear_trigger_status_mask();
     touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
     touch_ll_timeout_disable();
diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h
index 6606cf9d47b..b6e77b80950 100644
--- a/components/hal/include/hal/adc_types.h
+++ b/components/hal/include/hal/adc_types.h
@@ -16,7 +16,7 @@
 #include <stdbool.h>
 #include <stdint.h>
 #include "sdkconfig.h"
-#include "soc/adc_caps.h"
+#include "soc/soc_caps.h"
 
 /**
  * @brief ADC unit enumeration.
diff --git a/components/hal/include/hal/brownout_hal.h b/components/hal/include/hal/brownout_hal.h
index e2df9459419..b56823b3995 100644
--- a/components/hal/include/hal/brownout_hal.h
+++ b/components/hal/include/hal/brownout_hal.h
@@ -27,7 +27,7 @@ extern "C" {
 #include <stddef.h>
 #include <stdbool.h>
 #include <stdint.h>
-#include "soc/brownout_caps.h"
+#include "soc/soc_caps.h"
 
 typedef struct {
     uint8_t threshold;
diff --git a/components/hal/include/hal/cpu_hal.h b/components/hal/include/hal/cpu_hal.h
index 7584aa40781..fb6be55b30e 100644
--- a/components/hal/include/hal/cpu_hal.h
+++ b/components/hal/include/hal/cpu_hal.h
@@ -19,9 +19,9 @@
 
 #include "esp_err.h"
 
+#include "soc/soc_caps.h"
 #include "hal/cpu_types.h"
 #include "hal/cpu_ll.h"
-#include "soc/cpu_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/include/hal/dac_types.h b/components/hal/include/hal/dac_types.h
index 1adc511a6c8..c693deb6fa8 100644
--- a/components/hal/include/hal/dac_types.h
+++ b/components/hal/include/hal/dac_types.h
@@ -1,6 +1,6 @@
 #pragma once
 
-#include "soc/dac_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/adc_types.h"
 #include "sdkconfig.h"
 
diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h
index ca4249321cc..c013b5de902 100644
--- a/components/hal/include/hal/gpio_hal.h
+++ b/components/hal/include/hal/gpio_hal.h
@@ -319,7 +319,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num);
   */
 #define gpio_hal_iomux_out(hal, gpio_num, func, oen_inv) gpio_ll_iomux_out((hal)->dev, gpio_num, func, oen_inv)
 
-#if GPIO_SUPPORTS_FORCE_HOLD
+#if SOC_GPIO_SUPPORT_FORCE_HOLD
 /**
   * @brief Force hold digital and rtc gpio pad.
   * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h
index 498d4096251..4c5cd227065 100644
--- a/components/hal/include/hal/gpio_types.h
+++ b/components/hal/include/hal/gpio_types.h
@@ -15,7 +15,7 @@
 #pragma once
 
 #include "soc/gpio_periph.h"
-#include "soc/gpio_caps.h"
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -70,7 +70,7 @@ typedef enum {
 #define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
 #define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
 #define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
-#if GPIO_PIN_COUNT > 40
+#if SOC_GPIO_PIN_COUNT > 40
 #define GPIO_SEL_40             ((uint64_t)(((uint64_t)1)<<40))  /*!< Pin 40 selected */
 #define GPIO_SEL_41             ((uint64_t)(((uint64_t)1)<<41))  /*!< Pin 41 selected */
 #define GPIO_SEL_42             ((uint64_t)(((uint64_t)1)<<42))  /*!< Pin 42 selected */
@@ -122,7 +122,7 @@ typedef enum {
 #define GPIO_PIN_REG_37          IO_MUX_GPIO37_REG
 #define GPIO_PIN_REG_38          IO_MUX_GPIO38_REG
 #define GPIO_PIN_REG_39          IO_MUX_GPIO39_REG
-#if GPIO_PIN_COUNT > 40
+#if SOC_GPIO_PIN_COUNT > 40
 #define GPIO_PIN_REG_40          IO_MUX_GPIO40_REG
 #define GPIO_PIN_REG_41          IO_MUX_GPIO41_REG
 #define GPIO_PIN_REG_42          IO_MUX_GPIO42_REG
@@ -179,7 +179,7 @@ typedef enum {
     GPIO_NUM_37 = 37,   /*!< GPIO37, input mode only(ESP32) / input and output(ESP32-S2) */
     GPIO_NUM_38 = 38,   /*!< GPIO38, input mode only(ESP32) / input and output(ESP32-S2) */
     GPIO_NUM_39 = 39,   /*!< GPIO39, input mode only(ESP32) / input and output(ESP32-S2) */
-#if GPIO_PIN_COUNT > 40
+#if SOC_GPIO_PIN_COUNT > 40
     GPIO_NUM_40 = 40,   /*!< GPIO40, input and output */
     GPIO_NUM_41 = 41,   /*!< GPIO41, input and output */
     GPIO_NUM_42 = 42,   /*!< GPIO42, input and output */
@@ -202,6 +202,13 @@ typedef enum {
     GPIO_INTR_MAX,
 } gpio_int_type_t;
 
+/** @cond */
+#define GPIO_MODE_DEF_DISABLE         (0)
+#define GPIO_MODE_DEF_INPUT           (BIT0)    ///< bit mask for input
+#define GPIO_MODE_DEF_OUTPUT          (BIT1)    ///< bit mask for output
+#define GPIO_MODE_DEF_OD              (BIT2)    ///< bit mask for OD mode
+/** @endcond */
+
 typedef enum {
     GPIO_MODE_DISABLE = GPIO_MODE_DEF_DISABLE,                                                         /*!< GPIO mode : disable input and output             */
     GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT,                                                             /*!< GPIO mode : input only                           */
diff --git a/components/hal/include/hal/i2c_types.h b/components/hal/include/hal/i2c_types.h
index 8c30fb32c88..cc1c231e5ad 100644
--- a/components/hal/include/hal/i2c_types.h
+++ b/components/hal/include/hal/i2c_types.h
@@ -20,7 +20,7 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
-#include "soc/i2c_caps.h"
+#include "soc/soc_caps.h"
 
 /**
  * @brief I2C port number, can be I2C_NUM_0 ~ (I2C_NUM_MAX-1).
diff --git a/components/hal/include/hal/i2s_hal.h b/components/hal/include/hal/i2s_hal.h
index 49b3c1a0739..6964bfdf947 100644
--- a/components/hal/include/hal/i2s_hal.h
+++ b/components/hal/include/hal/i2s_hal.h
@@ -24,7 +24,7 @@
 #pragma once
 
 #include "soc/i2s_periph.h"
-#include "soc/i2s_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/i2s_ll.h"
 #include "hal/i2s_types.h"
 
diff --git a/components/hal/include/hal/i2s_types.h b/components/hal/include/hal/i2s_types.h
index 3a70ad19053..1f5b9e0f58c 100644
--- a/components/hal/include/hal/i2s_types.h
+++ b/components/hal/include/hal/i2s_types.h
@@ -17,7 +17,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <stddef.h>
-#include "soc/i2s_caps.h"
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/include/hal/ledc_types.h b/components/hal/include/hal/ledc_types.h
index 9091a1034e9..bc18d59aa24 100644
--- a/components/hal/include/hal/ledc_types.h
+++ b/components/hal/include/hal/ledc_types.h
@@ -20,7 +20,7 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
-#include "soc/ledc_caps.h"
+#include "soc/soc_caps.h"
 
 typedef enum {
 #ifdef SOC_LEDC_SUPPORT_HS_MODE
diff --git a/components/hal/include/hal/rmt_hal.h b/components/hal/include/hal/rmt_hal.h
index 6d44acf940a..8a21ac9dd48 100644
--- a/components/hal/include/hal/rmt_hal.h
+++ b/components/hal/include/hal/rmt_hal.h
@@ -18,8 +18,8 @@ extern "C" {
 #endif
 
 #include <stdint.h>
+#include "soc/soc_caps.h"
 #include "soc/rmt_struct.h"
-#include "soc/rmt_caps.h"
 
 /**
  * @brief HAL context type of RMT driver
diff --git a/components/hal/include/hal/rmt_types.h b/components/hal/include/hal/rmt_types.h
index 3f8b1b6b2e1..37d79ea224d 100644
--- a/components/hal/include/hal/rmt_types.h
+++ b/components/hal/include/hal/rmt_types.h
@@ -18,7 +18,7 @@
 extern "C" {
 #endif
 
-#include "soc/rmt_caps.h"
+#include "soc/soc_caps.h"
 
 /**
 * @brief RMT channel ID
diff --git a/components/hal/include/hal/rtc_io_hal.h b/components/hal/include/hal/rtc_io_hal.h
index 81e29721c88..5301cb32712 100644
--- a/components/hal/include/hal/rtc_io_hal.h
+++ b/components/hal/include/hal/rtc_io_hal.h
@@ -33,7 +33,7 @@ extern "C" {
  * Select the rtcio function.
  *
  * @note The RTC function must be selected before the pad analog function is enabled.
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @param func Select pin function.
  */
 #define rtcio_hal_function_select(rtcio_num, func) rtcio_ll_function_select(rtcio_num, func)
@@ -41,21 +41,21 @@ extern "C" {
 /**
  * Enable rtcio output.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_output_enable(rtcio_num) rtcio_ll_output_enable(rtcio_num)
 
 /**
  * Disable rtcio output.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_output_disable(rtcio_num) rtcio_ll_output_disable(rtcio_num)
 
 /**
  * Set RTCIO output level.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @param level 0: output low; ~0: output high.
  */
 #define rtcio_hal_set_level(rtcio_num, level) rtcio_ll_set_level(rtcio_num, level)
@@ -63,21 +63,21 @@ extern "C" {
 /**
  * Enable rtcio input.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_input_enable(rtcio_num) rtcio_ll_input_enable(rtcio_num)
 
 /**
  * Disable rtcio input.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_input_disable(rtcio_num) rtcio_ll_input_disable(rtcio_num)
 
 /**
  * Get RTCIO input level.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @return 0: input low; ~0: input high.
  */
 #define rtcio_hal_get_level(rtcio_num) rtcio_ll_get_level(rtcio_num)
@@ -85,7 +85,7 @@ extern "C" {
 /**
  * @brief Set RTC GPIO pad drive capability.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @param strength Drive capability of the pad. Range: 0 ~ 3.
  */
 #define rtcio_hal_set_drive_capability(rtcio_num, strength) rtcio_ll_set_drive_capability(rtcio_num, strength)
@@ -93,7 +93,7 @@ extern "C" {
 /**
  * @brief Get RTC GPIO pad drive capability.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @return Drive capability of the pad. Range: 0 ~ 3.
  */
 #define rtcio_hal_get_drive_capability(rtcio_num) rtcio_ll_get_drive_capability(rtcio_num)
@@ -101,7 +101,7 @@ extern "C" {
 /**
  * Set RTCIO output level.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @param level 0: output low; ~0: output high.
  */
 #define rtcio_hal_set_level(rtcio_num, level) rtcio_ll_set_level(rtcio_num, level)
@@ -109,7 +109,7 @@ extern "C" {
 /**
  * Get RTCIO input level.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @return 0: input low; ~0: input high.
  */
 #define rtcio_hal_get_level(rtcio_num) rtcio_ll_get_level(rtcio_num)
@@ -120,7 +120,7 @@ extern "C" {
  * Configure RTC IO direction, such as output only, input only,
  * output and input.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @param mode IO direction.
  */
 void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode);
@@ -131,7 +131,7 @@ void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode);
  * NOTE: ESP32 support INPUT_ONLY mode.
  *       ESP32S2 support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @param mode IO direction.
  */
 void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
@@ -139,28 +139,28 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 /**
  * RTC GPIO pullup enable.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_pullup_enable(rtcio_num) rtcio_ll_pullup_enable(rtcio_num)
 
 /**
  * RTC GPIO pullup disable.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_pullup_disable(rtcio_num) rtcio_ll_pullup_disable(rtcio_num)
 
 /**
  * RTC GPIO pulldown enable.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_pulldown_enable(rtcio_num) rtcio_ll_pulldown_enable(rtcio_num)
 
 /**
  * RTC GPIO pulldown disable.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_pulldown_disable(rtcio_num) rtcio_ll_pulldown_disable(rtcio_num)
 
@@ -172,7 +172,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
  * This function is useful when going into light or deep sleep mode to prevent
  * the pin configuration from changing.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_hold_enable(rtcio_num) rtcio_ll_force_hold_enable(rtcio_num)
 
@@ -180,7 +180,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
  * Disable hold function on an RTC IO pad
  *
  * @note If disable the pad hold, the status of pad maybe changed in sleep mode.
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_hold_disable(rtcio_num) rtcio_ll_force_hold_disable(rtcio_num)
 
@@ -192,7 +192,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
  * This function is useful when going into light or deep sleep mode to prevent
  * the pin configuration from changing.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_hold_all() rtcio_ll_force_hold_all()
 
@@ -200,14 +200,14 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
  * Disable hold function on an RTC IO pads.
  *
  * @note If disable the pad hold, the status of pad maybe changed in sleep mode.
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_unhold_all() rtcio_ll_force_unhold_all()
 
 /**
  * Enable wakeup function and set wakeup type from light sleep status for rtcio.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  * @param type  Wakeup on high level or low level.
  */
 #define rtcio_hal_wakeup_enable(rtcio_num, type) rtcio_ll_wakeup_enable(rtcio_num, type)
@@ -215,14 +215,14 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 /**
  * Disable wakeup function from light sleep status for rtcio.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_wakeup_disable(rtcio_num) rtcio_ll_wakeup_disable(rtcio_num)
 
 /**
  * Disable wakeup function from light sleep status for rtcio.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 #define rtcio_hal_ext0_set_wakeup_pin(rtcio_num, level)     rtcio_ll_ext0_set_wakeup_pin(rtcio_num, level)
 
@@ -237,7 +237,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
  * rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce
  * deep sleep current.
  *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
  */
 void rtcio_hal_isolate(int rtc_num);
 
diff --git a/components/hal/include/hal/sigmadelta_types.h b/components/hal/include/hal/sigmadelta_types.h
index e6ab0b4737a..e4dce6fbe66 100644
--- a/components/hal/include/hal/sigmadelta_types.h
+++ b/components/hal/include/hal/sigmadelta_types.h
@@ -14,7 +14,7 @@
 
 #pragma once
 
-#include "soc/sigmadelta_caps.h"
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -23,12 +23,27 @@ extern "C" {
 /**
  * @brief SIGMADELTA port number, the max port number is (SIGMADELTA_NUM_MAX -1).
  */
-typedef int sigmadelta_port_t;
+typedef enum {
+    SIGMADELTA_PORT_0,      /*!< SIGMADELTA port 0 */
+    SIGMADELTA_PORT_MAX,    /*!< SIGMADELTA port max */
+} sigmadelta_port_t;
+
+_Static_assert(SIGMADELTA_PORT_MAX == SOC_SIGMADELTA_NUM, "Sigma-delta port num incorrect.");
 
 /**
  * @brief Sigma-delta channel list
  */
-typedef int sigmadelta_channel_t;
+typedef enum {
+    SIGMADELTA_CHANNEL_0,   /*!< Sigma-delta channel 0 */
+    SIGMADELTA_CHANNEL_1,   /*!< Sigma-delta channel 1 */
+    SIGMADELTA_CHANNEL_2,   /*!< Sigma-delta channel 2 */
+    SIGMADELTA_CHANNEL_3,   /*!< Sigma-delta channel 3 */
+    SIGMADELTA_CHANNEL_4,   /*!< Sigma-delta channel 4 */
+    SIGMADELTA_CHANNEL_5,   /*!< Sigma-delta channel 5 */
+    SIGMADELTA_CHANNEL_6,   /*!< Sigma-delta channel 6 */
+    SIGMADELTA_CHANNEL_7,   /*!< Sigma-delta channel 7 */
+    SIGMADELTA_CHANNEL_MAX, /*!< Sigma-delta channel max */
+} sigmadelta_channel_t;
 
 /**
  * @brief Sigma-delta configure struct
diff --git a/components/hal/include/hal/spi_slave_hal.h b/components/hal/include/hal/spi_slave_hal.h
index 2beccd45c08..b6d2ad5b352 100644
--- a/components/hal/include/hal/spi_slave_hal.h
+++ b/components/hal/include/hal/spi_slave_hal.h
@@ -32,10 +32,10 @@
 
 #pragma once
 
+#include <esp_types.h>
 #include "soc/lldesc.h"
 #include "soc/spi_struct.h"
-#include <esp_types.h>
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/spi_ll.h"
 
 /**
diff --git a/components/hal/include/hal/spi_types.h b/components/hal/include/hal/spi_types.h
index b2fef1c3cb7..39aa2682dc1 100644
--- a/components/hal/include/hal/spi_types.h
+++ b/components/hal/include/hal/spi_types.h
@@ -14,10 +14,10 @@
 
 #pragma once
 
-#include "soc/spi_caps.h"
 #include "esp_attr.h"
-#include "sdkconfig.h"
 #include <esp_bit_defs.h>
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
 
 /**
  * @brief Enum with the three SPI peripherals that are software-accessible in it
diff --git a/components/hal/include/hal/systimer_types.h b/components/hal/include/hal/systimer_types.h
index 2ae7c4a2e74..02e65daf30c 100644
--- a/components/hal/include/hal/systimer_types.h
+++ b/components/hal/include/hal/systimer_types.h
@@ -19,7 +19,7 @@ extern "C" {
 #endif
 
 #include <stdint.h>
-#include "soc/systimer_caps.h"
+#include "soc/soc_caps.h"
 
 /*
  * @brief The structure of the counter value in systimer
diff --git a/components/hal/include/hal/timer_hal.h b/components/hal/include/hal/timer_hal.h
index f9188fe3f12..47a153226ca 100644
--- a/components/hal/include/hal/timer_hal.h
+++ b/components/hal/include/hal/timer_hal.h
@@ -27,9 +27,9 @@
 extern "C" {
 #endif
 
+#include "soc/soc_caps.h"
 #include "hal/timer_ll.h"
 #include "hal/timer_types.h"
-#include "soc/timer_group_caps.h"
 
 /**
  * Context that should be maintained by both the driver and the HAL
diff --git a/components/hal/include/hal/timer_types.h b/components/hal/include/hal/timer_types.h
index b84478dcf47..01f04830949 100644
--- a/components/hal/include/hal/timer_types.h
+++ b/components/hal/include/hal/timer_types.h
@@ -21,8 +21,8 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include <esp_bit_defs.h>
-#include "soc/timer_group_caps.h"
 #include "esp_attr.h"
+#include "soc/soc_caps.h"
 
 /**
  * @brief Selects a Timer-Group out of 2 available groups
diff --git a/components/hal/include/hal/touch_sensor_types.h b/components/hal/include/hal/touch_sensor_types.h
index d2ddf33e209..efea2b9ac71 100644
--- a/components/hal/include/hal/touch_sensor_types.h
+++ b/components/hal/include/hal/touch_sensor_types.h
@@ -15,11 +15,10 @@
 #pragma once
 
 #include <stdbool.h>
-
-#include "soc/soc.h"
-#include "soc/touch_sensor_caps.h"
-#include "sdkconfig.h"
 #include "esp_attr.h"
+#include "soc/soc.h"
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
 
 /** Touch pad channel */
 typedef enum {
@@ -115,9 +114,10 @@ typedef enum {
 } touch_trigger_src_t;
 
 /********************************/
+#define TOUCH_PAD_BIT_MASK_ALL              ((1<<SOC_TOUCH_SENSOR_NUM)-1)
 #define TOUCH_PAD_SLOPE_DEFAULT             (TOUCH_PAD_SLOPE_7)
 #define TOUCH_PAD_TIE_OPT_DEFAULT           (TOUCH_PAD_TIE_OPT_LOW)
-#define TOUCH_PAD_BIT_MASK_MAX              (SOC_TOUCH_SENSOR_BIT_MASK_MAX)
+#define TOUCH_PAD_BIT_MASK_MAX              (TOUCH_PAD_BIT_MASK_ALL)
 #define TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD    (TOUCH_HVOLT_2V7)
 #define TOUCH_PAD_LOW_VOLTAGE_THRESHOLD     (TOUCH_LVOLT_0V5)
 #define TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD   (TOUCH_HVOLT_ATTEN_0V5)
diff --git a/components/hal/include/hal/twai_types.h b/components/hal/include/hal/twai_types.h
index 1e6fc7ed8b2..5c51dba6d3a 100644
--- a/components/hal/include/hal/twai_types.h
+++ b/components/hal/include/hal/twai_types.h
@@ -21,6 +21,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "sdkconfig.h"
+#include "soc/soc_caps.h"
 
 /**
  * @brief   TWAI Constants
@@ -46,6 +47,10 @@ extern "C" {
 #define TWAI_MSG_FLAG_SELF              0x08        /**< Transmit as a Self Reception Request. Unused for received. */
 #define TWAI_MSG_FLAG_DLC_NON_COMP      0x10        /**< Message's Data length code is larger than 8. This will break compliance with TWAI */
 
+#define TWAI_BRP_MAX    SOC_TWAI_BRP_MAX    /**< Maximum configurable BRP value */
+#define TWAI_BRP_MIN    SOC_TWAI_BRP_MIN    /**< Minimum configurable BRP value */
+
+
 /**
  * @brief Initializer macros for timing configuration structure
  *
@@ -55,12 +60,12 @@ extern "C" {
  * @note These timing values are based on the assumption APB clock is at 80MHz
  * @note The available bit rates are dependent on the chip target and revision.
  */
-#if (TWAI_BRP_MAX > 256)
+#if (SOC_TWAI_BRP_MAX > 256)
 #define TWAI_TIMING_CONFIG_1KBITS()     {.brp = 4000, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_5KBITS()     {.brp = 800, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_10KBITS()    {.brp = 400, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #endif
-#if (TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
+#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
 #define TWAI_TIMING_CONFIG_12_5KBITS()  {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_16KBITS()    {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_20KBITS()    {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
diff --git a/components/hal/include/hal/uart_types.h b/components/hal/include/hal/uart_types.h
index 6d44cf1fee8..04ff86b323a 100644
--- a/components/hal/include/hal/uart_types.h
+++ b/components/hal/include/hal/uart_types.h
@@ -20,7 +20,7 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
-#include "soc/uart_caps.h"
+#include "soc/soc_caps.h"
 
 
 /**
diff --git a/components/hal/include/hal/wdt_hal.h b/components/hal/include/hal/wdt_hal.h
index 2347fb5978d..13d9f5d2f55 100644
--- a/components/hal/include/hal/wdt_hal.h
+++ b/components/hal/include/hal/wdt_hal.h
@@ -25,7 +25,7 @@ extern "C" {
 #endif
 
 #include <stdbool.h>
-#include "soc/timer_group_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/wdt_types.h"
 #include "hal/mwdt_ll.h"
 #include "hal/rwdt_ll.h"
diff --git a/components/hal/mpu_hal.c b/components/hal/mpu_hal.c
index 8b89f5d5978..d7913c54006 100644
--- a/components/hal/mpu_hal.c
+++ b/components/hal/mpu_hal.c
@@ -21,7 +21,7 @@
 #include "hal/mpu_ll.h"
 #include "hal/mpu_types.h"
 
-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"
 
 void mpu_hal_set_region_access(int id, mpu_access_t access)
 {
diff --git a/components/hal/spi_flash_hal.c b/components/hal/spi_flash_hal.c
index 6e881daa6f6..b545cbb8d92 100644
--- a/components/hal/spi_flash_hal.c
+++ b/components/hal/spi_flash_hal.c
@@ -15,7 +15,7 @@
 #include <stdlib.h>
 #include "hal/spi_flash_hal.h"
 #include "string.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/hal_defs.h"
 
 #define APB_CYCLE_NS   (1000*1000*1000LL/APB_CLK_FREQ)
diff --git a/components/hal/twai_hal.c b/components/hal/twai_hal.c
index 34d7cd1e1c7..12b417d1e4c 100644
--- a/components/hal/twai_hal.c
+++ b/components/hal/twai_hal.c
@@ -32,7 +32,7 @@ bool twai_hal_init(twai_hal_context_t *hal_ctx)
     if (!twai_ll_is_in_reset_mode(hal_ctx->dev)) {    //Must enter reset mode to write to config registers
         return false;
     }
-#ifdef TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT
+#ifdef SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT
     twai_ll_enable_extended_reg_layout(hal_ctx->dev);        //Changes the address layout of the registers
 #endif
     twai_ll_set_mode(hal_ctx->dev, TWAI_MODE_LISTEN_ONLY);    //Freeze REC by changing to LOM mode
@@ -70,7 +70,7 @@ void twai_hal_start(twai_hal_context_t *hal_ctx, twai_mode_t mode)
     twai_ll_set_mode(hal_ctx->dev, mode);                //Set operating mode
     (void) twai_ll_get_and_clear_intrs(hal_ctx->dev);    //Clear any latched interrupts
     TWAI_HAL_SET_FLAG(hal_ctx->state_flags, TWAI_HAL_STATE_FLAG_RUNNING);
-    twai_ll_exit_reset_mode(hal_ctx->dev); 
+    twai_ll_exit_reset_mode(hal_ctx->dev);
 }
 
 void twai_hal_stop(twai_hal_context_t *hal_ctx)
diff --git a/components/soc/soc/esp32/gpio_periph.c b/components/soc/soc/esp32/gpio_periph.c
index d8a30b0af50..a4132037418 100644
--- a/components/soc/soc/esp32/gpio_periph.c
+++ b/components/soc/soc/esp32/gpio_periph.c
@@ -14,7 +14,7 @@
 
 #include "soc/gpio_periph.h"
 
-const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
+const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
     IO_MUX_GPIO0_REG,
     IO_MUX_GPIO1_REG,
     IO_MUX_GPIO2_REG,
@@ -57,7 +57,7 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
     IO_MUX_GPIO39_REG,
 };
 
-const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
+const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
     0,
     BIT(1),
     0,
diff --git a/components/soc/soc/esp32/include/soc/adc_caps.h b/components/soc/soc/esp32/include/soc/adc_caps.h
deleted file mode 100644
index 66f5d6bb76d..00000000000
--- a/components/soc/soc/esp32/include/soc/adc_caps.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#pragma once 
-
-#define SOC_ADC_PERIPH_NUM              (2)
-#define SOC_ADC_PATT_LEN_MAX            (16)
-
-#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
-#define SOC_ADC_MAX_CHANNEL_NUM         (10)
-
-#define SOC_ADC1_DATA_INVERT_DEFAULT    (1)
-#define SOC_ADC2_DATA_INVERT_DEFAULT    (1)
-
-#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
-
-#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
-#define SOC_ADC_FSM_START_WAIT_DEFAULT      (SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT * 2)
-#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
-#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (2)
-
-/**
- * Check if adc support digital controller (DMA) mode.
- * @value
- *      - 1 : support;
- *      - 0 : not support;
- */
-#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 0)
-
-#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
-
-#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
-
-#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT    (16)
\ No newline at end of file
diff --git a/components/soc/soc/esp32/include/soc/can_caps.h b/components/soc/soc/esp32/include/soc/can_caps.h
deleted file mode 100644
index f372e9e07e6..00000000000
--- a/components/soc/soc/esp32/include/soc/can_caps.h
+++ /dev/null
@@ -1,33 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#warning soc/can_caps.h is deprecated, please use soc/twai_caps.h instead
-
-/* ---------------------------- Compatibility ------------------------------- */
-
-#define CAN_BRP_MIN                         2
-#define CAN_BRP_MAX                         128
-#define CAN_BRP_MAX_ECO                     256
-#define CAN_BRP_DIV_THRESH                  128
-#define CAN_SUPPORT_MULTI_ADDRESS_LAYOUT    1
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32/include/soc/can_periph.h b/components/soc/soc/esp32/include/soc/can_periph.h
index f4862b572a0..1feac200d26 100644
--- a/components/soc/soc/esp32/include/soc/can_periph.h
+++ b/components/soc/soc/esp32/include/soc/can_periph.h
@@ -23,8 +23,8 @@ extern "C" {
 #warning soc/can_periph.h is deprecated, please use soc/twai_periph.h instead
 
 #if CONFIG_IDF_TARGET_ESP32
+#include "soc/soc_caps.h"
 #include "soc/can_struct.h"
-#include "soc/can_caps.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/soc/esp32/include/soc/dac_caps.h b/components/soc/soc/esp32/include/soc/dac_caps.h
deleted file mode 100644
index 8f3fc02fda4..00000000000
--- a/components/soc/soc/esp32/include/soc/dac_caps.h
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_RTC_DAC_CAPS_H_
-#define _SOC_RTC_DAC_CAPS_H_
-
-#define SOC_DAC_PERIPH_NUM      2
-
-#define SOC_DAC_RESOLUTION      8 // DAC resolution ratio 8 bit
-
-#endif
\ No newline at end of file
diff --git a/components/soc/soc/esp32/include/soc/gpio_caps.h b/components/soc/soc/esp32/include/soc/gpio_caps.h
deleted file mode 100644
index 3c202c73177..00000000000
--- a/components/soc/soc/esp32/include/soc/gpio_caps.h
+++ /dev/null
@@ -1,51 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32 has 1 GPIO peripheral
-#define SOC_GPIO_PORT           (1)
-#define GPIO_PIN_COUNT          (40)
-
-// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. 
-// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
-#define GPIO_SUPPORTS_RTC_INDEPENDENT (0)
-// Force hold is a new function of ESP32-S2
-#define GPIO_SUPPORTS_FORCE_HOLD      (0)
-
-#define GPIO_APP_CPU_INTR_ENA      (BIT(0))
-#define GPIO_APP_CPU_NMI_INTR_ENA  (BIT(1))
-#define GPIO_PRO_CPU_INTR_ENA      (BIT(2))
-#define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(3))
-#define GPIO_SDIO_EXT_INTR_ENA     (BIT(4))
-
-#define GPIO_MODE_DEF_DISABLE         (0)
-#define GPIO_MODE_DEF_INPUT           (BIT0)
-#define GPIO_MODE_DEF_OUTPUT          (BIT1)
-#define GPIO_MODE_DEF_OD              (BIT2)
-
-#define GPIO_IS_VALID_GPIO(gpio_num)              ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0))                                     /*!< Check whether it is a valid GPIO number */
-#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)       ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34))                                                  /*!< Check whether it can be a valid GPIO number of output mode */
-#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask)   ((gpio_mask & (GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39)))  /*!< Check whether it contains input io */
-
-#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
-#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x30)
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32s2/include/soc/ledc_caps.h b/components/soc/soc/esp32/include/soc/gpio_pins.h
similarity index 88%
rename from components/soc/soc/esp32s2/include/soc/ledc_caps.h
rename to components/soc/soc/esp32/include/soc/gpio_pins.h
index 0600e581259..02a9693c4cb 100644
--- a/components/soc/soc/esp32s2/include/soc/ledc_caps.h
+++ b/components/soc/soc/esp32/include/soc/gpio_pins.h
@@ -3,6 +3,7 @@
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -17,7 +18,9 @@
 extern "C" {
 #endif
 
-#define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
+
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x30)
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/esp32/include/soc/i2c_caps.h b/components/soc/soc/esp32/include/soc/i2c_caps.h
deleted file mode 100644
index d2fec80990c..00000000000
--- a/components/soc/soc/esp32/include/soc/i2c_caps.h
+++ /dev/null
@@ -1,36 +0,0 @@
-// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32 have 2 I2C.
-#define SOC_I2C_NUM            (2)
-
-#define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
-#define I2C_INTR_MASK          (0x3fff) /*!< I2C all interrupt bitmap */
-
-//ESP32 do not support hardware FSM reset
-#define I2C_SUPPORT_HW_FSM_RST  (0)
-//ESP32 do not support hardware clear bus
-#define I2C_SUPPORT_HW_CLR_BUS  (0)
-
-#ifdef __cplusplus
-}
-#endif
-
-
diff --git a/components/soc/soc/esp32/include/soc/i2s_caps.h b/components/soc/soc/esp32/include/soc/i2s_caps.h
deleted file mode 100644
index 07c707e6990..00000000000
--- a/components/soc/soc/esp32/include/soc/i2s_caps.h
+++ /dev/null
@@ -1,37 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define APLL_MIN_FREQ                     (250000000)
-#define APLL_MAX_FREQ                     (500000000)
-#define APLL_I2S_MIN_RATE                 (10675) //in Hz, I2S Clock rate limited by hardware
-#define I2S_AD_BCK_FACTOR                 (2)
-#define I2S_PDM_BCK_FACTOR                (64)
-#define I2S_MAX_BUFFER_SIZE               (4 * 1024 * 1024) //the maximum RAM can be allocated
-#define I2S_BASE_CLK                      (2*APB_CLK_FREQ)
-
-// ESP32 have 2 I2S
-#define SOC_I2S_NUM            (2)
-
-#define SOC_I2S_SUPPORTS_PDM       (1) // ESP32 support PDM
-#define SOC_I2S_SUPPORTS_DMA_EQUAL (0) // ESP32 don't support dma equal
-#define SOC_I2S_SUPPORTS_ADC_DAC   (1) // ESP32 support ADC and DAC
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32/include/soc/mcpwm_caps.h b/components/soc/soc/esp32/include/soc/mcpwm_caps.h
deleted file mode 100644
index bb2ce198622..00000000000
--- a/components/soc/soc/esp32/include/soc/mcpwm_caps.h
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_MCPWM_PERIPH_NUM        2   ///< MCPWM peripheral number
-#define SOC_MCPWM_TIMER_NUM         3   ///< Timer that each peripheral has
-#define SOC_MCPWM_OP_NUM            3   ///< Operator that each peripheral has
-#define SOC_MCPWM_COMPARATOR_NUM    2   ///< Comparator that each operator has
-#define SOC_MCPWM_GENERATOR_NUM     2   ///< Generator that each operator has
-#define SOC_MCPWM_FAULT_SIG_NUM     3   ///< Fault signal number that each peripheral has
\ No newline at end of file
diff --git a/components/soc/soc/esp32/include/soc/mpu_caps.h b/components/soc/soc/esp32/include/soc/mpu_caps.h
deleted file mode 100644
index 8e12a2b133e..00000000000
--- a/components/soc/soc/esp32/include/soc/mpu_caps.h
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
-#define SOC_MPU_MIN_REGION_SIZE                   0x20000000
-#define SOC_MPU_REGIONS_MAX_NUM                   8
-#define SOC_MPU_REGION_RO_SUPPORTED               0
-#define SOC_MPU_REGION_WO_SUPPORTED               0
\ No newline at end of file
diff --git a/components/soc/soc/esp32/include/soc/rmt_caps.h b/components/soc/soc/esp32/include/soc/rmt_caps.h
deleted file mode 100644
index 8f25859365f..00000000000
--- a/components/soc/soc/esp32/include/soc/rmt_caps.h
+++ /dev/null
@@ -1,26 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
-#define SOC_RMT_CHANNELS_NUM (8)       /*!< Total 8 channels */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32/include/soc/rtc_io_caps.h b/components/soc/soc/esp32/include/soc/rtc_io_caps.h
deleted file mode 100644
index 29d4ec645f6..00000000000
--- a/components/soc/soc/esp32/include/soc/rtc_io_caps.h
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_RTC_IO_CAPS_H_
-#define _SOC_RTC_IO_CAPS_H_
-
-#define SOC_RTC_IO_PIN_COUNT   18
-#define SOC_PIN_FUNC_RTC_IO     0
-
-#endif
\ No newline at end of file
diff --git a/components/soc/soc/esp32/include/soc/sigmadelta_caps.h b/components/soc/soc/esp32/include/soc/sigmadelta_caps.h
deleted file mode 100644
index 53035d18550..00000000000
--- a/components/soc/soc/esp32/include/soc/sigmadelta_caps.h
+++ /dev/null
@@ -1,37 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32 have 1 SIGMADELTA peripheral.
-#define SIGMADELTA_PORT_0             (0) /*!< SIGMADELTA port 0 */
-#define SIGMADELTA_PORT_MAX           (1) /*!< SIGMADELTA port max */
-#define SOC_SIGMADELTA_NUM            (SIGMADELTA_PORT_MAX)
-
-#define SIGMADELTA_CHANNEL_0   (0)    /*!< Sigma-delta channel 0 */
-#define SIGMADELTA_CHANNEL_1   (1)    /*!< Sigma-delta channel 1 */
-#define SIGMADELTA_CHANNEL_2   (2)    /*!< Sigma-delta channel 2 */
-#define SIGMADELTA_CHANNEL_3   (3)    /*!< Sigma-delta channel 3 */
-#define SIGMADELTA_CHANNEL_4   (4)    /*!< Sigma-delta channel 4 */
-#define SIGMADELTA_CHANNEL_5   (5)    /*!< Sigma-delta channel 5 */
-#define SIGMADELTA_CHANNEL_6   (6)    /*!< Sigma-delta channel 6 */
-#define SIGMADELTA_CHANNEL_7   (7)    /*!< Sigma-delta channel 7 */
-#define SIGMADELTA_CHANNEL_MAX (8)
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32/include/soc/soc_caps.h b/components/soc/soc/esp32/include/soc/soc_caps.h
index a9e8e2c924f..96279bd6ee5 100644
--- a/components/soc/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/soc/esp32/include/soc/soc_caps.h
@@ -1,16 +1,237 @@
-// The long term plan is to have a single soc_caps.h for each peripheral.
-// During the refactoring and multichip support development process, we
-// seperate these information into periph_caps.h for each peripheral and
-// include them here.
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * Soc capabilities file, describing the following chip attributes:
+ * - Peripheral or feature supported or not
+ * - Number of resources (peripheral, channel, etc.)
+ * - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency
+ *   supported, etc.
+ *
+ * For boolean definitions:
+ * - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`.
+ *   (`#define` blank string causes error when checking by `#if x`)
+ * - if false: not define anything at all.
+ *   (`#ifdef x` is true even when `#define 0` is defined before.)
+ *
+ * The code depending on this file uses these boolean definitions as `#if x` or `#if !x`.
+ * (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define
+ * x 0`, it's still a risk.)
+ *
+ * ECO & exceptions:
+ * For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by
+ * `#if x` and `#if !x`, making these missing definitions more obvious.
+ */
 
 #pragma once
 
-#define SOC_MCPWM_SUPPORTED 1
-#define SOC_SDMMC_HOST_SUPPORTED 1
-#define SOC_BT_SUPPORTED 1
+#ifdef __has_include
+#  if __has_include("sdkconfig.h")
+#    include "sdkconfig.h"
+#    define SOC_CAPS_ECO_VER    CONFIG_ESP32_REV_MIN
+#  endif
+#endif
+
+#if __DOXYGEN__ && !defined(SOC_CAPS_ECO_VER)
+#define SOC_CAPS_ECO_VER    SOC_CAPS_ECO_VER_MAX
+#endif
+
+#ifndef SOC_CAPS_ECO_VER
+#warning ECO version not determined. Some ECO related caps will not be available.
+#warning Define SOC_CAPS_ECO_VER before including this header.
+
+// Define warning strings here for ECO-ed features to show error when they are used without being
+// defined correctly
+#define SOC_BROWNOUT_RESET_SUPPORTED    "Not determined"
+#define SOC_TWAI_BRP_DIV_SUPPORTED      "Not determined"
+#endif
+
+/*-------------------------- COMMON CAPS ---------------------------------------*/
+#define SOC_CAPS_ECO_VER_MAX        3
+
+#define SOC_MCPWM_SUPPORTED         1
+#define SOC_SDMMC_HOST_SUPPORTED    1
+#define SOC_BT_SUPPORTED            1
 #define SOC_SDIO_SLAVE_SUPPORTED    1
-#define SOC_TWAI_SUPPORTED 1
-#define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED
-#define SOC_EMAC_SUPPORTED 1
-#define SOC_RISCV_COPROC_SUPPORTED 0
-#define SOC_CPU_CORES_NUM 2
+#define SOC_TWAI_SUPPORTED          1
+#define SOC_EMAC_SUPPORTED          1
+#define SOC_RISCV_COPROC_SUPPORTED  0   //TODO: correct the caller and remove this line
+#define SOC_CPU_CORES_NUM           2
+
+
+/*-------------------------- ADC CAPS ----------------------------------------*/
+#define SOC_ADC_PERIPH_NUM              (2)
+#define SOC_ADC_PATT_LEN_MAX            (16)
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
+#define SOC_ADC_MAX_CHANNEL_NUM         (10)
+
+/**
+ * Check if adc support digital controller (DMA) mode.
+ * @value
+ *      - 1 : support;
+ *      - 0 : not support;
+ */
+#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 0)
+
+/*-------------------------- BROWNOUT CAPS -----------------------------------*/
+#if SOC_CAPS_ECO_VER >= 1
+#define SOC_BROWNOUT_RESET_SUPPORTED 1
+#endif
+
+/*-------------------------- CPU CAPS ----------------------------------------*/
+#define SOC_CPU_BREAKPOINTS_NUM         2
+#define SOC_CPU_WATCHPOINTS_NUM         2
+
+#define SOC_CPU_WATCHPOINT_SIZE         64 // bytes
+
+/*-------------------------- DAC CAPS ----------------------------------------*/
+#define SOC_DAC_PERIPH_NUM      2
+#define SOC_DAC_RESOLUTION      8 // DAC resolution ratio 8 bit
+
+/*-------------------------- GPIO CAPS ---------------------------------------*/
+// ESP32 has 1 GPIO peripheral
+#define SOC_GPIO_PORT                   (1)
+#define SOC_GPIO_PIN_COUNT              40
+
+
+// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
+// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
+#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT   (0)
+// Force hold is a new function of ESP32-S2
+#define SOC_GPIO_SUPPORT_FORCE_HOLD        (0)
+
+// 0~39 except from 20, 24, 28~31 are valid
+#define SOC_GPIO_VALID_GPIO_MASK        (0xFFFFFFFFFFULL & ~(0ULL | BIT20 | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
+// GPIO >= 34 are input only
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))
+
+/*-------------------------- I2C CAPS ----------------------------------------*/
+// ESP32 have 2 I2C.
+#define SOC_I2C_NUM             (2)
+
+#define SOC_I2C_FIFO_LEN        (32) /*!< I2C hardware FIFO depth */
+//ESP32 do not support hardware FSM reset
+#define SOC_I2C_SUPPORT_HW_FSM_RST  (0)
+//ESP32 do not support hardware clear bus
+#define SOC_I2C_SUPPORT_HW_CLR_BUS  (0)
+
+/*-------------------------- I2S CAPS ----------------------------------------*/
+// ESP32 have 2 I2S
+#define SOC_I2S_NUM                 (2)
+
+#define SOC_I2S_SUPPORTS_PDM        (1) // ESP32 support PDM
+#define SOC_I2S_SUPPORTS_DMA_EQUAL  (0) // ESP32 don't support dma equal
+#define SOC_I2S_SUPPORTS_ADC_DAC    (1) // ESP32 support ADC and DAC
+
+#define SOC_I2S_MAX_BUFFER_SIZE     (4 * 1024 * 1024) //the maximum RAM can be allocated
+
+#define SOC_I2S_APLL_MIN_FREQ       (250000000)
+#define SOC_I2S_APLL_MAX_FREQ       (500000000)
+#define SOC_I2S_APLL_MIN_RATE       (10675) //in Hz, I2S Clock rate limited by hardware
+
+/*-------------------------- LEDC CAPS ---------------------------------------*/
+#define SOC_LEDC_SUPPORT_HS_MODE  (1)
+
+/*-------------------------- MCPWM CAPS --------------------------------------*/
+#define SOC_MCPWM_PERIPH_NUM        2   ///< MCPWM peripheral number
+#define SOC_MCPWM_TIMER_NUM         3   ///< Timer that each peripheral has
+#define SOC_MCPWM_OP_NUM            3   ///< Operator that each peripheral has
+#define SOC_MCPWM_COMPARATOR_NUM    2   ///< Comparator that each operator has
+#define SOC_MCPWM_GENERATOR_NUM     2   ///< Generator that each operator has
+#define SOC_MCPWM_FAULT_SIG_NUM     3   ///< Fault signal number that each peripheral has
+
+/*-------------------------- MPU CAPS ----------------------------------------*/
+//TODO: correct the caller and remove unsupported lines
+#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
+#define SOC_MPU_MIN_REGION_SIZE                   0x20000000
+#define SOC_MPU_REGIONS_MAX_NUM                   8
+#define SOC_MPU_REGION_RO_SUPPORTED               0
+#define SOC_MPU_REGION_WO_SUPPORTED               0
+
+/*-------------------------- PCNT CAPS ---------------------------------------*/
+// ESP32 have 1 PCNT peripheral
+#define SOC_PCNT_PORT_NUM      (1)
+#define SOC_PCNT_UNIT_NUM      (8)
+
+/*-------------------------- RMT CAPS ----------------------------------------*/
+#define SOC_RMT_CHANNEL_MEM_WORDS   (64) /*!< Each channel owns 64 words memory */
+#define SOC_RMT_CHANNELS_NUM        (8)  /*!< Total 8 channels */
+
+/*-------------------------- RTCIO CAPS --------------------------------------*/
+#define SOC_RTCIO_PIN_COUNT 18
+
+/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
+// ESP32 have 1 SIGMADELTA peripheral.
+#define SOC_SIGMADELTA_NUM            1
+
+/*-------------------------- SPI CAPS ----------------------------------------*/
+#define SOC_SPI_PERIPH_NUM          3
+#define SOC_SPI_DMA_CHAN_NUM        2
+
+#define SOC_SPI_PERIPH_CS_NUM(i)    3
+
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
+
+#define SOC_SPI_SUPPORT_AS_CS       1 //Support to toggle the CS while the clock toggles
+
+// Peripheral supports DIO, DOUT, QIO, or QOUT
+#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host)         ({(void)spi_host; 1;})
+
+// Peripheral doesn't support output given level during its "dummy phase"
+#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_host)   ({(void)spi_host; 0;})
+
+/*-------------------------- TIMER GROUP CAPS --------------------------------*/
+// No contents here
+
+/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
+#define SOC_TOUCH_SENSOR_NUM                (10)
+
+#define SOC_TOUCH_PAD_MEASURE_WAIT_MAX      (0xFF)  /*!<The timer frequency is 8Mhz, the max value is 0xff */
+#define SOC_TOUCH_PAD_THRESHOLD_MAX         (0)     /*!<If set touch threshold max value, The touch sensor can't be in touched status */
+
+/*-------------------------- TWAI CAPS ---------------------------------------*/
+#define SOC_TWAI_BRP_MIN                        2
+#define SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT   1
+
+#define SOC_TWAI_BRP_MAX_ECO0               128
+//Any even number from 2 to 128
+#define SOC_TWAI_BRP_IS_VALID_ECO0(brp)     ((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0)
+
+#define SOC_TWAI_BRP_MAX_ECO                256
+//Any even number from 2 to 128, or multiples of 4 from 132 to 256
+#define SOC_TWAI_BRP_IS_VALID_ECO(brp)      (((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0) || ((brp) >= 132 && (brp) <= 256 && ((brp) & 0x3) == 0))
+
+#if SOC_CAPS_ECO_VER >= 2
+#  define SOC_TWAI_BRP_DIV_SUPPORTED    1
+#  define SOC_TWAI_BRP_DIV_THRESH       128
+#  define SOC_TWAI_BRP_IS_VALID         SOC_TWAI_BRP_IS_VALID_ECO
+#  define SOC_TWAI_BRP_MAX              SOC_TWAI_BRP_MAX_ECO
+#else
+#  define SOC_TWAI_BRP_IS_VALID         SOC_TWAI_BRP_IS_VALID_ECO0
+#  define SOC_TWAI_BRP_MAX              SOC_TWAI_BRP_MAX_ECO0
+#endif
+
+/*-------------------------- UART CAPS ---------------------------------------*/
+// ESP32 have 3 UART.
+#define SOC_UART_NUM            (3)
+
+#define SOC_UART_FIFO_LEN       (128)      /*!< The UART hardware FIFO length */
+#define SOC_UART_BITRATE_MAX    (5000000)  /*!< Max bit rate supported by UART */
+
+/* ---------------------------- Compatibility ------------------------------- */
+#define SOC_CAN_SUPPORTED                   SOC_TWAI_SUPPORTED
+#define CAN_BRP_MIN                         SOC_TWAI_BRP_MIN
+#define CAN_BRP_MAX                         SOC_TWAI_BRP_MAX
+#define CAN_BRP_DIV_THRESH                  SOC_TWAI_BRP_DIV_THRESH
+#define CAN_SUPPORT_MULTI_ADDRESS_LAYOUT    SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT
diff --git a/components/soc/soc/esp32s2/include/soc/cpu_caps.h b/components/soc/soc/esp32/include/soc/soc_pins.h
similarity index 61%
rename from components/soc/soc/esp32s2/include/soc/cpu_caps.h
rename to components/soc/soc/esp32/include/soc/soc_pins.h
index fbfd780bd49..6a8101067aa 100644
--- a/components/soc/soc/esp32s2/include/soc/cpu_caps.h
+++ b/components/soc/soc/esp32/include/soc/soc_pins.h
@@ -12,9 +12,15 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+/*
+ * Pin definition header file. The long term plan is to have a single soc_pins.h for all
+ * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
+ * peripheral and include them here to avoid developing conflicts in those header files.
+ */
+
 #pragma once
 
-#define SOC_CPU_BREAKPOINTS_NUM         2
-#define SOC_CPU_WATCHPOINTS_NUM         2
-
-#define SOC_CPU_WATCHPOINT_SIZE         64 // bytes
\ No newline at end of file
+#include "soc/gpio_pins.h"
+#include "soc/spi_pins.h"
+#include "soc/sdio_slave_pins.h"
+#include "soc/sdmmc_pins.h"
\ No newline at end of file
diff --git a/components/soc/soc/esp32/include/soc/spi_caps.h b/components/soc/soc/esp32/include/soc/spi_pins.h
similarity index 71%
rename from components/soc/soc/esp32/include/soc/spi_caps.h
rename to components/soc/soc/esp32/include/soc/spi_pins.h
index fe7461a4520..3727f9bdfeb 100644
--- a/components/soc/soc/esp32/include/soc/spi_caps.h
+++ b/components/soc/soc/esp32/include/soc/spi_pins.h
@@ -14,10 +14,6 @@
 
 #pragma once
 
-#define SOC_SPI_PERIPH_NUM      3
-#define SOC_SPI_DMA_CHAN_NUM    2
-#define SOC_SPI_PERIPH_CS_NUM(i)    3
-
 #define SPI_FUNC_NUM            1
 #define SPI_IOMUX_PIN_NUM_MISO  7
 #define SPI_IOMUX_PIN_NUM_MOSI  8
@@ -51,17 +47,4 @@
 #define VSPI_IOMUX_PIN_NUM_WP   22
 #define VSPI_IOMUX_PIN_NUM_HD   21
 
-#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
-
-#define SOC_SPI_SUPPORT_AS_CS   1   //Support to toggle the CS while the clock toggles
-
-//#define SOC_SPI_SUPPORT_DDRCLK
-//#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
-//#define SOC_SPI_SUPPORT_CD_SIG
-
-// Peripheral supports DIO, DOUT, QIO, or QOUT
-#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host)          ({(void)spi_host; 1;})
-
-// Peripheral doesn't support output given level during its "dummy phase"
-#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_host)    ({(void)spi_host; 0;})
 
diff --git a/components/soc/soc/esp32/include/soc/timer_group_caps.h b/components/soc/soc/esp32/include/soc/timer_group_caps.h
deleted file mode 100644
index e15269aaee2..00000000000
--- a/components/soc/soc/esp32/include/soc/timer_group_caps.h
+++ /dev/null
@@ -1,15 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
diff --git a/components/soc/soc/esp32/include/soc/touch_sensor_caps.h b/components/soc/soc/esp32/include/soc/touch_sensor_caps.h
deleted file mode 100644
index a3d75544988..00000000000
--- a/components/soc/soc/esp32/include/soc/touch_sensor_caps.h
+++ /dev/null
@@ -1,29 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SOC_TOUCH_SENSOR_NUM                (10)
-#define SOC_TOUCH_SENSOR_BIT_MASK_MAX       (0x3ff)
-
-#define SOC_TOUCH_PAD_MEASURE_WAIT          (0xFF)  /*!<The timer frequency is 8Mhz, the max value is 0xff */
-#define SOC_TOUCH_PAD_THRESHOLD_MAX         (0)     /*!<If set touch threshold max value, The touch sensor can't be in touched status */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32/include/soc/twai_caps.h b/components/soc/soc/esp32/include/soc/twai_caps.h
deleted file mode 100644
index 03cf1559974..00000000000
--- a/components/soc/soc/esp32/include/soc/twai_caps.h
+++ /dev/null
@@ -1,29 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define TWAI_BRP_MIN                        2
-#define TWAI_BRP_MAX                        128
-#define TWAI_BRP_MAX_ECO                    256
-#define TWAI_BRP_DIV_THRESH                 128
-#define TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT   1
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32/include/soc/uart_caps.h b/components/soc/soc/esp32/include/soc/uart_caps.h
deleted file mode 100644
index 348a907ed1f..00000000000
--- a/components/soc/soc/esp32/include/soc/uart_caps.h
+++ /dev/null
@@ -1,33 +0,0 @@
-// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define UART_FIFO_LEN          (128)      /*!< The UART hardware FIFO length */
-#define UART_BITRATE_MAX       (5000000)  /*!< Max bit rate supported by UART */
-
-// ESP32 have 3 UART.
-#define SOC_UART_NUM           (3)
-#define SOC_UART_MIN_WAKEUP_THRESH (2)
-
-#define UART_INTR_MASK         (0x7ffff) //All interrupt mask
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/components/soc/soc/esp32/rtc_io_periph.c b/components/soc/soc/esp32/rtc_io_periph.c
index 6ec58f66631..dee0e6481b4 100644
--- a/components/soc/soc/esp32/rtc_io_periph.c
+++ b/components/soc/soc/esp32/rtc_io_periph.c
@@ -14,7 +14,7 @@
 
 #include "soc/rtc_io_periph.h"
 
-const int rtc_io_num_map[GPIO_PIN_COUNT] = {
+const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
     RTCIO_GPIO0_CHANNEL,    //GPIO0
     -1,//GPIO1
     RTCIO_GPIO2_CHANNEL,    //GPIO2
@@ -58,7 +58,7 @@ const int rtc_io_num_map[GPIO_PIN_COUNT] = {
 };
 
 //Reg,Mux,Fun,IE,Up,Down,Rtc_number
-const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = {
+const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = {
     /*REG                    MUX select                  function select              Input enable                Pullup                   Pulldown                 Sleep select                 Sleep input enable             PAD hold                  Pad force hold                    Mask of drive capability Offset                   gpio number */
     {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M,    RTC_IO_SENSE1_FUN_SEL_S,     RTC_IO_SENSE1_FUN_IE_M,     0,                       0,                       RTC_IO_SENSE1_SLP_SEL_M,     RTC_IO_SENSE1_SLP_IE_M,     0, RTC_IO_SENSE1_HOLD_M,     RTC_CNTL_SENSE1_HOLD_FORCE_M,     0,                       0,                       RTCIO_CHANNEL_0_GPIO_NUM}, //36
     {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M,    RTC_IO_SENSE2_FUN_SEL_S,     RTC_IO_SENSE2_FUN_IE_M,     0,                       0,                       RTC_IO_SENSE2_SLP_SEL_M,     RTC_IO_SENSE2_SLP_IE_M,     0, RTC_IO_SENSE2_HOLD_M,     RTC_CNTL_SENSE2_HOLD_FORCE_M,     0,                       0,                       RTCIO_CHANNEL_1_GPIO_NUM}, //37
diff --git a/components/soc/soc/esp32s2/gpio_periph.c b/components/soc/soc/esp32s2/gpio_periph.c
index 03ef9143b14..346984b57c2 100644
--- a/components/soc/soc/esp32s2/gpio_periph.c
+++ b/components/soc/soc/esp32s2/gpio_periph.c
@@ -14,7 +14,7 @@
 
 #include "soc/gpio_periph.h"
 
-const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
+const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
     IO_MUX_GPIO0_REG,
     IO_MUX_GPIO1_REG,
     IO_MUX_GPIO2_REG,
@@ -65,7 +65,7 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
     0,
 };
 
-const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
+const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
     0,
     0,
     0,
diff --git a/components/soc/soc/esp32s2/include/soc/adc_caps.h b/components/soc/soc/esp32s2/include/soc/adc_caps.h
deleted file mode 100644
index a29892d28bf..00000000000
--- a/components/soc/soc/esp32s2/include/soc/adc_caps.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#pragma once 
-
-#define SOC_ADC_PERIPH_NUM              (2)
-#define SOC_ADC_PATT_LEN_MAX            (16)
-
-#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
-#define SOC_ADC_MAX_CHANNEL_NUM         (10)
-
-#define SOC_ADC1_DATA_INVERT_DEFAULT    (0)
-#define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
-
-#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
-
-#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
-#define SOC_ADC_FSM_START_WAIT_DEFAULT      (5)
-#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
-#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (3)
-
-/**
- * Check if adc support digital controller (DMA) mode.
- * @value
- *      - 1 : support;
- *      - 0 : not support;
- */
-#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
-
-#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
-
-#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
-
-#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT    (2)
\ No newline at end of file
diff --git a/components/soc/soc/esp32s2/include/soc/dac_caps.h b/components/soc/soc/esp32s2/include/soc/dac_caps.h
deleted file mode 100644
index 8f3fc02fda4..00000000000
--- a/components/soc/soc/esp32s2/include/soc/dac_caps.h
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_RTC_DAC_CAPS_H_
-#define _SOC_RTC_DAC_CAPS_H_
-
-#define SOC_DAC_PERIPH_NUM      2
-
-#define SOC_DAC_RESOLUTION      8 // DAC resolution ratio 8 bit
-
-#endif
\ No newline at end of file
diff --git a/components/soc/soc/esp32s2/include/soc/gpio_caps.h b/components/soc/soc/esp32s2/include/soc/gpio_caps.h
deleted file mode 100644
index 9fa5936a289..00000000000
--- a/components/soc/soc/esp32s2/include/soc/gpio_caps.h
+++ /dev/null
@@ -1,48 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32-S2 has 1 GPIO peripheral
-#define SOC_GPIO_PORT           (1)
-#define GPIO_PIN_COUNT          (48)
-
-// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. 
-// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
-#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
-// Force hold is a new function of ESP32-S2
-#define GPIO_SUPPORTS_FORCE_HOLD      (1)
-
-#define GPIO_PRO_CPU_INTR_ENA      (BIT(0))
-#define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(1))
-
-#define GPIO_MODE_DEF_DISABLE         (0)
-#define GPIO_MODE_DEF_INPUT           (BIT0)
-#define GPIO_MODE_DEF_OUTPUT          (BIT1)
-#define GPIO_MODE_DEF_OD              (BIT2)
-
-#define GPIO_IS_VALID_GPIO(gpio_num)             ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
-#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)      ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46))              /*!< Check whether it can be a valid GPIO number of output mode */
-#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask)  ((gpio_mask & (GPIO_SEL_46)))                                    /*!< Check whether it contains input io */
-
-#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
-#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32/include/soc/ledc_caps.h b/components/soc/soc/esp32s2/include/soc/gpio_pins.h
similarity index 88%
rename from components/soc/soc/esp32/include/soc/ledc_caps.h
rename to components/soc/soc/esp32s2/include/soc/gpio_pins.h
index e7283424bc8..6d5129fce19 100644
--- a/components/soc/soc/esp32/include/soc/ledc_caps.h
+++ b/components/soc/soc/esp32s2/include/soc/gpio_pins.h
@@ -3,6 +3,7 @@
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -17,7 +18,8 @@
 extern "C" {
 #endif
 
-#define SOC_LEDC_SUPPORT_HS_MODE  (1)
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/esp32s2/include/soc/i2c_caps.h b/components/soc/soc/esp32s2/include/soc/i2c_caps.h
deleted file mode 100644
index 08f452ee3ea..00000000000
--- a/components/soc/soc/esp32s2/include/soc/i2c_caps.h
+++ /dev/null
@@ -1,36 +0,0 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32-S2 have 2 I2C.
-#define SOC_I2C_NUM            (2)
-
-#define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
-#define I2C_INTR_MASK          (0x1ffff) /*!< I2C all interrupt bitmap */
-
-//ESP32-S2 support hardware FSM reset
-#define I2C_SUPPORT_HW_FSM_RST  (1)
-//ESP32-S2 support hardware clear bus
-#define I2C_SUPPORT_HW_CLR_BUS  (1)
-
-#ifdef __cplusplus
-}
-#endif
-
-
diff --git a/components/soc/soc/esp32s2/include/soc/i2s_caps.h b/components/soc/soc/esp32s2/include/soc/i2s_caps.h
deleted file mode 100644
index 17d46803fbb..00000000000
--- a/components/soc/soc/esp32s2/include/soc/i2s_caps.h
+++ /dev/null
@@ -1,30 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define APLL_MIN_FREQ                     (250000000)
-#define APLL_MAX_FREQ                     (500000000)
-#define APLL_I2S_MIN_RATE                 (10675) //in Hz, I2S Clock rate limited by hardware
-#define I2S_AD_BCK_FACTOR                 (2)
-#define I2S_PDM_BCK_FACTOR                (64)
-#define I2S_MAX_BUFFER_SIZE               (4 * 1024 * 1024) //the maximum RAM can be allocated
-#define I2S_BASE_CLK                      (2*APB_CLK_FREQ)
-
-// ESP32-S2 have 2 I2S
-#define SOC_I2S_NUM            (1)
-
-#define SOC_I2S_SUPPORTS_PDM       (0) // ESP32-S2 don't support PDM
-#define SOC_I2S_SUPPORTS_DMA_EQUAL (1) // ESP32-S2 need dma equal
-#define SOC_I2S_SUPPORTS_ADC_DAC   (0) // ESP32-S2 don't support ADC and DAC
diff --git a/components/soc/soc/esp32s2/include/soc/mpu_caps.h b/components/soc/soc/esp32s2/include/soc/mpu_caps.h
deleted file mode 100644
index 8e12a2b133e..00000000000
--- a/components/soc/soc/esp32s2/include/soc/mpu_caps.h
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
-#define SOC_MPU_MIN_REGION_SIZE                   0x20000000
-#define SOC_MPU_REGIONS_MAX_NUM                   8
-#define SOC_MPU_REGION_RO_SUPPORTED               0
-#define SOC_MPU_REGION_WO_SUPPORTED               0
\ No newline at end of file
diff --git a/components/soc/soc/esp32s2/include/soc/pcnt_caps.h b/components/soc/soc/esp32s2/include/soc/pcnt_caps.h
deleted file mode 100644
index 7a0eca58e53..00000000000
--- a/components/soc/soc/esp32s2/include/soc/pcnt_caps.h
+++ /dev/null
@@ -1,27 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32-S2 have 1 PCNT peripheral
-#define SOC_PCNT_PORT_NUM      (1)
-#define SOC_PCNT_UNIT_NUM      (4) // ESP32-S2 only have 4 unit
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32s2/include/soc/rmt_caps.h b/components/soc/soc/esp32s2/include/soc/rmt_caps.h
deleted file mode 100644
index 04b63cb29c0..00000000000
--- a/components/soc/soc/esp32s2/include/soc/rmt_caps.h
+++ /dev/null
@@ -1,30 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SOC_RMT_CHANNEL_MEM_WORDS (64)       /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
-#define SOC_RMT_CHANNELS_NUM (4)             /*!< Total 4 channels */
-#define SOC_RMT_SUPPORT_RX_PINGPONG (1)      /*!< Support Ping-Pong mode on RX path */
-#define SOC_RMT_SUPPORT_RX_DEMODULATION  (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
-#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1)    /*!< Support transmit specified number of cycles in loop mode */
-#define SOC_RMT_SUPPORT_TX_GROUP (1)         /*!< Support a group of TX channels to transmit simultaneously */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32s2/include/soc/rtc_io_caps.h b/components/soc/soc/esp32s2/include/soc/rtc_io_caps.h
deleted file mode 100644
index d57a239e257..00000000000
--- a/components/soc/soc/esp32s2/include/soc/rtc_io_caps.h
+++ /dev/null
@@ -1,18 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_RTC_IO_PIN_COUNT   22
-#define SOC_PIN_FUNC_RTC_IO     0
\ No newline at end of file
diff --git a/components/soc/soc/esp32s2/include/soc/sigmadelta_caps.h b/components/soc/soc/esp32s2/include/soc/sigmadelta_caps.h
deleted file mode 100644
index 5ae88424abe..00000000000
--- a/components/soc/soc/esp32s2/include/soc/sigmadelta_caps.h
+++ /dev/null
@@ -1,37 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32-S2 have 1 SIGMADELTA peripheral.
-#define SIGMADELTA_PORT_0             (0) /*!< SIGMADELTA port 0 */
-#define SIGMADELTA_PORT_MAX           (1) /*!< SIGMADELTA port max */
-#define SOC_SIGMADELTA_NUM            (SIGMADELTA_PORT_MAX)
-
-#define SIGMADELTA_CHANNEL_0   (0)    /*!< Sigma-delta channel 0 */
-#define SIGMADELTA_CHANNEL_1   (1)    /*!< Sigma-delta channel 1 */
-#define SIGMADELTA_CHANNEL_2   (2)    /*!< Sigma-delta channel 2 */
-#define SIGMADELTA_CHANNEL_3   (3)    /*!< Sigma-delta channel 3 */
-#define SIGMADELTA_CHANNEL_4   (4)    /*!< Sigma-delta channel 4 */
-#define SIGMADELTA_CHANNEL_5   (5)    /*!< Sigma-delta channel 5 */
-#define SIGMADELTA_CHANNEL_6   (6)    /*!< Sigma-delta channel 6 */
-#define SIGMADELTA_CHANNEL_7   (7)    /*!< Sigma-delta channel 7 */
-#define SIGMADELTA_CHANNEL_MAX (8)
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32s2/include/soc/soc_caps.h b/components/soc/soc/esp32s2/include/soc/soc_caps.h
index 86e111db020..8c88823a68d 100644
--- a/components/soc/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/soc/esp32s2/include/soc/soc_caps.h
@@ -1,10 +1,42 @@
-// The long term plan is to have a single soc_caps.h for each peripheral.
-// During the refactoring and multichip support development process, we
-// seperate these information into periph_caps.h for each peripheral and
-// include them here.
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * Soc capabilities file, describing the following chip attributes:
+ * - Peripheral or feature supported or not
+ * - Number of resources (peripheral, channel, etc.)
+ * - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency
+ *   supported, etc.
+ *
+ * For boolean definitions:
+ * - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`.
+ *   (`#define` blank string causes error when checking by `#if x`)
+ * - if false: not define anything at all.
+ *   (`#ifdef x` is true even when `#define 0` is defined before.)
+ *
+ * The code depending on this file uses these boolean definitions as `#if x` or `#if !x`.
+ * (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define
+ * x 0`, it's still a risk.)
+ *
+ * ECO & exceptions:
+ * For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by
+ * `#if x` and `#if !x`, making these missing definitions more obvious.
+ */
 
 #pragma once
 
+/*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_TWAI_SUPPORTED 1
 #define SOC_CP_DMA_SUPPORTED 1
 #define SOC_CPU_CORES_NUM 1
@@ -12,4 +44,167 @@
 #define SOC_RISCV_COPROC_SUPPORTED 1
 #define SOC_USB_SUPPORTED 1
 
-#define SOC_CACHE_SUPPORT_WRAP    1
\ No newline at end of file
+#define SOC_CACHE_SUPPORT_WRAP    1
+
+/*-------------------------- ADC CAPS ----------------------------------------*/
+#define SOC_ADC_PERIPH_NUM              (2)
+#define SOC_ADC_PATT_LEN_MAX            (16)
+
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
+#define SOC_ADC_MAX_CHANNEL_NUM         (10)
+
+/**
+ * Check if adc support digital controller (DMA) mode.
+ * @value
+ *      - 1 : support;
+ *      - 0 : not support;
+ */
+#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
+
+/*-------------------------- BROWNOUT CAPS -----------------------------------*/
+#define SOC_BROWNOUT_RESET_SUPPORTED 1
+
+/*-------------------------- CP-DMA CAPS -------------------------------------*/
+#define SOC_CP_DMA_MAX_BUFFER_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */
+
+/*-------------------------- CPU CAPS ----------------------------------------*/
+#define SOC_CPU_BREAKPOINTS_NUM         2
+#define SOC_CPU_WATCHPOINTS_NUM         2
+
+#define SOC_CPU_WATCHPOINT_SIZE         64 // bytes
+
+/*-------------------------- DAC CAPS ----------------------------------------*/
+#define SOC_DAC_PERIPH_NUM      2
+
+#define SOC_DAC_RESOLUTION      8 // DAC resolution ratio 8 bit
+
+/*-------------------------- GPIO CAPS ---------------------------------------*/
+// ESP32-S2 has 1 GPIO peripheral
+#define SOC_GPIO_PORT           (1)
+#define SOC_GPIO_PIN_COUNT      (48)
+
+// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
+// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
+#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
+// Force hold is a new function of ESP32-S2
+#define SOC_GPIO_SUPPORT_FORCE_HOLD      (1)
+
+// 0~47 except from 22~25, 47 are valid
+#define SOC_GPIO_VALID_GPIO_MASK             (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47))
+// GPIO 46, 47 are input only
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK     (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47))
+
+/*-------------------------- I2C CAPS ----------------------------------------*/
+// ESP32-S2 have 2 I2C.
+#define SOC_I2C_NUM            (2)
+
+#define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
+
+//ESP32-S2 support hardware FSM reset
+#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
+//ESP32-S2 support hardware clear bus
+#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+
+/*-------------------------- I2S CAPS ----------------------------------------*/
+// ESP32-S2 have 2 I2S
+#define SOC_I2S_NUM            (1)
+
+#define SOC_I2S_SUPPORTS_PDM       (0) // ESP32-S2 don't support PDM
+#define SOC_I2S_SUPPORTS_DMA_EQUAL (1) // ESP32-S2 need dma equal
+#define SOC_I2S_SUPPORTS_ADC_DAC   (0) // ESP32-S2 don't support ADC and DAC
+
+#define SOC_I2S_MAX_BUFFER_SIZE               (4 * 1024 * 1024) //the maximum RAM can be allocated
+
+#define SOC_I2S_APLL_MIN_FREQ                     (250000000)
+#define SOC_I2S_APLL_MAX_FREQ                     (500000000)
+#define SOC_I2S_APLL_MIN_RATE                 (10675) //in Hz, I2S Clock rate limited by hardware
+
+/*-------------------------- LEDC CAPS ---------------------------------------*/
+#define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
+
+/*-------------------------- MPU CAPS ----------------------------------------*/
+//TODO: correct the caller and remove unsupported lines
+#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
+#define SOC_MPU_MIN_REGION_SIZE                   0x20000000
+#define SOC_MPU_REGIONS_MAX_NUM                   8
+#define SOC_MPU_REGION_RO_SUPPORTED               0
+#define SOC_MPU_REGION_WO_SUPPORTED               0
+
+/*-------------------------- PCNT CAPS ---------------------------------------*/
+// ESP32-S2 have 1 PCNT peripheral
+#define SOC_PCNT_PORT_NUM      (1)
+#define SOC_PCNT_UNIT_NUM      (4) // ESP32-S2 only have 4 unit
+
+/*-------------------------- RMT CAPS ----------------------------------------*/
+#define SOC_RMT_CHANNEL_MEM_WORDS (64)       /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
+#define SOC_RMT_CHANNELS_NUM (4)             /*!< Total 4 channels */
+#define SOC_RMT_SUPPORT_RX_PINGPONG (1)      /*!< Support Ping-Pong mode on RX path */
+#define SOC_RMT_SUPPORT_RX_DEMODULATION  (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
+#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1)    /*!< Support transmit specified number of cycles in loop mode */
+#define SOC_RMT_SUPPORT_TX_GROUP (1)         /*!< Support a group of TX channels to transmit simultaneously */
+
+/*-------------------------- RTCIO CAPS --------------------------------------*/
+#define SOC_RTCIO_PIN_COUNT   22
+
+/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
+// ESP32-S2 have 1 SIGMADELTA peripheral.
+#define SOC_SIGMADELTA_NUM            1
+
+/*-------------------------- SPI CAPS ----------------------------------------*/
+#define SOC_SPI_PERIPH_NUM      3
+#define SOC_SPI_DMA_CHAN_NUM    3
+#define SOC_SPI_PERIPH_CS_NUM(i)    (((i)==0)? 2: (((i)==1)? 6: 3))
+
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE     72
+
+//#define SOC_SPI_SUPPORT_AS_CS         //don't support to toggle the CS while the clock toggles
+#define SOC_SPI_SUPPORT_DDRCLK              1
+#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
+#define SOC_SPI_SUPPORT_CD_SIG              1
+#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
+/// The SPI Slave half duplex mode has been updated greatly in ESP32-S2
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+
+// Peripheral supports DIO, DOUT, QIO, or QOUT
+// VSPI (SPI3) only support 1-bit mode
+#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)          ((host_id) != 2)
+
+// Peripheral supports output given level during its "dummy phase"
+// Only SPI1 supports this feature
+#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id)    ((host_id) == 0)
+
+#define SOC_MEMSPI_IS_INDEPENDENT 1
+
+/*-------------------------- SYS TIMER CAPS ----------------------------------*/
+#define SOC_SYSTIMER_COUNTER_NUM (1)   // Number of counter units
+#define SOC_SYSTIMER_ALARM_NUM (3)     // Number of alarm units
+
+#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
+#define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part
+
+/*-------------------------- TIMER GROUP CAPS --------------------------------*/
+#define SOC_TIMER_GROUP_SUPPORT_XTAL
+
+/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
+#define SOC_TOUCH_SENSOR_NUM                (15)    /*! 15 Touch channels */
+#define SOC_TOUCH_PROXIMITY_CHANNEL_NUM     (3)  /* Sopport touch proximity channel number. */
+
+#define SOC_TOUCH_PAD_THRESHOLD_MAX         (0x1FFFFF)  /*!<If set touch threshold max value, The touch sensor can't be in touched status */
+#define SOC_TOUCH_PAD_MEASURE_WAIT_MAX      (0xFF)  /*!<The timer frequency is 8Mhz, the max value is 0xff */
+
+/*-------------------------- TWAI CAPS ---------------------------------------*/
+#define SOC_TWAI_BRP_MIN                2
+#define SOC_TWAI_BRP_MAX                32768
+
+/*-------------------------- UART CAPS ---------------------------------------*/
+// ESP32-S2 have 2 UART.
+#define SOC_UART_NUM           (2)
+
+#define SOC_UART_FIFO_LEN          (128)      /*!< The UART hardware FIFO length */
+#define SOC_UART_BITRATE_MAX       (5000000)  /*!< Max bit rate supported by UART */
+
+/*-------------------------- USB CAPS ----------------------------------------*/
+#define SOC_USB_PERIPH_NUM 1
+
+/* ---------------------------- Compatibility ------------------------------- */
+// No contents
\ No newline at end of file
diff --git a/components/soc/soc/esp32/include/soc/brownout_caps.h b/components/soc/soc/esp32s2/include/soc/soc_pins.h
similarity index 61%
rename from components/soc/soc/esp32/include/soc/brownout_caps.h
rename to components/soc/soc/esp32s2/include/soc/soc_pins.h
index 3d96a52dfb7..a71cf2d2420 100644
--- a/components/soc/soc/esp32/include/soc/brownout_caps.h
+++ b/components/soc/soc/esp32s2/include/soc/soc_pins.h
@@ -12,18 +12,15 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+/*
+ * Pin definition header file. The long term plan is to have a single soc_pins.h for all
+ * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
+ * peripheral and include them here to avoid developing conflicts in those header files.
+ */
+
 #pragma once
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "sdkconfig.h"
-
-#if __DOXYGEN__ || (CONFIG_ESP32_REV_MIN >= 1)
-#define SOC_BROWNOUT_RESET_SUPPORTED 1
-#endif
-
-#ifdef __cplusplus
-}
-#endif
+#include "soc/usb_pins.h"
+#include "soc/gpio_pins.h"
+#include "soc/spi_pins.h"
+#include "soc/touch_sensor_pins.h"
\ No newline at end of file
diff --git a/components/soc/soc/esp32s2/include/soc/spi_caps.h b/components/soc/soc/esp32s2/include/soc/spi_caps.h
deleted file mode 100644
index b527fafda2b..00000000000
--- a/components/soc/soc/esp32s2/include/soc/spi_caps.h
+++ /dev/null
@@ -1,59 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_SPI_PERIPH_NUM      3
-#define SOC_SPI_DMA_CHAN_NUM    3
-#define SOC_SPI_PERIPH_CS_NUM(i)    (((i)==0)? 2: (((i)==1)? 6: 3))
-
-#define SPI_FUNC_NUM            0
-#define SPI_IOMUX_PIN_NUM_HD    27
-#define SPI_IOMUX_PIN_NUM_CS    29
-#define SPI_IOMUX_PIN_NUM_MOSI  32
-#define SPI_IOMUX_PIN_NUM_CLK   30
-#define SPI_IOMUX_PIN_NUM_MISO  31
-#define SPI_IOMUX_PIN_NUM_WP    28
-//TODO: add the next slot
-
-#define FSPI_FUNC_NUM           4
-#define FSPI_IOMUX_PIN_NUM_HD   9
-#define FSPI_IOMUX_PIN_NUM_CS   10
-#define FSPI_IOMUX_PIN_NUM_MOSI 11
-#define FSPI_IOMUX_PIN_NUM_CLK  12
-#define FSPI_IOMUX_PIN_NUM_MISO 13
-#define FSPI_IOMUX_PIN_NUM_WP   14
-//TODO: add the next slot
-
-//HSPI has no iomux pins
-
-#define SOC_SPI_MAXIMUM_BUFFER_SIZE     72
-
-//#define SOC_SPI_SUPPORT_AS_CS         //don't support to toggle the CS while the clock toggles
-#define SOC_SPI_SUPPORT_DDRCLK              1
-#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
-#define SOC_SPI_SUPPORT_CD_SIG              1
-#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
-/// The SPI Slave half duplex mode has been updated greatly in ESP32-S2
-#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
-
-// Peripheral supports DIO, DOUT, QIO, or QOUT
-// VSPI (SPI3) only support 1-bit mode
-#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)          ((host_id) != 2)
-
-// Peripheral supports output given level during its "dummy phase"
-// Only SPI1 supports this feature
-#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id)    ((host_id) == 0)
-
-#define SOC_MEMSPI_IS_INDEPENDENT 1
diff --git a/components/soc/soc/esp32s2/include/soc/spi_pins.h b/components/soc/soc/esp32s2/include/soc/spi_pins.h
index fb95efe127c..df2f4855487 100644
--- a/components/soc/soc/esp32s2/include/soc/spi_pins.h
+++ b/components/soc/soc/esp32s2/include/soc/spi_pins.h
@@ -1,9 +1,9 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -12,29 +12,22 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#ifndef _SOC_SPI_PINS_H_
-#define _SOC_SPI_PINS_H_
+#pragma once
 
-#define SPI_PERIPH_NUM          3
-
-#define SPI_FUNC_NUM            2
+#define SPI_FUNC_NUM            0
 #define SPI_IOMUX_PIN_NUM_HD    27
 #define SPI_IOMUX_PIN_NUM_CS    29
 #define SPI_IOMUX_PIN_NUM_MOSI  32
 #define SPI_IOMUX_PIN_NUM_CLK   30
 #define SPI_IOMUX_PIN_NUM_MISO  31
 #define SPI_IOMUX_PIN_NUM_WP    28
-//TODO: add the next slot
 
-#define FSPI_FUNC_NUM           0
+#define FSPI_FUNC_NUM           4
 #define FSPI_IOMUX_PIN_NUM_HD   9
 #define FSPI_IOMUX_PIN_NUM_CS   10
 #define FSPI_IOMUX_PIN_NUM_MOSI 11
 #define FSPI_IOMUX_PIN_NUM_CLK  12
 #define FSPI_IOMUX_PIN_NUM_MISO 13
 #define FSPI_IOMUX_PIN_NUM_WP   14
-//TODO: add the next slot
 
-//HSPI and VSPI have no iomux pins
-
-#endif
\ No newline at end of file
+//SPI3 has no iomux pins
diff --git a/components/soc/soc/esp32s2/include/soc/systimer_caps.h b/components/soc/soc/esp32s2/include/soc/systimer_caps.h
deleted file mode 100644
index ca670c2e267..00000000000
--- a/components/soc/soc/esp32s2/include/soc/systimer_caps.h
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_SYSTIMER_COUNTER_NUM (1)   // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM (3)     // Number of alarm units
-
-#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part
diff --git a/components/soc/soc/esp32s2/include/soc/timer_group_caps.h b/components/soc/soc/esp32s2/include/soc/timer_group_caps.h
deleted file mode 100644
index f3c44bae8c8..00000000000
--- a/components/soc/soc/esp32s2/include/soc/timer_group_caps.h
+++ /dev/null
@@ -1,17 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_TIMER_GROUP_SUPPORT_XTAL
diff --git a/components/soc/soc/esp32s2/include/soc/touch_sensor_caps.h b/components/soc/soc/esp32s2/include/soc/touch_sensor_pins.h
similarity index 70%
rename from components/soc/soc/esp32s2/include/soc/touch_sensor_caps.h
rename to components/soc/soc/esp32s2/include/soc/touch_sensor_pins.h
index d9dfb1e95ca..6ec17be72a1 100644
--- a/components/soc/soc/esp32s2/include/soc/touch_sensor_caps.h
+++ b/components/soc/soc/esp32s2/include/soc/touch_sensor_pins.h
@@ -18,17 +18,10 @@
 extern "C" {
 #endif
 
-#define SOC_TOUCH_SENSOR_NUM                (15)    /*! 15 Touch channels */
-#define SOC_TOUCH_SENSOR_BIT_MASK_MAX       (0x7fff)/*! 15 Touch channels */
-
-#define SOC_TOUCH_PAD_MEASURE_WAIT          (0xFF)  /*!<The timer frequency is 8Mhz, the max value is 0xff */
-#define SOC_TOUCH_PAD_THRESHOLD_MAX         (0x1FFFFF)  /*!<If set touch threshold max value, The touch sensor can't be in touched status */
-
 #define SOC_TOUCH_SHIELD_CHANNEL            (14) /*!< The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) */
-#define SOC_TOUCH_DENOISE_CHANNEL           (0)  /*!< T0 is an internal channel that does not have a corresponding external GPIO. 
-                                                    T0 will work simultaneously with the measured channel Tn. Finally, the actual 
+#define SOC_TOUCH_DENOISE_CHANNEL           (0)  /*!< T0 is an internal channel that does not have a corresponding external GPIO.
+                                                    T0 will work simultaneously with the measured channel Tn. Finally, the actual
                                                     measured value of Tn is the value after subtracting lower bits of T0. */
-#define SOC_TOUCH_PROXIMITY_CHANNEL_NUM     (3)  /* Sopport touch proximity channel number. */
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/esp32s2/include/soc/twai_caps.h b/components/soc/soc/esp32s2/include/soc/twai_caps.h
deleted file mode 100644
index 4ad5fbd8291..00000000000
--- a/components/soc/soc/esp32s2/include/soc/twai_caps.h
+++ /dev/null
@@ -1,26 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define TWAI_BRP_MIN                2
-#define TWAI_BRP_MAX                32768
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/soc/esp32s2/include/soc/uart_caps.h b/components/soc/soc/esp32s2/include/soc/uart_caps.h
deleted file mode 100644
index b6a84ce845d..00000000000
--- a/components/soc/soc/esp32s2/include/soc/uart_caps.h
+++ /dev/null
@@ -1,32 +0,0 @@
-// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define UART_FIFO_LEN          (128)      /*!< The UART hardware FIFO length */
-#define UART_BITRATE_MAX       (5000000)  /*!< Max bit rate supported by UART */
-
-// ESP32-S2 have 2 UART.
-#define SOC_UART_NUM           (2)
-#define SOC_UART_MIN_WAKEUP_THRESH (2)
-#define UART_INTR_MASK         (0x7ffff) //All interrupt mask
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/components/soc/soc/esp32s2/include/soc/usb_caps.h b/components/soc/soc/esp32s2/include/soc/usb_caps.h
deleted file mode 100644
index 820e98a4dd5..00000000000
--- a/components/soc/soc/esp32s2/include/soc/usb_caps.h
+++ /dev/null
@@ -1,17 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_USB_PERIPH_NUM 1
diff --git a/components/soc/soc/esp32s2/include/soc/usb_periph.h b/components/soc/soc/esp32s2/include/soc/usb_periph.h
index 782e5ad2404..af18350aea4 100644
--- a/components/soc/soc/esp32s2/include/soc/usb_periph.h
+++ b/components/soc/soc/esp32s2/include/soc/usb_periph.h
@@ -16,7 +16,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
-#include "soc/usb_pins.h"
+#include "soc/soc_pins.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/usb_reg.h"
 #include "soc/usb_types.h"
diff --git a/components/soc/soc/esp32s2/rtc_io_periph.c b/components/soc/soc/esp32s2/rtc_io_periph.c
index 92326be96aa..63828d8d25a 100644
--- a/components/soc/soc/esp32s2/rtc_io_periph.c
+++ b/components/soc/soc/esp32s2/rtc_io_periph.c
@@ -14,7 +14,7 @@
 
 #include "soc/rtc_io_periph.h"
 
-const int rtc_io_num_map[GPIO_PIN_COUNT] = {
+const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
     RTCIO_GPIO0_CHANNEL,    //GPIO0
     RTCIO_GPIO1_CHANNEL,    //GPIO1
     RTCIO_GPIO2_CHANNEL,    //GPIO2
@@ -66,7 +66,7 @@ const int rtc_io_num_map[GPIO_PIN_COUNT] = {
 };
 
 //Reg,Mux,Fun,IE,Up,Down,Rtc_number
-const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = {
+const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = {
     /*REG                    MUX select                    function select               Input enable                 Pullup                    Pulldown                  Sleep select                   Sleep input enable           Sleep output enable           PAD hold   Pad force hold              Mask of drive capability  Offset                    gpio number */
     {RTC_IO_TOUCH_PAD0_REG,  RTC_IO_TOUCH_PAD0_MUX_SEL_M,  RTC_IO_TOUCH_PAD0_FUN_SEL_S,  RTC_IO_TOUCH_PAD0_FUN_IE_M,  RTC_IO_TOUCH_PAD0_RUE_M,  RTC_IO_TOUCH_PAD0_RDE_M,  RTC_IO_TOUCH_PAD0_SLP_SEL_M,   RTC_IO_TOUCH_PAD0_SLP_IE_M,  RTC_IO_TOUCH_PAD0_SLP_OE_M,   0,         RTC_CNTL_TOUCH_PAD0_HOLD_M,  RTC_IO_TOUCH_PAD0_DRV_V,  RTC_IO_TOUCH_PAD0_DRV_S,  RTCIO_CHANNEL_0_GPIO_NUM}, //0
     {RTC_IO_TOUCH_PAD1_REG,  RTC_IO_TOUCH_PAD1_MUX_SEL_M,  RTC_IO_TOUCH_PAD1_FUN_SEL_S,  RTC_IO_TOUCH_PAD1_FUN_IE_M,  RTC_IO_TOUCH_PAD1_RUE_M,  RTC_IO_TOUCH_PAD1_RDE_M,  RTC_IO_TOUCH_PAD1_SLP_SEL_M,   RTC_IO_TOUCH_PAD1_SLP_IE_M,  RTC_IO_TOUCH_PAD1_SLP_OE_M,   0,         RTC_CNTL_TOUCH_PAD1_HOLD_M,  RTC_IO_TOUCH_PAD1_DRV_V,  RTC_IO_TOUCH_PAD1_DRV_S,  RTCIO_CHANNEL_1_GPIO_NUM}, //1
diff --git a/components/soc/soc/esp32s2/usb_periph.c b/components/soc/soc/esp32s2/usb_periph.c
index 9abc798c54c..2f55335feb9 100644
--- a/components/soc/soc/esp32s2/usb_periph.c
+++ b/components/soc/soc/esp32s2/usb_periph.c
@@ -12,8 +12,8 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+#include "soc/soc_caps.h"
 #include "soc/usb_periph.h"
-#include "soc/gpio_caps.h"
 
 const usb_iopin_dsc_t usb_periph_iopins[] = {
     {USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
diff --git a/components/soc/soc/esp32s3/gpio_periph.c b/components/soc/soc/esp32s3/gpio_periph.c
index 03ef9143b14..346984b57c2 100644
--- a/components/soc/soc/esp32s3/gpio_periph.c
+++ b/components/soc/soc/esp32s3/gpio_periph.c
@@ -14,7 +14,7 @@
 
 #include "soc/gpio_periph.h"
 
-const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
+const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
     IO_MUX_GPIO0_REG,
     IO_MUX_GPIO1_REG,
     IO_MUX_GPIO2_REG,
@@ -65,7 +65,7 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
     0,
 };
 
-const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
+const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
     0,
     0,
     0,
diff --git a/components/soc/soc/esp32s3/include/soc/adc_caps.h b/components/soc/soc/esp32s3/include/soc/adc_caps.h
index c622fb3c97f..c6ea4cfaf95 100644
--- a/components/soc/soc/esp32s3/include/soc/adc_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/adc_caps.h
@@ -19,16 +19,6 @@
 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
 #define SOC_ADC_MAX_CHANNEL_NUM         (10)
 
-#define SOC_ADC1_DATA_INVERT_DEFAULT    (0)
-#define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
-
-#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
-
-#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
-#define SOC_ADC_FSM_START_WAIT_DEFAULT      (5)
-#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
-#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (2)
-
 /**
  * Check if adc support digital controller (DMA) mode.
  * @value
@@ -36,9 +26,3 @@
  *      - 0 : not support;
  */
 #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
-
-#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
-
-#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
-
-#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT     (1)
\ No newline at end of file
diff --git a/components/soc/soc/esp32s3/include/soc/gpio_caps.h b/components/soc/soc/esp32s3/include/soc/gpio_caps.h
index 38cb5ed2535..e3a5a10a613 100644
--- a/components/soc/soc/esp32s3/include/soc/gpio_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/gpio_caps.h
@@ -20,27 +20,18 @@ extern "C" {
 
 // ESP32-S3 has 1 GPIO peripheral
 #define SOC_GPIO_PORT           (1)
-#define GPIO_PIN_COUNT          (48)
+#define SOC_GPIO_PIN_COUNT      (48)
 
 // On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
-#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
+#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
 // Force hold is a new function of ESP32-S3
-#define GPIO_SUPPORTS_FORCE_HOLD      (1)
+#define SOC_GPIO_SUPPORT_FORCE_HOLD      (1)
 
-#define GPIO_PRO_CPU_INTR_ENA      (BIT(0))
-#define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+// 0~47 except from 22~25, 47 are valid
+#define SOC_GPIO_VALID_GPIO_MASK             (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47))
+// GPIO 46, 47 are input only
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK     (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47))
 
-#define GPIO_MODE_DEF_DISABLE         (0)
-#define GPIO_MODE_DEF_INPUT           (BIT0)
-#define GPIO_MODE_DEF_OUTPUT          (BIT1)
-#define GPIO_MODE_DEF_OD              (BIT2)
-
-#define GPIO_IS_VALID_GPIO(gpio_num)             ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
-#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)      ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46))              /*!< Check whether it can be a valid GPIO number of output mode */
-#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask)  ((gpio_mask & (GPIO_SEL_46)))                                    /*!< Check whether it contains input io */
-
-#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
-#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/esp32/include/soc/pcnt_caps.h b/components/soc/soc/esp32s3/include/soc/gpio_pins.h
similarity index 86%
rename from components/soc/soc/esp32/include/soc/pcnt_caps.h
rename to components/soc/soc/esp32s3/include/soc/gpio_pins.h
index 2d276092179..2edb3ae6912 100644
--- a/components/soc/soc/esp32/include/soc/pcnt_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/gpio_pins.h
@@ -12,16 +12,16 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+
 #pragma once
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-// ESP32 have 1 PCNT peripheral
-#define SOC_PCNT_PORT_NUM      (1)
-#define SOC_PCNT_UNIT_NUM      (8)
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
 
 #ifdef __cplusplus
 }
-#endif
+#endif
\ No newline at end of file
diff --git a/components/soc/soc/esp32s3/include/soc/i2c_caps.h b/components/soc/soc/esp32s3/include/soc/i2c_caps.h
index f95be82a5c3..f7c758d403e 100644
--- a/components/soc/soc/esp32s3/include/soc/i2c_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/i2c_caps.h
@@ -22,12 +22,11 @@ extern "C" {
 #define SOC_I2C_NUM            (2)
 
 #define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
-#define I2C_INTR_MASK          (0x3fff) /*!< I2C all interrupt bitmap */
 
 //ESP32-S3 support hardware FSM reset
-#define I2C_SUPPORT_HW_FSM_RST  (1)
+#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
 //ESP32-S3 support hardware clear bus
-#define I2C_SUPPORT_HW_CLR_BUS  (1)
+#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/esp32s3/include/soc/i2s_caps.h b/components/soc/soc/esp32s3/include/soc/i2s_caps.h
index bce5c0253e7..a0d476b1ad2 100644
--- a/components/soc/soc/esp32s3/include/soc/i2s_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/i2s_caps.h
@@ -14,13 +14,10 @@
 
 #pragma once
 
-#define APLL_MIN_FREQ                     (250000000)
-#define APLL_MAX_FREQ                     (500000000)
-#define APLL_I2S_MIN_RATE                 (10675) //in Hz, I2S Clock rate limited by hardware
-#define I2S_AD_BCK_FACTOR                 (2)
-#define I2S_PDM_BCK_FACTOR                (64)
-#define I2S_MAX_BUFFER_SIZE               (4 * 1024 * 1024) //the maximum RAM can be allocated
-#define I2S_BASE_CLK                      (2*APB_CLK_FREQ)
+#define SOC_I2S_APLL_MIN_FREQ                     (250000000)
+#define SOC_I2S_APLL_MAX_FREQ                     (500000000)
+#define SOC_I2S_APLL_MIN_RATE                 (10675) //in Hz, I2S Clock rate limited by hardware
+#define SOC_I2S_MAX_BUFFER_SIZE               (4 * 1024 * 1024) //the maximum RAM can be allocated
 
 // ESP32-S3 have 1 I2S
 #define SOC_I2S_NUM            (1)
diff --git a/components/soc/soc/esp32s3/include/soc/rtc_io_caps.h b/components/soc/soc/esp32s3/include/soc/rtc_io_caps.h
index 20f34d6fe01..e4438990795 100644
--- a/components/soc/soc/esp32s3/include/soc/rtc_io_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/rtc_io_caps.h
@@ -14,5 +14,5 @@
 
 #pragma once
 
-#define SOC_RTC_IO_PIN_COUNT   22
-#define SOC_PIN_FUNC_RTC_IO     0
\ No newline at end of file
+#define SOC_RTCIO_PIN_COUNT   22
+#define RTCIO_LL_PIN_FUNC     0
\ No newline at end of file
diff --git a/components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h b/components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h
index 0a3d99c2b13..0aa44b707f0 100644
--- a/components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h
@@ -18,20 +18,8 @@ extern "C" {
 #endif
 
 // ESP32-S3 have 1 SIGMADELTA peripheral.
-#define SIGMADELTA_PORT_0             (0) /*!< SIGMADELTA port 0 */
-#define SIGMADELTA_PORT_MAX           (1) /*!< SIGMADELTA port max */
 #define SOC_SIGMADELTA_NUM            (SIGMADELTA_PORT_MAX)
 
-#define SIGMADELTA_CHANNEL_0   (0)    /*!< Sigma-delta channel 0 */
-#define SIGMADELTA_CHANNEL_1   (1)    /*!< Sigma-delta channel 1 */
-#define SIGMADELTA_CHANNEL_2   (2)    /*!< Sigma-delta channel 2 */
-#define SIGMADELTA_CHANNEL_3   (3)    /*!< Sigma-delta channel 3 */
-#define SIGMADELTA_CHANNEL_4   (4)    /*!< Sigma-delta channel 4 */
-#define SIGMADELTA_CHANNEL_5   (5)    /*!< Sigma-delta channel 5 */
-#define SIGMADELTA_CHANNEL_6   (6)    /*!< Sigma-delta channel 6 */
-#define SIGMADELTA_CHANNEL_7   (7)    /*!< Sigma-delta channel 7 */
-#define SIGMADELTA_CHANNEL_MAX (8)
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/soc/esp32s3/include/soc/soc_caps.h b/components/soc/soc/esp32s3/include/soc/soc_caps.h
index e6225a11359..44cecec96bf 100644
--- a/components/soc/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/soc_caps.h
@@ -1,15 +1,76 @@
-// The long term plan is to have a single soc_caps.h for each peripheral.
+// The long term plan is to have a single soc_caps.h for all peripherals.
 // During the refactoring and multichip support development process, we
-// seperate these information into periph_caps.h for each peripheral and
-// include them here.
+// separate these information into periph_caps.h for each peripheral and
+// include them here to avoid developing conflicts.
 
 #pragma once
 
+/*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_TWAI_SUPPORTED 1
 #define SOC_GDMA_SUPPORTED 1
 #define SOC_CPU_CORES_NUM 2
 #define SOC_CACHE_SUPPORT_WRAP    1
 
+/*-------------------------- ADC CAPS ----------------------------------------*/
+#include "adc_caps.h"
+
+/*-------------------------- BROWNOUT CAPS -----------------------------------*/
+#include "brownout_caps.h"
+
+/*-------------------------- CPU CAPS ----------------------------------------*/
+#include "cpu_caps.h"
+
+/*-------------------------- DAC CAPS ----------------------------------------*/
+#include "dac_caps.h"
+
+/*-------------------------- GDMA CAPS ---------------------------------------*/
+#include "gdma_caps.h"
+
+/*-------------------------- GPIO CAPS ---------------------------------------*/
+#include "gpio_caps.h"
+
+/*-------------------------- I2C CAPS ----------------------------------------*/
+#include "i2c_caps.h"
+
+/*-------------------------- I2S CAPS ----------------------------------------*/
+#include "i2s_caps.h"
+
+/*-------------------------- LEDC CAPS ---------------------------------------*/
+#include "ledc_caps.h"
+
+/*-------------------------- MPU CAPS ----------------------------------------*/
+#include "mpu_caps.h"
+
+/*-------------------------- PCNT CAPS ---------------------------------------*/
+#include "pcnt_caps.h"
+
+/*-------------------------- RMT CAPS ----------------------------------------*/
+#include "rmt_caps.h"
+
+/*-------------------------- RTCIO CAPS --------------------------------------*/
+#include "rtc_io_caps.h"
+
+/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
+#include "sigmadelta_caps.h"
+
+/*-------------------------- SPI CAPS ----------------------------------------*/
+#include "spi_caps.h"
+
+/*-------------------------- SYS TIMER CAPS ----------------------------------*/
+#include "systimer_caps.h"
+
+/*-------------------------- TIMER GROUP CAPS --------------------------------*/
+#include "timer_group_caps.h"
+
+/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
+#include "touch_sensor_caps.h"
+
+/*-------------------------- TWAI CAPS ---------------------------------------*/
+#include "twai_caps.h"
+
+/*-------------------------- UART CAPS ---------------------------------------*/
+#include "uart_caps.h"
+
 // Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
 // Remove them when GDMA driver API is ready
 #define SOC_GDMA_M2M_DMA_CHANNEL  (0)
diff --git a/components/soc/soc/esp32s2/include/soc/brownout_caps.h b/components/soc/soc/esp32s3/include/soc/soc_pins.h
similarity index 61%
rename from components/soc/soc/esp32s2/include/soc/brownout_caps.h
rename to components/soc/soc/esp32s3/include/soc/soc_pins.h
index 797d33ebb9f..6a8101067aa 100644
--- a/components/soc/soc/esp32s2/include/soc/brownout_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/soc_pins.h
@@ -12,14 +12,15 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+/*
+ * Pin definition header file. The long term plan is to have a single soc_pins.h for all
+ * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
+ * peripheral and include them here to avoid developing conflicts in those header files.
+ */
+
 #pragma once
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SOC_BROWNOUT_RESET_SUPPORTED 1
-
-#ifdef __cplusplus
-}
-#endif
+#include "soc/gpio_pins.h"
+#include "soc/spi_pins.h"
+#include "soc/sdio_slave_pins.h"
+#include "soc/sdmmc_pins.h"
\ No newline at end of file
diff --git a/components/soc/soc/esp32s3/include/soc/spi_caps.h b/components/soc/soc/esp32s3/include/soc/spi_caps.h
index 79c19aaf56f..6cf5f5c36d0 100644
--- a/components/soc/soc/esp32s3/include/soc/spi_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/spi_caps.h
@@ -14,30 +14,10 @@
 
 #pragma once
 
-#define SOC_SPI_PERIPH_NUM      4
+#define SOC_SPI_PERIPH_NUM      3
 #define SOC_SPI_DMA_CHAN_NUM    3
 #define SOC_SPI_PERIPH_CS_NUM(i)    3
 
-#define SPI_FUNC_NUM            0
-#define SPI_IOMUX_PIN_NUM_HD    27
-#define SPI_IOMUX_PIN_NUM_CS    29
-#define SPI_IOMUX_PIN_NUM_MOSI  32
-#define SPI_IOMUX_PIN_NUM_CLK   30
-#define SPI_IOMUX_PIN_NUM_MISO  31
-#define SPI_IOMUX_PIN_NUM_WP    28
-//TODO: add the next slot
-
-#define FSPI_FUNC_NUM           4
-#define FSPI_IOMUX_PIN_NUM_HD   9
-#define FSPI_IOMUX_PIN_NUM_CS   10
-#define FSPI_IOMUX_PIN_NUM_MOSI 11
-#define FSPI_IOMUX_PIN_NUM_CLK  12
-#define FSPI_IOMUX_PIN_NUM_MISO 13
-#define FSPI_IOMUX_PIN_NUM_WP   14
-//TODO: add the next slot
-
-//HSPI and VSPI have no iomux pins
-
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE     72
 
 //#define SOC_SPI_SUPPORT_AS_CS         //don't support to toggle the CS while the clock toggles
diff --git a/components/soc/soc/esp32s3/include/soc/spi_pins.h b/components/soc/soc/esp32s3/include/soc/spi_pins.h
index 12f7aa639ec..8dc0cce28ee 100644
--- a/components/soc/soc/esp32s3/include/soc/spi_pins.h
+++ b/components/soc/soc/esp32s3/include/soc/spi_pins.h
@@ -14,22 +14,20 @@
 
 #pragma once
 
-#define SPI_PERIPH_NUM          3
-
-#define SPI_FUNC_NUM            2
+#define SPI_FUNC_NUM            0
 #define SPI_IOMUX_PIN_NUM_HD    27
 #define SPI_IOMUX_PIN_NUM_CS    29
 #define SPI_IOMUX_PIN_NUM_MOSI  32
 #define SPI_IOMUX_PIN_NUM_CLK   30
 #define SPI_IOMUX_PIN_NUM_MISO  31
 #define SPI_IOMUX_PIN_NUM_WP    28
-//TODO: add the next slot
 
-#define FSPI_FUNC_NUM           0
+#define FSPI_FUNC_NUM           4
 #define FSPI_IOMUX_PIN_NUM_HD   9
 #define FSPI_IOMUX_PIN_NUM_CS   10
 #define FSPI_IOMUX_PIN_NUM_MOSI 11
 #define FSPI_IOMUX_PIN_NUM_CLK  12
 #define FSPI_IOMUX_PIN_NUM_MISO 13
 #define FSPI_IOMUX_PIN_NUM_WP   14
-//TODO: add the next slot
+
+//HSPI have no iomux pins
diff --git a/components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h b/components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h
index 0860bd83846..9f92af6d58f 100644
--- a/components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h
@@ -19,9 +19,8 @@ extern "C" {
 #endif
 
 #define SOC_TOUCH_SENSOR_NUM                (15)
-#define SOC_TOUCH_SENSOR_BIT_MASK_MAX       (0x7fff)
 
-#define SOC_TOUCH_PAD_MEASURE_WAIT          (0xFF)
+#define SOC_TOUCH_PAD_MEASURE_WAIT_MAX          (0xFF)
 #define SOC_TOUCH_PAD_THRESHOLD_MAX         (0x1FFFFF)
 
 #define SOC_TOUCH_SHIELD_CHANNEL            (14)
diff --git a/components/soc/soc/esp32s3/include/soc/twai_caps.h b/components/soc/soc/esp32s3/include/soc/twai_caps.h
index 4ad5fbd8291..c9b304226ee 100644
--- a/components/soc/soc/esp32s3/include/soc/twai_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/twai_caps.h
@@ -18,8 +18,8 @@
 extern "C" {
 #endif
 
-#define TWAI_BRP_MIN                2
-#define TWAI_BRP_MAX                32768
+#define SOC_TWAI_BRP_MIN    2
+#define SOC_TWAI_BRP_MAX    32768
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/esp32s3/include/soc/uart_caps.h b/components/soc/soc/esp32s3/include/soc/uart_caps.h
index 767c067659c..395df10edd6 100644
--- a/components/soc/soc/esp32s3/include/soc/uart_caps.h
+++ b/components/soc/soc/esp32s3/include/soc/uart_caps.h
@@ -18,13 +18,11 @@
 extern "C" {
 #endif
 
-#define UART_FIFO_LEN          (128)      /*!< The UART hardware FIFO length */
-#define UART_BITRATE_MAX       (5000000)  /*!< Max bit rate supported by UART */
+#define SOC_UART_FIFO_LEN          (128)      /*!< The UART hardware FIFO length */
+#define SOC_UART_BITRATE_MAX       (5000000)  /*!< Max bit rate supported by UART */
 
 // ESP32-S3 have 2 UART
 #define SOC_UART_NUM           (2)
-#define SOC_UART_MIN_WAKEUP_THRESH (2)
-#define UART_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/esp32s3/rtc_io_periph.c b/components/soc/soc/esp32s3/rtc_io_periph.c
index b7c9eae3b47..47f502feb91 100644
--- a/components/soc/soc/esp32s3/rtc_io_periph.c
+++ b/components/soc/soc/esp32s3/rtc_io_periph.c
@@ -14,7 +14,7 @@
 
 #include "soc/rtc_io_periph.h"
 
-const int rtc_io_num_map[GPIO_PIN_COUNT] = {
+const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
     RTCIO_GPIO0_CHANNEL,    //GPIO0
     RTCIO_GPIO1_CHANNEL,    //GPIO1
     RTCIO_GPIO2_CHANNEL,    //GPIO2
@@ -66,7 +66,7 @@ const int rtc_io_num_map[GPIO_PIN_COUNT] = {
 };
 
 //Reg,Mux,Fun,IE,Up,Down,Rtc_number
-const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = {
+const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = {
     /*REG                    MUX select                    function select               Input enable                 Pullup                    Pulldown                  Sleep select                   Sleep input enable           Sleep output enable           PAD hold   Pad force hold              Mask of drive capability  Offset                    gpio number */
     {RTC_IO_TOUCH_PAD0_REG,  RTC_IO_TOUCH_PAD0_MUX_SEL_M,  RTC_IO_TOUCH_PAD0_FUN_SEL_S,  RTC_IO_TOUCH_PAD0_FUN_IE_M,  RTC_IO_TOUCH_PAD0_RUE_M,  RTC_IO_TOUCH_PAD0_RDE_M,  RTC_IO_TOUCH_PAD0_SLP_SEL_M,   RTC_IO_TOUCH_PAD0_SLP_IE_M,  RTC_IO_TOUCH_PAD0_SLP_OE_M,   0,         RTC_CNTL_TOUCH_PAD0_HOLD_M,  RTC_IO_TOUCH_PAD0_DRV_V,  RTC_IO_TOUCH_PAD0_DRV_S,  RTCIO_CHANNEL_0_GPIO_NUM}, //0
     {RTC_IO_TOUCH_PAD1_REG,  RTC_IO_TOUCH_PAD1_MUX_SEL_M,  RTC_IO_TOUCH_PAD1_FUN_SEL_S,  RTC_IO_TOUCH_PAD1_FUN_IE_M,  RTC_IO_TOUCH_PAD1_RUE_M,  RTC_IO_TOUCH_PAD1_RDE_M,  RTC_IO_TOUCH_PAD1_SLP_SEL_M,   RTC_IO_TOUCH_PAD1_SLP_IE_M,  RTC_IO_TOUCH_PAD1_SLP_OE_M,   0,         RTC_CNTL_TOUCH_PAD1_HOLD_M,  RTC_IO_TOUCH_PAD1_DRV_V,  RTC_IO_TOUCH_PAD1_DRV_S,  RTCIO_CHANNEL_1_GPIO_NUM}, //1
diff --git a/components/soc/soc/include/soc/adc_periph.h b/components/soc/soc/include/soc/adc_periph.h
index 2ac7e7d35bd..d3504ebce20 100644
--- a/components/soc/soc/include/soc/adc_periph.h
+++ b/components/soc/soc/include/soc/adc_periph.h
@@ -21,7 +21,7 @@
 #include "soc/rtc_io_struct.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/adc_channel.h"
-#include "soc/adc_caps.h"
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -29,7 +29,7 @@ extern "C" {
 
 /**
  * Store IO number corresponding to the ADC channel number.
- * 
+ *
  * @value
  *      - >=0 : GPIO number index.
  *      - -1  : Not support.
diff --git a/components/soc/soc/include/soc/dac_periph.h b/components/soc/soc/include/soc/dac_periph.h
index fe06f470488..bed3f22a661 100644
--- a/components/soc/soc/include/soc/dac_periph.h
+++ b/components/soc/soc/include/soc/dac_periph.h
@@ -20,7 +20,7 @@
 #include "soc/rtc_io_struct.h"
 #include "soc/rtc.h"
 #include "soc/dac_channel.h"
-#include "soc/dac_caps.h"
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C"
diff --git a/components/soc/soc/include/soc/gpio_periph.h b/components/soc/soc/include/soc/gpio_periph.h
index ee5d7c36ed8..ae0ed73ec9c 100644
--- a/components/soc/soc/include/soc/gpio_periph.h
+++ b/components/soc/soc/include/soc/gpio_periph.h
@@ -17,7 +17,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/gpio_struct.h"
 #include "soc/gpio_reg.h"
-#include "soc/gpio_caps.h"
+#include "soc/soc_caps.h"
 #include "soc/gpio_sig_map.h"
 
 #ifdef __cplusplus
@@ -25,9 +25,9 @@ extern "C"
 {
 #endif
 
-extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT];
+extern const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT];
 
-extern const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT];
+extern const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT];
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/include/soc/i2c_periph.h b/components/soc/soc/include/soc/i2c_periph.h
index 3f597c5d5bb..f56fbe29470 100644
--- a/components/soc/soc/include/soc/i2c_periph.h
+++ b/components/soc/soc/include/soc/i2c_periph.h
@@ -15,7 +15,7 @@
 
 #include "soc/i2c_reg.h"
 #include "soc/i2c_struct.h"
-#include "soc/i2c_caps.h"
+#include "soc/soc_caps.h"
 #include "soc/periph_defs.h"
 
 #ifdef __cplusplus
diff --git a/components/soc/soc/include/soc/i2s_periph.h b/components/soc/soc/include/soc/i2s_periph.h
index df72723a2fd..a2b9c542744 100644
--- a/components/soc/soc/include/soc/i2s_periph.h
+++ b/components/soc/soc/include/soc/i2s_periph.h
@@ -17,7 +17,7 @@
 #include "soc/periph_defs.h"
 #include "soc/i2s_struct.h"
 #include "soc/i2s_reg.h"
-#include "soc/i2s_caps.h"
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/soc/include/soc/ledc_periph.h b/components/soc/soc/include/soc/ledc_periph.h
index 4cfb5ac9da1..e53e90f01fc 100644
--- a/components/soc/soc/include/soc/ledc_periph.h
+++ b/components/soc/soc/include/soc/ledc_periph.h
@@ -13,9 +13,9 @@
 // limitations under the License.
 
 #pragma once
+#include "soc/soc_caps.h"
 #include "soc/ledc_reg.h"
 #include "soc/ledc_struct.h"
-#include "soc/ledc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/soc/include/soc/rtc_io_periph.h b/components/soc/soc/include/soc/rtc_io_periph.h
index a5f104f3d34..aca325f0118 100644
--- a/components/soc/soc/include/soc/rtc_io_periph.h
+++ b/components/soc/soc/include/soc/rtc_io_periph.h
@@ -16,14 +16,13 @@
 
 #include "soc/soc.h"
 //include soc related (generated) definitions
-#include "soc/rtc_io_caps.h"
+#include "soc/soc_caps.h"
 #include "soc/rtc_io_channel.h"
 #include "soc/rtc_io_reg.h"
 #include "soc/rtc_io_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/sens_struct.h"
-#include "soc/gpio_caps.h"
 
 #ifdef __cplusplus
 extern "C"
@@ -61,7 +60,7 @@ typedef struct {
  * This is an internal function of the driver, and is not usually useful
  * for external use.
  */
-extern const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT];
+extern const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT];
 
 /**
  * @brief Provides a constant table to get rtc io number with gpio number
@@ -69,7 +68,7 @@ extern const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT];
  * This is an internal function of the driver, and is not usually useful
  * for external use.
  */
-extern const int rtc_io_num_map[GPIO_PIN_COUNT];
+extern const int rtc_io_num_map[SOC_GPIO_PIN_COUNT];
 
 #ifdef CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC
 /**
diff --git a/components/soc/soc/include/soc/rtc_periph.h b/components/soc/soc/include/soc/rtc_periph.h
index 535245224dc..121dc597d9f 100644
--- a/components/soc/soc/include/soc/rtc_periph.h
+++ b/components/soc/soc/include/soc/rtc_periph.h
@@ -15,7 +15,7 @@
 #pragma once
 #include <stdint.h>
 #include "rtc_io_periph.h"
-#include "soc/gpio_caps.h"
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C"
diff --git a/components/soc/soc/include/soc/sdio_slave_periph.h b/components/soc/soc/include/soc/sdio_slave_periph.h
index 189f9075720..d39f72f5269 100644
--- a/components/soc/soc/include/soc/sdio_slave_periph.h
+++ b/components/soc/soc/include/soc/sdio_slave_periph.h
@@ -15,7 +15,7 @@
 #pragma once
 #include <stdint.h>
 //include soc related (generated) definitions
-#include "soc/sdio_slave_pins.h"
+#include "soc/soc_pins.h"
 #include "soc/slc_reg.h"
 #include "soc/slc_struct.h"
 #include "soc/host_reg.h"
diff --git a/components/soc/soc/include/soc/sdmmc_periph.h b/components/soc/soc/include/soc/sdmmc_periph.h
index 75499b0b408..7a64f4c5fe8 100644
--- a/components/soc/soc/include/soc/sdmmc_periph.h
+++ b/components/soc/soc/include/soc/sdmmc_periph.h
@@ -15,7 +15,7 @@
 #pragma once
 #include <stdint.h>
 //include soc related (generated) definitions
-#include "soc/sdmmc_pins.h"
+#include "soc/soc_pins.h"
 #include "soc/sdmmc_reg.h"
 #include "soc/sdmmc_struct.h"
 #include "soc/gpio_sig_map.h"
diff --git a/components/soc/soc/include/soc/spi_periph.h b/components/soc/soc/include/soc/spi_periph.h
index 79b637ced75..4ddb8b3f1ef 100644
--- a/components/soc/soc/include/soc/spi_periph.h
+++ b/components/soc/soc/include/soc/spi_periph.h
@@ -19,7 +19,8 @@
 #include "soc/periph_defs.h"
 
 //include soc related (generated) definitions
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
+#include "soc/soc_pins.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_struct.h"
 #include "soc/gpio_sig_map.h"
diff --git a/components/soc/soc/include/soc/touch_sensor_periph.h b/components/soc/soc/include/soc/touch_sensor_periph.h
index a1ebeafcd31..653d30138b5 100644
--- a/components/soc/soc/include/soc/touch_sensor_periph.h
+++ b/components/soc/soc/include/soc/touch_sensor_periph.h
@@ -14,8 +14,8 @@
 
 #pragma once
 
+#include "soc/soc_caps.h"
 #include "soc/touch_sensor_channel.h"
-#include "soc/touch_sensor_caps.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/sens_reg.h"
diff --git a/components/soc/soc/include/soc/twai_periph.h b/components/soc/soc/include/soc/twai_periph.h
index b59a4baea85..48fc1d8ea8d 100644
--- a/components/soc/soc/include/soc/twai_periph.h
+++ b/components/soc/soc/include/soc/twai_periph.h
@@ -20,8 +20,8 @@
 extern "C" {
 #endif
 
+#include "soc/soc_caps.h"
 #include "soc/twai_struct.h"
-#include "soc/twai_caps.h"
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/soc/include/soc/uart_periph.h b/components/soc/soc/include/soc/uart_periph.h
index 3ce864543be..61bd029ba6a 100644
--- a/components/soc/soc/include/soc/uart_periph.h
+++ b/components/soc/soc/include/soc/uart_periph.h
@@ -13,9 +13,9 @@
 
 #pragma once
 
+#include "soc/soc_caps.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
-#include "soc/uart_caps.h"
 #include "soc/periph_defs.h"
 #include "soc/gpio_sig_map.h"
 
diff --git a/examples/peripherals/sdio/host/main/app_main.c b/examples/peripherals/sdio/host/main/app_main.c
index 18f7b341fa7..7765b1bd5f5 100644
--- a/examples/peripherals/sdio/host/main/app_main.c
+++ b/examples/peripherals/sdio/host/main/app_main.c
@@ -276,7 +276,7 @@ void slave_power_on(void)
 #endif
     gpio_config_t cfg = {
         .pin_bit_mask = BIT64(GPIO_B1),
-        .mode = GPIO_MODE_DEF_OUTPUT,
+        .mode = GPIO_MODE_OUTPUT,
         .pull_up_en = false,
         .pull_down_en = false,
         .intr_type = GPIO_INTR_DISABLE,
diff --git a/examples/storage/nvs_rw_blob/main/nvs_blob_example_main.c b/examples/storage/nvs_rw_blob/main/nvs_blob_example_main.c
index 8541369eba1..4860b412a97 100644
--- a/examples/storage/nvs_rw_blob/main/nvs_blob_example_main.c
+++ b/examples/storage/nvs_rw_blob/main/nvs_blob_example_main.c
@@ -168,7 +168,7 @@ void app_main(void)
     if (err != ESP_OK) printf("Error (%s) saving restart counter to NVS!\n", esp_err_to_name(err));
 
     gpio_reset_pin(GPIO_NUM_0);
-    gpio_set_direction(GPIO_NUM_0, GPIO_MODE_DEF_INPUT);
+    gpio_set_direction(GPIO_NUM_0, GPIO_MODE_INPUT);
 
     /* Read the status of GPIO0. If GPIO0 is LOW for longer than 1000 ms,
        then save module's run time and restart it