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feat(phy): rename sleep modem state to sleep phy

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This commit is contained in:
cjin
2026-09-04 10:27:25 +08:00
parent e87eb3bd62
commit 639ae612ed
23 changed files with 148 additions and 146 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4 -4
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@@ -1443,10 +1443,6 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
bool
default y
config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
int
default 4
config SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY
bool
default y
@@ -1455,6 +1451,10 @@ config SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
bool
default y
config SOC_PM_PAU_REGDMA_LINK_IDX_PHY
int
default 4
config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1 -1
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@@ -585,10 +585,10 @@
#define SOC_PM_PAU_LINK_NUM (5)
#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
#define SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY (1)
/** Workaround: software-triggered modem PHY retention uses dedicated WiFi MAC REGDMA, not entry link_sel */
#define SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND (1)
#define SOC_PM_PAU_REGDMA_LINK_IDX_PHY (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED (1)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+1 -1
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@@ -1183,7 +1183,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
bool
default y
config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
config SOC_PM_PAU_REGDMA_LINK_MODEM
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+1 -1
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@@ -486,7 +486,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1)
#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC (1)
#define SOC_PM_PAU_REGDMA_LINK_MODEM (1)
#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1)
#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED (1)
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+1 -1
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@@ -1091,7 +1091,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
bool
default y
config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
config SOC_PM_PAU_REGDMA_LINK_MODEM
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
+1 -1
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@@ -450,7 +450,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1)
#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC (1)
#define SOC_PM_PAU_REGDMA_LINK_MODEM (1)
#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1)
#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED (1)
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+1 -1
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@@ -1131,7 +1131,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
bool
default y
config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
config SOC_PM_PAU_REGDMA_LINK_MODEM
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+1 -1
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@@ -487,7 +487,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1)
#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC (1)
#define SOC_PM_PAU_REGDMA_LINK_MODEM (1)
#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1)
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+1 -1
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@@ -1571,7 +1571,7 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
bool
default y
config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
config SOC_PM_PAU_REGDMA_LINK_IDX_PHY
int
default 4
components/soc/esp32s31/include/soc/soc_caps.h
+1 -1
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@@ -581,7 +581,7 @@
#define SOC_PM_PAU_LINK_NUM (5)
#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
#define SOC_PM_PAU_REGDMA_LINK_IDX_PHY (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
/** Workaround: software-triggered modem PHY retention uses dedicated WiFi MAC REGDMA, not entry link_sel */
#define SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND (1)