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refactor(gpio): split GPIO HAL into separate component

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cleaned up some includes in GPIO peripheral files
This commit is contained in:
Song Ruo Jing
2025-12-08 14:33:26 +08:00
parent c231e0e777
commit 62899cbba6
191 changed files with 377 additions and 336 deletions
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components/soc/esp32c5/dedic_gpio_periph.c
-36
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@@ -1,36 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_sig_map.h"
#include "soc/dedic_gpio_periph.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.irq = -1,
.cores = {
[0] = {
.in_sig_per_channel = {
[0] = CPU_GPIO_IN0_IDX,
[1] = CPU_GPIO_IN1_IDX,
[2] = CPU_GPIO_IN2_IDX,
[3] = CPU_GPIO_IN3_IDX,
[4] = CPU_GPIO_IN4_IDX,
[5] = CPU_GPIO_IN5_IDX,
[6] = CPU_GPIO_IN6_IDX,
[7] = CPU_GPIO_IN7_IDX,
},
.out_sig_per_channel = {
[0] = CPU_GPIO_OUT0_IDX,
[1] = CPU_GPIO_OUT1_IDX,
[2] = CPU_GPIO_OUT2_IDX,
[3] = CPU_GPIO_OUT3_IDX,
[4] = CPU_GPIO_OUT4_IDX,
[5] = CPU_GPIO_OUT5_IDX,
[6] = CPU_GPIO_OUT6_IDX,
[7] = CPU_GPIO_OUT7_IDX,
}
},
},
};
components/soc/esp32c5/gpio_periph.c
+1
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@@ -5,6 +5,7 @@
*/
#include "soc/gpio_periph.h"
#include "esp_bit_defs.h"
const uint32_t GPIO_HOLD_MASK[] = {
BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
components/soc/esp32c5/rtc_io_periph.c
-39
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@@ -1,39 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/rtc_io_periph.h"
const int8_t rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0
RTCIO_GPIO1_CHANNEL, //GPIO1
RTCIO_GPIO2_CHANNEL, //GPIO2
RTCIO_GPIO3_CHANNEL, //GPIO3
RTCIO_GPIO4_CHANNEL, //GPIO4
RTCIO_GPIO5_CHANNEL, //GPIO5
RTCIO_GPIO6_CHANNEL, //GPIO6
-1,//GPIO7
-1,//GPIO8
-1,//GPIO9
-1,//GPIO10
-1,//GPIO11
-1,//GPIO12
-1,//GPIO13
-1,//GPIO14
-1,//GPIO15
-1,//GPIO16
-1,//GPIO17
-1,//GPIO18
-1,//GPIO19
-1,//GPIO20
-1,//GPIO21
-1,//GPIO22
-1,//GPIO23
-1,//GPIO24
-1,//GPIO25
-1,//GPIO26
-1,//GPIO27
-1,//GPIO28
};
components/soc/esp32c5/sdm_periph.c
-58
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@@ -1,58 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/gpio_ext_reg.h"
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
.sig_id_matrix = GPIO_SD3_OUT_IDX
}
}
}
};
/**
* @brief Registers in retention context:
* GPIO_EXT_SIGMADELTA[x]_REG
* GPIO_EXT_SIGMADELTA_MISC_REG
*/
#define GPIO_EXT_RETENTION_REGS_CNT 5
#define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x4)
static const uint32_t gpio_ext_regs_map[4] = {0x1f, 0x0, 0x0, 0x0};
static const regdma_entries_config_t gpio_ext_regdma_entries[] = {
// backup stage: save configuration and status registers
// restore stage: restore the configuration and status registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_SDM_LINK(0x00),
GPIO_EXT_RETENTION_REGS_BASE, GPIO_EXT_RETENTION_REGS_BASE,
GPIO_EXT_RETENTION_REGS_CNT, 0, 0,
gpio_ext_regs_map[0], gpio_ext_regs_map[1],
gpio_ext_regs_map[2], gpio_ext_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2),
},
};
const soc_sdm_retention_desc_t soc_sdm_retention_infos[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_SDM0,
.regdma_entry_array = gpio_ext_regdma_entries,
.array_size = ARRAY_SIZE(gpio_ext_regdma_entries)
}
};