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https://github.com/espressif/esp-idf.git
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refactor(clk): split clock HAL into separate component
This commit is contained in:
Song Ruo Jing
@@ -0,0 +1,887 @@
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/*
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/chip_revision.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/hp_sys_clkrst_reg.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#include "soc/lp_clkrst_reg.h"
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#include "soc/lp_clkrst_struct.h"
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#include "soc/hp_alive_sys_reg.h"
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#include "soc/pmu_reg.h"
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// #include "hal/clkout_channel.h"
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#include "hal/assert.h"
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#include "hal/log.h"
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#include "esp32s31/rom/rtc.h"
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#include "hal/misc.h"
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#include "hal/efuse_hal.h"
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#define MHZ (1000000)
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#define CLK_LL_PLL_8M_FREQ_MHZ (8)
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#define CLK_LL_PLL_80M_FREQ_MHZ (80)
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#define CLK_LL_PLL_160M_FREQ_MHZ (160)
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#define CLK_LL_PLL_240M_FREQ_MHZ (240)
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#define CLK_LL_PLL_SDIO_FREQ_MHZ (200)
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#define CLK_LL_PLL_360M_FREQ_MHZ (360)
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#define CLK_LL_PLL_400M_FREQ_MHZ (400)
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#define CLK_LL_PLL_480M_FREQ_MHZ (480)
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#define CLK_LL_PLL_500M_FREQ_MHZ (500)
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/* APLL configuration parameters */
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#define CLK_LL_APLL_SDM_STOP_VAL_1 0x09
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#define CLK_LL_APLL_SDM_STOP_VAL_2_REV0 0x69
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#define CLK_LL_APLL_SDM_STOP_VAL_2_REV1 0x49
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/* APLL calibration parameters */
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#define CLK_LL_APLL_CAL_DELAY_1 0x0f
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#define CLK_LL_APLL_CAL_DELAY_2 0x3f
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#define CLK_LL_APLL_CAL_DELAY_3 0x1f
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/* APLL multiplier output frequency range */
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// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
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#define CLK_LL_APLL_MULTIPLIER_MIN_HZ (350000000) // 350 MHz
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#define CLK_LL_APLL_MULTIPLIER_MAX_HZ (500000000) // 500 MHz
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/* APLL output frequency range */
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#define CLK_LL_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
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#define CLK_LL_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
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#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
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.dac = 3, \
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.dres = 3, \
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.dgm = 3, \
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.dbuf = 1, \
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}
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief XTAL32K_CLK enable modes
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*/
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typedef enum {
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CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL, //!< Enable the external 32kHz crystal for XTAL32K_CLK
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CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP, //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */
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} clk_ll_xtal32k_enable_mode_t;
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/**
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* @brief XTAL32K_CLK configuration structure
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*/
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typedef struct {
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uint32_t dac : 6;
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uint32_t dres : 3;
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uint32_t dgm : 3;
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uint32_t dbuf: 1;
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} clk_ll_xtal32k_config_t;
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/**
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* @brief Power up CPLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpll_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Power down CPLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Power up APLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Power down APLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_apll_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Enable the internal oscillator output for LP_PLL_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_lp_pll_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Disable the internal oscillator output for LP_PLL_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_lp_pll_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Power up MPLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Power down MPLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_mpll_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Enable the 32kHz crystal oscillator
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*
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* @param mode Used to determine the xtal32k configuration parameters
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Disable the 32kHz crystal oscillator
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
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{
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// Disable xtal32k xpd
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//ESP32S31-TODO
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// CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
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}
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/**
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* @brief Get the state of the 32kHz crystal clock
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*
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* @return True if the 32kHz XTAL is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
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{
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//ESP32S31-TODO// TODO: [ESP32S31] IDF-14733
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return 0;
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}
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/**
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* @brief Enable the internal oscillator output for RC32K_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Disable the internal oscillator output for RC32K_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Get the state of the internal oscillator for RC32K_CLK
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*
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* @return True if the oscillator is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void)
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{
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//ESP32S31-TODO
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return 0;
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}
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/**
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* @brief Enable the internal oscillator output for RC_FAST_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Disable the internal oscillator output for RC_FAST_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Get the state of the internal oscillator for RC_FAST_CLK
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*
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* @return True if the oscillator is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
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{
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// TODO: [ESP32S31] IDF-14733
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return 0;// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Get the state of the digital RC_FAST_CLK
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*
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* @return True if the digital RC_FAST_CLK is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
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{
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return 0;
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Get the state of the digital XTAL32K_CLK
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*
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* @return True if the digital XTAL32K_CLK is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
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{
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return 0;
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Enable the digital RC32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Disable the digital RC32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Get the state of the digital RC32K_CLK
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*
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* @return True if the digital RC32K_CLK is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void)
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{
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return 0;
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Get CPLL_CLK frequency (only reliable when CPLL power is on)
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*
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* @param xtal_freq_mhz XTAL frequency, in MHz
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*
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* @return CPLL clock frequency, in MHz
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(uint32_t xtal_freq_mhz)
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{
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// TODO: [ESP32S31] IDF-14733
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return 0;
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}
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/**
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* @brief Set CPLL frequency from XTAL source (Digital part)
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*
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* @param cpll_freq_mhz CPLL frequency, in MHz
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpll_set_freq_mhz(uint32_t cpll_freq_mhz)
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{
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// Do nothing. CPLL frequency controlled by analog only on the target.
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(void)cpll_freq_mhz;
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}
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/**
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* @brief Set CPLL frequency from XTAL source (Analog part - through regi2c)
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*
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* @param cpll_freq_mhz CPLL frequency, in MHz
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* @param xtal_freq_mhz XTAL frequency, in MHz
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_t cpll_freq_mhz, uint32_t xtal_freq_mhz)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Get MPLL_CLK frequency (only reliable when MPLL power is on)
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*
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* @param xtal_freq_mhz XTAL frequency, in MHz
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*
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* @return MPLL clock frequency, in MHz
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_mpll_get_freq_mhz(uint32_t xtal_freq_mhz)
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{
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// uint8_t div = REGI2C_READ_MASK(I2C_MPLL, I2C_MPLL_DIV_ADDR);
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// uint8_t ref_div = REGI2C_READ_MASK(I2C_MPLL, I2C_MPLL_REF_DIV_ADDR);
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return 0;//xtal_freq_mhz * (div + 1) / (ref_div + 1);
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}
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/**
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* @brief Set MPLL frequency from XTAL source (Analog part - through regi2c)
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*
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* @param mpll_freq_mhz MPLL frequency, in MHz
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* @param xtal_freq_mhz XTAL frequency, in MHz
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*/
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static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_t mpll_freq_mhz, uint32_t xtal_freq_mhz)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Get APLL configuration which can be used to calculate APLL frequency
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*
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* @param[out] o_div Frequency divider, 0..31
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* @param[out] sdm0 Frequency adjustment parameter, 0..255
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* @param[out] sdm1 Frequency adjustment parameter, 0..255
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* @param[out] sdm2 Frequency adjustment parameter, 0..63
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*/
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static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Set APLL configuration
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*
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* @param o_div Frequency divider, 0..31
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* @param sdm0 Frequency adjustment parameter, 0..255
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* @param sdm1 Frequency adjustment parameter, 0..255
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* @param sdm2 Frequency adjustment parameter, 0..63
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*/
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static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Set APLL calibration parameters
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*/
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static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void)
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{
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// TODO: [ESP32S31] IDF-14733
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}
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/**
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* @brief Check whether APLL calibration is done
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*
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* @return True if calibration is done; otherwise false
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*/
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static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void)
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{
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// TODO: [ESP32S31] IDF-14733
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return 0;
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}
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/**
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* @brief To enable the change of cpu_div_num, mem_div_num, sys_div_num, and apb_div_num
|
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*/
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static inline __attribute__((always_inline)) void clk_ll_bus_update(void)
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||||
{
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HP_SYS_CLKRST.root_clk_ctrl0.reg_soc_clk_update = 1;
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while (HP_SYS_CLKRST.root_clk_ctrl0.reg_soc_clk_update);
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}
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/**
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* @brief Select the clock source for CPU_CLK (SOC Clock Root)
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*
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* @param in_sel One of the clock sources in soc_cpu_clk_src_t
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel)
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{
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// TODO: [ESP32S31] IDF-14733
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switch (in_sel) {
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case SOC_CPU_CLK_SRC_XTAL:
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||||
HP_SYS_CLKRST.soc_clk_sel.reg_soc_clk_sel = 0;
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break;
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case SOC_CPU_CLK_SRC_CPLL:
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HP_SYS_CLKRST.soc_clk_sel.reg_soc_clk_sel = 1;
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break;
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||||
case SOC_CPU_CLK_SRC_RC_FAST:
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||||
HP_SYS_CLKRST.soc_clk_sel.reg_soc_clk_sel = 2;
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||||
break;
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||||
default:
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||||
// Unsupported CPU_CLK mux input sel
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||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for CPU_CLK (SOC Clock Root)
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_cpu_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
uint32_t clk_sel = HP_SYS_CLKRST.soc_clk_sel.reg_soc_clk_sel;
|
||||
switch (clk_sel) {
|
||||
case 0:
|
||||
return SOC_CPU_CLK_SRC_XTAL;
|
||||
case 1:
|
||||
return SOC_CPU_CLK_SRC_CPLL;
|
||||
case 2:
|
||||
return SOC_CPU_CLK_SRC_RC_FAST;
|
||||
default:
|
||||
// Invalid HP_ROOT_CLK_SRC_SEL value
|
||||
return SOC_CPU_CLK_SRC_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CPU_CLK divider. freq of CPU_CLK = freq of HP_ROOT_CLK / divider
|
||||
*
|
||||
* @param integer Integer part of the divider
|
||||
* @param numerator Numerator part of the divider
|
||||
* @param denominator Denominator part of the divider
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t integer, uint32_t numerator, uint32_t denominator)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(integer >= 1 && integer <= HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V);
|
||||
HAL_ASSERT(numerator <= HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_V);
|
||||
HAL_ASSERT(denominator <= HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_V);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_num, integer - 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_numerator, numerator);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_denominator, denominator);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CPU_CLK divider
|
||||
*
|
||||
* @param integer Integer part of the divider
|
||||
* @param numerator Numerator part of the divider
|
||||
* @param denominator Denominator part of the divider
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_cpu_get_divider(uint32_t *integer, uint32_t *numerator, uint32_t *denominator)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
*integer = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_num) + 1;
|
||||
*numerator = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_numerator);
|
||||
*denominator = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.cpu_freq_ctrl0, reg_cpu_clk_div_denominator);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set MEM_CLK divider. freq of MEM_CLK = freq of CPU_CLK / divider
|
||||
*
|
||||
* ESP32P4 MEM_CLK supports fractional divnum (not supported in software yet)
|
||||
*
|
||||
* @note There is constraint on the mem divider. Hardware could change the actual divider if the configured value is
|
||||
* unachievable. Be careful on this. Check TRM or upper layer.
|
||||
*
|
||||
* @param divider Divider. CLK_DIV_NUM = divider - 1.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_mem_set_divider(uint32_t divider)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(divider >= 1 && divider <= 2); // We haven't confirmed the reliable functionality of cache when cpu_clk freq is more than 2 times faster than the cache clk freq. Need to verify before removing the constraint of divider <= 2.
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.mem_freq_ctrl0, reg_mem_clk_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get MEM_CLK divider
|
||||
*
|
||||
* Fractional divnum not used now.
|
||||
*
|
||||
* @return Divider. Divider = (CLK_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_mem_get_divider(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.mem_freq_ctrl0, reg_mem_clk_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SYS_CLK divider. freq of SYS_CLK = freq of MEM_CLK / divider
|
||||
*
|
||||
* ESP32P4 SYS_CLK supports fractional divnum (not supported in software yet)
|
||||
*
|
||||
* @param divider Divider. CLK_DIV_NUM = divider - 1.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_sys_set_divider(uint32_t divider)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(divider >= 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.sys_freq_ctrl0, reg_sys_clk_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SYS_CLK divider
|
||||
*
|
||||
* Fractional divnum not used now.
|
||||
*
|
||||
* @return Divider. Divider = (CLK_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_sys_get_divider(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.sys_freq_ctrl0, reg_sys_clk_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set APB_CLK divider. freq of APB_CLK = freq of SYS_CLK / divider
|
||||
*
|
||||
* ESP32P4 APB_CLK supports fractional divnum (not supported in software yet)
|
||||
*
|
||||
* @note There is constraint on the apb divider. Hardware could change the actual divider if the configured value is
|
||||
* unachievable. Be careful on this. Check TRM or upper layer.
|
||||
*
|
||||
* @param divider Divider. CLK_DIV_NUM = divider - 1.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(divider >= 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.apb_freq_ctrl0, reg_apb_clk_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get APB_CLK divider
|
||||
*
|
||||
* Fractional divnum not used now.
|
||||
*
|
||||
* @return Divider. Divider = (CLK_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.apb_freq_ctrl0, reg_apb_clk_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PLL_F50M_CLK divider. freq of PLL_F50M_CLK = freq of MPLL_CLK / divider
|
||||
*
|
||||
* @param divider Divider. CLK_DIV_NUM = divider - 1.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_pll_f50m_set_divider(uint32_t divider)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(divider >= 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.ref_50m_ctrl0, reg_ref_50m_clk_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PLL_F25M_CLK divider. freq of PLL_F25M_CLK = freq of MPLL_CLK / divider
|
||||
*
|
||||
* @param divider Divider. CLK_DIV_NUM = divider - 1.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_pll_f25m_set_divider(uint32_t divider)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(divider >= 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.ref_25m_ctrl0, reg_ref_25m_clk_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PLL_F20M_CLK divider. freq of PLL_F20M_CLK = freq of SPLL_CLK / divider
|
||||
*
|
||||
* @param divider Divider. CLK_DIV_NUM = divider - 1.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_pll_f20m_set_divider(uint32_t divider)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(divider >= 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.ref_20m_ctrl0, reg_ref_20m_clk_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PLL_F20M_CLK divider
|
||||
*
|
||||
* @return Divider. Divider = (CLK_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f20m_get_divider(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_20m_ctrl0, reg_ref_20m_clk_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the clock source for RTC_SLOW_CLK
|
||||
*
|
||||
* @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for RTC_SLOW_CLK
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the clock source for LP_PLL_CLK
|
||||
*
|
||||
* @param in_sel One of the clock sources in soc_lp_pll_clk_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for LP_PLL_CLK
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_lp_pll_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return SOC_LP_PLL_CLK_SRC_RC32K;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LP_PLL_CLK frequency
|
||||
*
|
||||
* @return LP_PLL clock frequency, in MHz
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_lp_pll_get_freq_mhz(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
// The target has a fixed 8MHz LP_PLL
|
||||
return CLK_LL_PLL_8M_FREQ_MHZ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the clock source for RTC_FAST_CLK
|
||||
*
|
||||
* @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for RTC_FAST_CLK
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return SOC_RTC_FAST_CLK_SRC_RC_FAST;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX.
|
||||
*
|
||||
* @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
|
||||
{
|
||||
// No divider on the target
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(divider == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RC_FAST_CLK divider
|
||||
*
|
||||
* @return Divider
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
|
||||
{
|
||||
// No divider on the target, always return divider = 1
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RC_SLOW_CLK divider
|
||||
*
|
||||
* @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
|
||||
{
|
||||
// No divider on the target
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
HAL_ASSERT(divider == 1);
|
||||
}
|
||||
|
||||
/************************** CLOCK OUTPUT **************************/
|
||||
// /**
|
||||
// * @brief Clock output channel configuration
|
||||
// *
|
||||
// * @param clk_sig The clock signal source to be mapped to GPIOs
|
||||
// * @param channel_id The clock output channel ID
|
||||
// */
|
||||
// static inline __attribute__((always_inline)) void clk_ll_bind_output_channel(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
|
||||
// {
|
||||
// if (channel_id == CLKOUT_CHANNEL_1) {
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch0_sel, clk_sig);
|
||||
// } else if (channel_id == CLKOUT_CHANNEL_2) {
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch1_sel, clk_sig);
|
||||
// } else {
|
||||
// abort();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /**
|
||||
// * @brief Enable the clock output channel
|
||||
// *
|
||||
// * @param channel_id The clock output channel ID
|
||||
// * @param enable Enable or disable the clock output channel
|
||||
// */
|
||||
// static inline __attribute__((always_inline)) void clk_ll_enable_output_channel(clock_out_channel_t channel_id, bool enable)
|
||||
// {
|
||||
// if (channel_id == CLKOUT_CHANNEL_1) {
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch0_en, enable);
|
||||
// } else if (channel_id == CLKOUT_CHANNEL_2) {
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch1_en, enable);
|
||||
// } else {
|
||||
// abort();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /**
|
||||
// * @brief Output the mapped clock after frequency division
|
||||
// *
|
||||
// * @param channel_id The clock output channel ID
|
||||
// * @param divider Clock frequency division value
|
||||
// */
|
||||
// static inline __attribute__((always_inline)) void clk_ll_set_output_channel_divider(clock_out_channel_t channel_id, uint32_t div_num)
|
||||
// {
|
||||
// if (channel_id == CLKOUT_CHANNEL_1) {
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch0_div_num, div_num - 1);
|
||||
// } else if (channel_id == CLKOUT_CHANNEL_2) {
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch1_div_num, div_num - 1);
|
||||
// } else {
|
||||
// abort();
|
||||
// }
|
||||
// }
|
||||
|
||||
/************************** LP STORAGE REGISTER STORE/LOAD **************************/
|
||||
/**
|
||||
* @brief Store XTAL_CLK frequency in RTC storage register
|
||||
*
|
||||
* Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
|
||||
* halves. These are the routines to work with that representation.
|
||||
*
|
||||
* @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
|
||||
* otherwise there will be a conflict with the low bit, which is used to disable logs
|
||||
* in the ROM code.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load XTAL_CLK frequency from RTC storage register
|
||||
*
|
||||
* Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
|
||||
* halves. These are the routines to work with that representation.
|
||||
*
|
||||
* @return XTAL frequency, in MHz. Returns 0 if value in reg is invalid.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store RTC_SLOW_CLK calibration value in RTC storage register
|
||||
*
|
||||
* Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds,
|
||||
* in Q13.19 fixed-point format).
|
||||
*
|
||||
* @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register
|
||||
*
|
||||
* This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches
|
||||
*
|
||||
* @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
return REG_READ(RTC_SLOW_CLK_CAL_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load the rtc_fix_ticks from RTC storage register
|
||||
*
|
||||
* @return The value used to correct the time obtained from the rtc timer when the calibration value changes
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void)
|
||||
{
|
||||
return 0;// TODO: [ESP32S31] IDF-14733
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store rtc_fix_us in RTC storage register
|
||||
*
|
||||
* @param rtc_fix_us The value used to correct the time obtained from the rtc timer when the calibration value changes
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14733
|
||||
}
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user