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https://github.com/espressif/esp-idf.git
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refactor(clk): split clock HAL into separate component
This commit is contained in:
Song Ruo Jing
@@ -0,0 +1,79 @@
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/*
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/assert.h"
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
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{
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switch (cpu_clk_src) {
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case SOC_CPU_CLK_SRC_XTAL:
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return clk_hal_xtal_get_freq_mhz();
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case SOC_CPU_CLK_SRC_PLL_F160M:
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return CLK_LL_PLL_160M_FREQ_MHZ;
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case SOC_CPU_CLK_SRC_PLL_F240M:
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return CLK_LL_PLL_240M_FREQ_MHZ;
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case SOC_CPU_CLK_SRC_RC_FAST:
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return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
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default:
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// Unknown CPU_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_cpu_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t divider = clk_ll_cpu_get_divider();
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
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}
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uint32_t clk_hal_ahb_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t divider = clk_ll_ahb_get_divider();
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
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}
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uint32_t clk_hal_apb_get_freq_hz(void)
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{
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return clk_hal_ahb_get_freq_hz() / clk_ll_apb_get_divider();
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}
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uint32_t clk_hal_lp_slow_get_freq_hz(void)
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{
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switch (clk_ll_rtc_slow_get_src()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
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return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
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return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
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return SOC_CLK_OSC_SLOW_FREQ_APPROX;
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default:
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// Unknown RTC_SLOW_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_xtal_get_freq_mhz(void)
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{
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uint32_t freq = clk_ll_xtal_get_freq_mhz();
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HAL_ASSERT(freq == SOC_XTAL_FREQ_48M || freq == SOC_XTAL_FREQ_40M);
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return freq;
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}
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void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
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{
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clk_ll_bind_output_channel(clk_sig, channel_id);
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}
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void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
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{
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clk_ll_bind_output_channel(0, channel_id);
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}
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@@ -0,0 +1,234 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/reset_reasons.h"
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#include "soc/pcr_struct.h"
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#include "soc/ahb_dma_struct.h"
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#include "soc/lpperi_struct.h"
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#include "soc/uart_struct.h"
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#include "soc/tee_struct.h"
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#include "soc/lp_gpio_struct.h"
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#include "soc/lp_tee_struct.h"
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#include "soc/lp_apm_struct.h"
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#include "soc/lp_apm0_struct.h"
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#include "soc/hp_apm_struct.h"
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#include "soc/cpu_apm_struct.h"
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#include "soc/usb_serial_jtag_struct.h"
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#include "soc/lp_clkrst_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Enable or disable the clock gate for ref_12m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_12m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_12m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_12m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_12m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for ref_20m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_20m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_20m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_20m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_20m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for ref_40m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_40m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_40m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_40m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_40m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for ref_48m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_48m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_48m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_48m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_48m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for ref_60m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_60m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_60m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_60m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_60m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for ref_80m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_80m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_80m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_80m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_80m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for ref_120m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_120m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_120m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_120m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_120m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for ref_160m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_160m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_160m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_160m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_160m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for ref_240m.
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_ref_240m_clk_en(bool enable)
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{
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PCR.pll_div_clk_en.pll_240m_clk_en = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_ref_240m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_240m_clk_en(__VA_ARGS__)
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/**
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* Enable or disable the clock gate for rtc_fast to lp periph
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* @param enable Enable / disable
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*/
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FORCE_INLINE_ATTR void _clk_gate_ll_rtc_fast_to_lp_periph_en(bool enable)
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{
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LP_CLKRST.lp_clk_en.fast_ori_gate = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define clk_gate_ll_rtc_fast_to_lp_periph_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_rtc_fast_to_lp_periph_en(__VA_ARGS__)
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/**
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* @brief Configuration structure for peripheral clock gate settings
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*/
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typedef struct {
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bool disable_uart0_clk; ///< Disable UART0 clock (when UART0 is not console)
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bool disable_uart1_clk; ///< Disable UART1 clock (when UART1 is not console)
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bool disable_mspi_flash_clk; ///< Disable MSPI flash clock (for PURE_RAM_APP)
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bool disable_crypto_periph_clk; ///< Disable crypto peripherals clock when TEE is not enabled
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bool disable_usb_serial_jtag; ///< Disable USB-Serial-JTAG clock and pad (when not enabled)
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} periph_ll_clk_gate_config_t;
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/**
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* @brief Set the default clock gate configuration
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* @param config The configuration structure
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*/
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static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason, const periph_ll_clk_gate_config_t *config)
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{
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if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \
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&& (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \
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&& (rst_reason != RESET_REASON_CPU0_JTAG) && (rst_reason != RESET_REASON_CPU0_LOCKUP)) {
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if (config->disable_uart0_clk) {
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PCR.uart0_conf.uart0_clk_en = 0;
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PCR.uart0_sclk_conf.uart0_sclk_en = 0;
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}
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else if (config->disable_uart1_clk) {
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PCR.uart1_sclk_conf.uart1_sclk_en = 0;
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PCR.uart1_conf.uart1_clk_en = 0;
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}
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PCR.timergroup_xtal_conf.tg0_xtal_clk_en = 0;
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PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = 0;
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PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = 0;
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PCR.timergroup0_conf.tg0_clk_en = 0;
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PCR.timergroup1_conf.tg1_clk_en = 0;
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PCR.gdma_conf.gdma_clk_en = 0;
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if (config->disable_mspi_flash_clk) {
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PCR.mspi_conf.mspi_clk_en = 0;
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}
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PCR.spi2_conf.spi2_clk_en = 0;
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if (config->disable_crypto_periph_clk) {
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TEE.clock_gate.clk_en = 0;
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LP_TEE.clock_gate.clk_en = 0;
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HP_APM.clock_gate.clk_en = 0;
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CPU_APM.clock_gate.clk_en = 0;
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}
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PCR.uhci_conf.uhci_clk_en = 0;
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PCR.tcm_mem_monitor_conf.tcm_mem_monitor_clk_en = 0;
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PCR.psram_mem_monitor_conf.psram_mem_monitor_clk_en = 0;
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PCR.ctrl_clk_out_en.val = 0;
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if (config->disable_usb_serial_jtag) {
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// Disable USB-Serial-JTAG clock and it's pad if not used
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USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
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PCR.usb_device_conf.usb_device_clk_en = 0;
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USB_SERIAL_JTAG.mem_conf.usb_mem_clk_en = 0;
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USB_SERIAL_JTAG.mem_conf.usb_mem_pd = 1;
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}
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}
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if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \
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|| (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \
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|| (rst_reason == RESET_REASON_CORE_PWR_GLITCH)) {
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LP_GPIO.clock_gate.clk_en = 0;
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LP_UART.clk_conf.val = 0;
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LPPERI.clk_en.val = 0;
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LPPERI.clk_en.efuse_ck_en = 1; // keep efuse clock enabled
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if (config->disable_crypto_periph_clk) {
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LP_APM.clock_gate.clk_en = 0;
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LP_APM0.clock_gate.clk_en = 0;
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}
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LP_CLKRST.lp_clk_po_en.val = 0;
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}
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,714 @@
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/*
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* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/pcr_reg.h"
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#include "soc/pcr_struct.h"
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#include "soc/lp_clkrst_struct.h"
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#include "soc/pmu_reg.h"
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#include "soc/pmu_struct.h"
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#include "soc/chip_revision.h"
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#include "soc/gpio_ext_reg.h"
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#include "hal/clkout_channel.h"
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#include "hal/regi2c_ctrl.h"
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#include "soc/regi2c_bbpll.h"
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#include "hal/assert.h"
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#include "hal/log.h"
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#include "esp32c5/rom/rtc.h"
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#include "hal/misc.h"
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#include "hal/efuse_hal.h"
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#define MHZ (1000000)
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#define CLK_LL_PLL_80M_FREQ_MHZ (80)
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#define CLK_LL_PLL_120M_FREQ_MHZ (120)
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#define CLK_LL_PLL_160M_FREQ_MHZ (160)
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#define CLK_LL_PLL_240M_FREQ_MHZ (240)
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#define CLK_LL_PLL_480M_FREQ_MHZ (480)
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#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
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.dac = 3, \
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.dres = 3, \
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.dgm = 3, \
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.dbuf = 1, \
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}
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// Fix default division factor for the RC_FAST clock for calibration to be 32
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#define CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS 5
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief XTAL32K_CLK enable modes
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*/
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typedef enum {
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CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL, //!< Enable the external 32kHz crystal for XTAL32K_CLK
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CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL, //!< Enable the external clock signal for OSC_SLOW_CLK
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CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP, //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */
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} clk_ll_xtal32k_enable_mode_t;
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/**
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* @brief XTAL32K_CLK configuration structure
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*/
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typedef struct {
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uint32_t dac : 6;
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uint32_t dres : 3;
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uint32_t dgm : 3;
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uint32_t dbuf: 1;
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} clk_ll_xtal32k_config_t;
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/**
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* @brief Power up BBPLL circuit
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||||
*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
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||||
{
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||||
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BB_I2C |
|
||||
PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C);
|
||||
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Power down BBPLL circuit
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG) ;
|
||||
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_BBPLL | PMU_TIE_LOW_XPD_BBPLL_I2C);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release the root clock source locked by PMU
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_cpu_clk_src_lock_release(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(PMU_IMM_SLEEP_SYSCLK_REG, PMU_UPDATE_DIG_SYS_CLK_SEL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the 32kHz crystal oscillator
|
||||
*
|
||||
* @param mode Used to determine the xtal32k configuration parameters
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
|
||||
{
|
||||
if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) {
|
||||
// No need to configure anything for OSC_SLOW_CLK
|
||||
return;
|
||||
}
|
||||
// Configure xtal32k
|
||||
clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT();
|
||||
LP_CLKRST.xtal32k.dac_xtal32k = cfg.dac;
|
||||
LP_CLKRST.xtal32k.dres_xtal32k = cfg.dres;
|
||||
LP_CLKRST.xtal32k.dgm_xtal32k = cfg.dgm;
|
||||
LP_CLKRST.xtal32k.dbuf_xtal32k = cfg.dbuf;
|
||||
// Enable xtal32k xpd
|
||||
SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the 32kHz crystal oscillator
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
|
||||
{
|
||||
// Disable xtal32k xpd
|
||||
CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the state of the 32kHz crystal clock
|
||||
*
|
||||
* @return True if the 32kHz XTAL is enabled
|
||||
*/
|
||||
static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
|
||||
{
|
||||
return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the internal oscillator output for RC_FAST_CLK
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the internal oscillator output for RC_FAST_CLK
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the state of the internal oscillator for RC_FAST_CLK
|
||||
*
|
||||
* @return True if the oscillator is enabled
|
||||
*/
|
||||
static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
|
||||
{
|
||||
return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
|
||||
{
|
||||
LP_CLKRST.clk_to_hp.icg_hp_fosc = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
|
||||
{
|
||||
LP_CLKRST.clk_to_hp.icg_hp_fosc = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the state of the digital RC_FAST_CLK
|
||||
*
|
||||
* @return True if the digital RC_FAST_CLK is enabled
|
||||
*/
|
||||
static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
|
||||
{
|
||||
return LP_CLKRST.clk_to_hp.icg_hp_fosc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
|
||||
{
|
||||
LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
|
||||
{
|
||||
LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the state of the digital XTAL32K_CLK
|
||||
*
|
||||
* @return True if the digital XTAL32K_CLK is enabled
|
||||
*/
|
||||
static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
|
||||
{
|
||||
return LP_CLKRST.clk_to_hp.icg_hp_xtal32k;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get XTAL_CLK frequency
|
||||
*
|
||||
* PCR_CLK_XTAL_FREQ updates its value based on EFUSE_XTAL_48M_SEL.
|
||||
*
|
||||
* @return Main XTAL clock frequency, in MHz.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(void)
|
||||
{
|
||||
return PCR.sysclk_conf.clk_xtal_freq;
|
||||
}
|
||||
|
||||
#define clk_ll_xtal_load_freq_mhz() clk_ll_xtal_get_freq_mhz()
|
||||
|
||||
/**
|
||||
* @brief Get SPLL_CLK frequency
|
||||
*
|
||||
* @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
|
||||
{
|
||||
// The target has a fixed 480MHz SPLL
|
||||
return CLK_LL_PLL_480M_FREQ_MHZ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SPLL frequency from XTAL source (Digital part)
|
||||
*
|
||||
* @param pll_freq_mhz PLL frequency, in MHz
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz)
|
||||
{
|
||||
// The target SPLL is fixed to 480MHz
|
||||
// Do nothing
|
||||
HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SPLL frequency from XTAL source (Analog part)
|
||||
*
|
||||
* @param pll_freq_mhz PLL frequency, in MHz
|
||||
* @param xtal_freq_mhz XTAL frequency, in MHz
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
|
||||
{
|
||||
HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ);
|
||||
uint8_t div_ref;
|
||||
uint8_t div7_0;
|
||||
uint8_t dr1;
|
||||
uint8_t dr3;
|
||||
uint8_t dchgp = 5;
|
||||
uint8_t dbias = 3;
|
||||
uint8_t href = 3;
|
||||
uint8_t lref = 1;
|
||||
|
||||
/* Configure 480M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case SOC_XTAL_FREQ_48M:
|
||||
div_ref = 1;
|
||||
div7_0 = 10;
|
||||
dr1 = 1;
|
||||
dr3 = 1;
|
||||
break;
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
div_ref = 1;
|
||||
div7_0 = 12;
|
||||
dr1 = 0;
|
||||
dr3 = 0;
|
||||
break;
|
||||
default:
|
||||
div_ref = 1;
|
||||
div7_0 = 12;
|
||||
dr1 = 0;
|
||||
dr3 = 0;
|
||||
break;
|
||||
}
|
||||
uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
|
||||
uint8_t i2c_bbpll_div_7_0 = div7_0;
|
||||
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
|
||||
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
|
||||
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
|
||||
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
|
||||
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, lref);
|
||||
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, href);
|
||||
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_bus_update(void)
|
||||
{
|
||||
PCR.bus_clk_update.bus_clock_update = 1;
|
||||
while (PCR.bus_clk_update.bus_clock_update);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the clock source for CPU_CLK (SOC Clock Root)
|
||||
*
|
||||
* @param in_sel One of the clock sources in soc_cpu_clk_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel)
|
||||
{
|
||||
switch (in_sel) {
|
||||
case SOC_CPU_CLK_SRC_XTAL:
|
||||
PCR.sysclk_conf.soc_clk_sel = 0;
|
||||
break;
|
||||
case SOC_CPU_CLK_SRC_RC_FAST:
|
||||
PCR.sysclk_conf.soc_clk_sel = 1;
|
||||
break;
|
||||
case SOC_CPU_CLK_SRC_PLL_F160M:
|
||||
PCR.sysclk_conf.soc_clk_sel = 2;
|
||||
break;
|
||||
case SOC_CPU_CLK_SRC_PLL_F240M:
|
||||
PCR.sysclk_conf.soc_clk_sel = 3;
|
||||
break;
|
||||
default:
|
||||
// Unsupported SOC_CLK mux input sel
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for CPU_CLK (SOC Clock Root)
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_cpu_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void)
|
||||
{
|
||||
uint32_t clk_sel = PCR.sysclk_conf.soc_clk_sel;
|
||||
switch (clk_sel) {
|
||||
case 0:
|
||||
return SOC_CPU_CLK_SRC_XTAL;
|
||||
case 1:
|
||||
return SOC_CPU_CLK_SRC_RC_FAST;
|
||||
case 2:
|
||||
return SOC_CPU_CLK_SRC_PLL_F160M;
|
||||
case 3:
|
||||
return SOC_CPU_CLK_SRC_PLL_F240M;
|
||||
default:
|
||||
// Invalid SOC_CLK_SEL value
|
||||
return SOC_CPU_CLK_SRC_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CPU_CLK's divider
|
||||
*
|
||||
* SOC_ROOT_CLK ------> CPU_CLK
|
||||
*
|
||||
* @param divider Divider. (PCR_CPU_DIV_NUM + 1) = divider.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider)
|
||||
{
|
||||
HAL_ASSERT(divider >= 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, (divider) - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CPU_CLK's divider
|
||||
*
|
||||
* @return Divider. Divider = (PCR_CPU_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set AHB_CLK's divider
|
||||
*
|
||||
* SOC_ROOT_CLK ------> AHB_CLK
|
||||
* Constraint: f_ahb <= 48 MHz, f_cpu = n * f_ahb
|
||||
*
|
||||
* @param divider Divider. (PCR_AHB_DIV_NUM + 1) = divider.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider)
|
||||
{
|
||||
HAL_ASSERT(divider >= 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AHB_CLK's divider
|
||||
*
|
||||
* @return Divider. Divider = (PCR_AHB_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider
|
||||
*
|
||||
* @param divider Divider. PCR_APB_DIV_NUM = divider - 1.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider)
|
||||
{
|
||||
// AHB ------> APB
|
||||
// Divider option: 1, 2, 4 (PCR_APB_DIV_NUM=0, 1, 3)
|
||||
HAL_ASSERT(divider == 1 || divider == 2 || divider == 4);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get APB_CLK divider
|
||||
*
|
||||
* @return Divider. Divider = (PCR_APB_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the soc root clock auto gating logic
|
||||
*
|
||||
* @param ena true to enable, false to disable
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_soc_root_clk_auto_gating_bypass(bool ena)
|
||||
{
|
||||
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
|
||||
if (ena) {
|
||||
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
|
||||
} else {
|
||||
REG_SET_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC clock calibration reference XTAL source on timer group0.
|
||||
* @param enable Enable or disable the XTAL source.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_enable_timergroup_rtc_calibration_clock(bool enable)
|
||||
{
|
||||
PCR.timergroup_xtal_conf.tg0_xtal_clk_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the frequency calculation clock source for timergroup0
|
||||
*
|
||||
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
|
||||
{
|
||||
int timg_cali_clk_sel = -1;
|
||||
|
||||
switch (clk_sel) {
|
||||
case CLK_CAL_32K_XTAL:
|
||||
timg_cali_clk_sel = 1;
|
||||
break;
|
||||
case CLK_CAL_32K_OSC_SLOW:
|
||||
timg_cali_clk_sel = 2;
|
||||
break;
|
||||
case CLK_CAL_RC_SLOW:
|
||||
timg_cali_clk_sel = 3;
|
||||
break;
|
||||
case CLK_CAL_RC_FAST:
|
||||
timg_cali_clk_sel = 4;
|
||||
break;
|
||||
default:
|
||||
// Unsupported CLK_CAL mux input
|
||||
abort();
|
||||
}
|
||||
|
||||
if (timg_cali_clk_sel >= 0) {
|
||||
PCR.ctrl_32k_conf.clk_32k_sel = timg_cali_clk_sel;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the frequency division factor of RC_FAST clock
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the clock source for RTC_SLOW_CLK
|
||||
*
|
||||
* @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
|
||||
{
|
||||
switch (in_sel) {
|
||||
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
|
||||
LP_CLKRST.lp_clk_conf.slow_clk_sel = 0;
|
||||
break;
|
||||
case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
|
||||
LP_CLKRST.lp_clk_conf.slow_clk_sel = 1;
|
||||
break;
|
||||
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
|
||||
LP_CLKRST.lp_clk_conf.slow_clk_sel = 3;
|
||||
break;
|
||||
default:
|
||||
// Unsupported RTC_SLOW_CLK mux input sel
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for RTC_SLOW_CLK
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
|
||||
{
|
||||
uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel;
|
||||
switch (clk_sel) {
|
||||
case 0:
|
||||
return SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
|
||||
case 1:
|
||||
return SOC_RTC_SLOW_CLK_SRC_XTAL32K;
|
||||
case 3:
|
||||
return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW;
|
||||
default:
|
||||
return SOC_RTC_SLOW_CLK_SRC_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the clock source for RTC_FAST_CLK
|
||||
*
|
||||
* @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
|
||||
{
|
||||
switch (in_sel) {
|
||||
case SOC_RTC_FAST_CLK_SRC_RC_FAST:
|
||||
LP_CLKRST.lp_clk_conf.fast_clk_sel = 0;
|
||||
break;
|
||||
case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
|
||||
LP_CLKRST.lp_clk_conf.fast_clk_sel = 1;
|
||||
break;
|
||||
case SOC_RTC_FAST_CLK_SRC_XTAL:
|
||||
LP_CLKRST.lp_clk_conf.fast_clk_sel = 2;
|
||||
break;
|
||||
default:
|
||||
// Unsupported RTC_FAST_CLK mux input sel
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for RTC_FAST_CLK
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
|
||||
{
|
||||
uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel;
|
||||
switch (clk_sel) {
|
||||
case 0:
|
||||
return SOC_RTC_FAST_CLK_SRC_RC_FAST;
|
||||
case 1:
|
||||
return SOC_RTC_FAST_CLK_SRC_XTAL_D2;
|
||||
case 2:
|
||||
return SOC_RTC_FAST_CLK_SRC_XTAL;
|
||||
default:
|
||||
return SOC_RTC_FAST_CLK_SRC_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX.
|
||||
*
|
||||
* @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
|
||||
{
|
||||
// No divider on the target
|
||||
HAL_ASSERT(divider == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RC_FAST_CLK divider
|
||||
*
|
||||
* @return Divider
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
|
||||
{
|
||||
// No divider on the target, always return divider = 1
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RC_SLOW_CLK divider
|
||||
*
|
||||
* @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
|
||||
{
|
||||
// No divider on the target
|
||||
HAL_ASSERT(divider == 1);
|
||||
}
|
||||
|
||||
/************************** CLOCK OUTPUT **************************/
|
||||
/**
|
||||
* @brief Clock output channel configuration
|
||||
*
|
||||
* @param clk_sig The clock signal source to be mapped to GPIOs
|
||||
* @param channel_id The clock output channel ID
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_bind_output_channel(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
|
||||
{
|
||||
SET_PERI_REG_BITS(GPIO_EXT_PIN_CTRL_REG, CLKOUT_CHANNEL_MASK(channel_id), clk_sig, CLKOUT_CHANNEL_SHIFT(channel_id));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the clock output channel
|
||||
*
|
||||
* @param channel_id The clock output channel ID
|
||||
* @param enable Enable or disable the clock output channel
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_enable_output_channel(clock_out_channel_t channel_id, bool enable)
|
||||
{
|
||||
// No such gating on the target
|
||||
(void)channel_id;
|
||||
(void)enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Output the mapped clock after frequency division
|
||||
*
|
||||
* @param channel_id The clock output channel ID
|
||||
* @param divider Clock frequency division value
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_set_output_channel_divider(clock_out_channel_t channel_id, uint32_t divider)
|
||||
{
|
||||
// No divider on the target
|
||||
HAL_ASSERT(divider == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the clock gate for clock output signal source
|
||||
*
|
||||
* @param clk_src The clock output signal source
|
||||
* @param en Enable or disable the clock output signal source
|
||||
*/
|
||||
static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
|
||||
{
|
||||
switch (clk_src) {
|
||||
case CLKOUT_SIG_PLL_F22M:
|
||||
PCR.ctrl_clk_out_en.clk22_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F44M:
|
||||
PCR.ctrl_clk_out_en.clk44_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F40M:
|
||||
PCR.ctrl_clk_out_en.clk_bb_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F80M:
|
||||
PCR.ctrl_clk_out_en.clk80_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F160M:
|
||||
PCR.ctrl_clk_out_en.clk160_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F480M:
|
||||
PCR.ctrl_clk_out_en.clk_480m_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_XTAL:
|
||||
PCR.ctrl_clk_out_en.clk_xtal_oen = en;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/************************** LP STORAGE REGISTER STORE/LOAD **************************/
|
||||
/**
|
||||
* @brief Store RTC_SLOW_CLK calibration value in RTC storage register
|
||||
*
|
||||
* Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds,
|
||||
* in Q13.19 fixed-point format).
|
||||
*
|
||||
* @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
|
||||
{
|
||||
REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register
|
||||
*
|
||||
* This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches
|
||||
*
|
||||
* @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
|
||||
{
|
||||
return REG_READ(RTC_SLOW_CLK_CAL_REG);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_assert.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/gpio_ext_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum clock_out_channel {
|
||||
CLKOUT_CHANNEL_1,
|
||||
CLKOUT_CHANNEL_2,
|
||||
CLKOUT_CHANNEL_3,
|
||||
CLKOUT_CHANNEL_MAX,
|
||||
} clock_out_channel_t;
|
||||
|
||||
#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
|
||||
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
|
||||
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
|
||||
|
||||
#define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? GPIO_EXT_CLK_OUT1 : \
|
||||
(channel == CLKOUT_CHANNEL_2) ? GPIO_EXT_CLK_OUT2 : \
|
||||
(channel == CLKOUT_CHANNEL_3) ? GPIO_EXT_CLK_OUT3 : 0)
|
||||
|
||||
#define CLKOUT_CHANNEL_SHIFT(channel) ((channel == CLKOUT_CHANNEL_1) ? GPIO_EXT_CLK_OUT1_S : \
|
||||
(channel == CLKOUT_CHANNEL_2) ? GPIO_EXT_CLK_OUT2_S : \
|
||||
(channel == CLKOUT_CHANNEL_3) ? GPIO_EXT_CLK_OUT3_S : 0)
|
||||
|
||||
ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user