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feat(esp_hw_support): support PMU clock ICG management for esp32s31

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This commit is contained in:
wuzhenghui
2026-06-17 11:34:37 +08:00
parent 902a849e7f
commit 61be47b739
41 changed files with 215 additions and 87 deletions
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components/esp_hw_support/port/esp32c5/pmu_sleep.c
+1 -1
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@@ -234,7 +234,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
+1 -1
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@@ -332,7 +332,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32c6/pmu_sleep.c
+1 -1
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@@ -218,7 +218,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
+1 -1
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@@ -328,7 +328,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32c61/pmu_sleep.c
+1 -1
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@@ -228,7 +228,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
+1 -1
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@@ -328,7 +328,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h2/pmu_sleep.c
+1 -1
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@@ -131,7 +131,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
+1 -1
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@@ -320,7 +320,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h21/pmu_sleep.c
+1 -1
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@@ -144,7 +144,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32h21/private_include/pmu_param.h
+1 -1
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@@ -356,7 +356,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h4/pmu_sleep.c
+1 -1
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@@ -129,7 +129,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32h4/private_include/pmu_param.h
+1 -1
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@@ -360,7 +360,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = clk_flags \
.icg_func = (uint32_t)(clk_flags) \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+1 -1
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@@ -160,7 +160,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
components/esp_hw_support/port/esp32p4/pmu_sleep_clock_icg.c
+1 -1
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@@ -182,7 +182,7 @@ void pmu_sleep_clock_icg_config(void *icg_context, const uint32_t icg_func)
if (icg_func & BIT(PMU_ICG_FUNC_ENA_IOMUX)) {
regdma_link_set_write_wait_content(clock_icg->regdma_desc[28], PERI_CLK_EN(IOMUX), PERI_CLK_MASK(IOMUX));
}
if (icg_func & BIT(PMU_ICG_FUNC_ENA_LEDC)) {
if (icg_func & BIT(PMU_ICG_FUNC_ENA_LEDC0)) {
regdma_link_set_write_wait_content(clock_icg->regdma_desc[24], PERI_CLK_EN(LEDC), PERI_CLK_MASK(LEDC));
}
if (icg_func & BIT(PMU_ICG_FUNC_ENA_UART0)) {
components/esp_hw_support/port/esp32p4/private_include/pmu_icg_mapping.h
+1 -1
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@@ -21,5 +21,5 @@
#define PMU_ICG_FUNC_ENA_UART2 8
#define PMU_ICG_FUNC_ENA_UART3 9
#define PMU_ICG_FUNC_ENA_UART4 10
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_LEDC0 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
+2 -2
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@@ -357,7 +357,7 @@ typedef struct {
.lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = { 0, clk_flags } \
.icg_func = { 0, (uint32_t)(clk_flags) } \
}
#else // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
@@ -373,7 +373,7 @@ typedef struct {
.dig_pad_slp_sel = 0, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = { 0, clk_flags } \
.icg_func = { 0, (uint32_t)(clk_flags) } \
}
#endif
components/esp_hw_support/port/esp32s31/pmu_sleep.c
+6 -2
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@@ -192,7 +192,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
uint32_t clk_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
@@ -212,7 +212,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->analog = analog_default;
} else {
// Get light sleep digital_default
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
config->digital = digital_default;
// Get light sleep analog default
@@ -281,6 +281,10 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi
static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig)
{
const bool icg_func_enabled = (dig->icg_func.clock[0] != 0) || (dig->icg_func.clock[1] != 0);
pmu_ll_hp_set_icg_sysclk_enable(ctx->hal->dev, HP(SLEEP), icg_func_enabled);
pmu_ll_hp_set_icg_func(ctx->hal->dev, HP(SLEEP), dig->icg_func.clock[0], dig->icg_func.clock[1]);
pmu_ll_hp_set_icg_apb(ctx->hal->dev, HP(SLEEP), dig->icg_apb.clock[0], dig->icg_apb.clock[1]);
pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel);
pmu_ll_hp_set_hold_all_hp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.hp_pad_hold_all);
pmu_ll_hp_set_hold_all_lp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.lp_pad_hold_all);
components/esp_hw_support/port/esp32s31/private_include/pmu_param.h
+15 -3
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@@ -11,6 +11,7 @@
#include <esp_types.h>
#include "soc/pmu_struct.h"
#include "hal/pmu_hal.h"
#include "soc/pmu_icg_mapping.h"
#ifdef __cplusplus
extern "C" {
@@ -324,6 +325,12 @@ typedef struct {
typedef struct {
pmu_hp_sys_cntl_reg_t syscntl;
struct {
uint32_t clock[2];
} icg_func;
struct {
uint32_t clock[2];
} icg_apb;
} pmu_sleep_digital_config_t;
@@ -334,17 +341,22 @@ typedef struct {
.hp_pad_hold_all = 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
.c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \
} \
}, \
.icg_func = { .clock = { 0, 0 } }, \
}
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) { \
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
.syscntl = { \
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.lp_pad_hold_all = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
.hp_pad_hold_all = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
.c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \
} \
}, \
.icg_func = { \
.clock = { PMU_SLEEP_CLK_ICG_FUNC_LO(clk_flags), \
PMU_SLEEP_CLK_ICG_FUNC_HI(clk_flags) } \
}, \
}
typedef struct {