Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets

Browse Source 
Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2 and ESP32-S3 to expose the
number of FSLS USB_WRAP PHYs available on each target. This separates
FSLS USB_WRAP support from OTG/UTMI support so that downstream code can
gate FSLS PHY handling independently.
This commit is contained in:
igor.masar
2026-04-24 13:39:08 +02:00
parent d125a34453
commit 6141df83e0
4 changed files with 10 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -839,6 +839,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
components/soc/esp32s2/include/soc/soc_caps.h
+1
View File
@@ -359,6 +359,7 @@
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (1U)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -1007,6 +1007,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
components/soc/esp32s3/include/soc/soc_caps.h
+1
View File
@@ -399,6 +399,7 @@
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (1U)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,