Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feat/esp32c61_adc_support' into 'master'

Browse Source 
ADC: support ADC oneshot and continuous mode on ESP32C61

Closes IDF-9302 and IDF-9304

See merge request espressif/esp-idf!32907
This commit is contained in:
Gao Xu
2024-11-11 10:22:47 +08:00
parent d74e99c08a efd04b7709
commit 611e163024
32 changed files with 1189 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c61/adc_periph.c
+18
View File
@@ -0,0 +1,18 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
ADC1_CHANNEL_1_GPIO_NUM,
ADC1_CHANNEL_2_GPIO_NUM,
ADC1_CHANNEL_3_GPIO_NUM,
},
};
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+79 -3
View File
@@ -3,6 +3,10 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_ADC_SUPPORTED
bool
default y
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
@@ -167,18 +171,90 @@ config SOC_XTAL_SUPPORT_40M
bool
default y
config SOC_ADC_DIG_CTRL_SUPPORTED
bool
default y
config SOC_ADC_DIG_IIR_FILTER_SUPPORTED
bool
default y
config SOC_ADC_MONITOR_SUPPORTED
bool
default y
config SOC_ADC_DMA_SUPPORTED
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 1
bool
default y
config SOC_ADC_MAX_CHANNEL_NUM
int
default 7
default 4
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_DIGI_RESULT_BYTES
int
default 4
config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_TEMPERATURE_SHARE_INTR
bool
default y
config SOC_ADC_SHARED_POWER
bool
default y
config SOC_APB_BACKUP_DMA
bool
default n
components/soc/esp32c61/include/soc/adc_channel.h
+8 -18
View File
@@ -6,24 +6,14 @@
#pragma once
// TODO: [ESP32-C61] IDF-9302 Check the channel
#define ADC1_GPIO0_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO1_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 1
#define ADC1_GPIO1_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO3_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 3
#define ADC1_GPIO2_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO4_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 4
#define ADC1_GPIO3_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL 4
#define ADC1_CHANNEL_4_GPIO_NUM 4
#define ADC1_GPIO5_CHANNEL 5
#define ADC1_CHANNEL_5_GPIO_NUM 5
#define ADC1_GPIO6_CHANNEL 6
#define ADC1_CHANNEL_6_GPIO_NUM 6
#define ADC1_GPIO5_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 5
components/soc/esp32c61/include/soc/soc_caps.h
+26 -27
View File
@@ -17,7 +17,7 @@
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
// \#define SOC_ADC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
#define SOC_ADC_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
@@ -67,35 +67,34 @@
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_40M 1
//TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
// \#define SOC_ADC_DIG_CTRL_SUPPORTED 1
// \#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
// \#define SOC_ADC_MONITOR_SUPPORTED 1
// \#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
// \#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_MAX_CHANNEL_NUM (7)
// \#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7)
// \#define SOC_ADC_ATTEN_NUM (4)
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1)
#define SOC_ADC_MAX_CHANNEL_NUM (4)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (4)
#define SOC_ADC_ATTEN_NUM (4)
// /*!< Digital */
// \#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
// \#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
// \#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
// \#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
// \#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
// \#define SOC_ADC_DIGI_MONITOR_NUM (2)
// \#define SOC_ADC_DIGI_RESULT_BYTES (4)
// \#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
// /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
// \#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
// \#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
// /*!< RTC */
// \#define SOC_ADC_RTC_MIN_BITWIDTH (12)
// \#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
// /*!< Calibration */ // TODO: [ESP32C61] IDF-9303
// \#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
@@ -106,7 +105,7 @@
#define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
/*!< ADC power control is shared by PWDET */
// \#define SOC_ADC_SHARED_POWER 1
#define SOC_ADC_SHARED_POWER 1
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (0)
components/soc/esp32c61/register/soc/reg_base.h
+1
View File
@@ -61,3 +61,4 @@
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_CACHE_BASE 0x600C8000
#define DR_REG_CLINT_M_BASE 0x20000000
#define PWDET_CONF_REG 0x600A0808