mirror of
https://github.com/espressif/esp-idf.git
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feat(esp32p4): Support newer Key Manager key sources for ESP32-P4 V3
This commit is contained in:
harshal.patil
@@ -209,7 +209,11 @@ config SOC_ECDSA_SUPPORTED
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config SOC_KEY_MANAGER_SUPPORTED
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bool
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default n
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default y
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config SOC_HUK_SUPPORTED
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bool
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default y
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config SOC_FLASH_ENC_SUPPORTED
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bool
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@@ -1753,7 +1757,7 @@ config SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
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bool
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default y
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default n
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config SOC_KEY_MANAGER_FE_KEY_DEPLOY
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bool
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@@ -1767,6 +1771,14 @@ config SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
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bool
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default y
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config SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
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bool
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default y
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config SOC_KEY_MANAGER_DS_KEY_DEPLOY
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bool
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default y
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config SOC_SECURE_BOOT_V2_RSA
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bool
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default y
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@@ -73,8 +73,9 @@
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#define SOC_DIG_SIGN_SUPPORTED 1
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#define SOC_ECC_SUPPORTED 1
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#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
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#define SOC_ECDSA_SUPPORTED 0
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#define SOC_KEY_MANAGER_SUPPORTED 0
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#define SOC_ECDSA_SUPPORTED 0 // TODO: IDF-13523
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#define SOC_KEY_MANAGER_SUPPORTED 1
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#define SOC_HUK_SUPPORTED 1
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#define SOC_FLASH_ENC_SUPPORTED 1
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#define SOC_SECURE_BOOT_SUPPORTED 1
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#define SOC_BOD_SUPPORTED 1
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@@ -654,10 +655,12 @@
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/*-------------------------- Key Manager CAPS----------------------------*/
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#define SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1 /*!< Key manager supports key deployment */
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#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */
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#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 0 /*!< Key manager responsible to deploy ECDSA key */ // TODO: IDF-13523
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#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */
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#define SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 1 /*!< Key manager responsible to deploy the XTS-AES-128 key */
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#define SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 1 /*!< Key manager responsible to deploy the XTS-AES-256 key */
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#define SOC_KEY_MANAGER_HMAC_KEY_DEPLOY 1 /*!< Key manager responsible to deploy HMAC key */
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#define SOC_KEY_MANAGER_DS_KEY_DEPLOY 1 /*!< Key manager responsible to deploy DS key */
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/*-------------------------- Secure Boot CAPS----------------------------*/
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#define SOC_SECURE_BOOT_V2_RSA 1
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@@ -1,395 +0,0 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** KEYMNG_CLK_REG register
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* Key Manager clock gate control register
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*/
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#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
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/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
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* Write 1 to force on register clock gate.
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*/
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#define KEYMNG_REG_CG_FORCE_ON (BIT(0))
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#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
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#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U
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#define KEYMNG_REG_CG_FORCE_ON_S 0
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/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
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* Write 1 to force on memory clock gate.
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*/
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#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
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#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
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#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
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#define KEYMNG_MEM_CG_FORCE_ON_S 1
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/** KEYMNG_INT_RAW_REG register
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* Key Manager interrupt raw register, valid in level.
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*/
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#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
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/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
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#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
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#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_RAW_S 0
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/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
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#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
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#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_RAW_S 1
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/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status bit for the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
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#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
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#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_RAW_S 2
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/** KEYMNG_INT_ST_REG register
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* Key Manager interrupt status register.
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*/
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#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
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/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
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#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
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#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_ST_S 0
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/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
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#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
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#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_ST_S 1
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/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
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* The masked interrupt status bit for the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_ST (BIT(2))
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#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
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#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_ST_S 2
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/** KEYMNG_INT_ENA_REG register
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* Key Manager interrupt enable register.
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*/
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#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
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/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
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#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
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#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_ENA_S 0
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/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
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#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
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#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_ENA_S 1
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/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
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* The interrupt enable bit for the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
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#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
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#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_ENA_S 2
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/** KEYMNG_INT_CLR_REG register
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* Key Manager interrupt clear register.
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*/
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#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
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/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
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#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
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#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_CLR_S 0
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/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
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#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
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#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_CLR_S 1
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/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
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* Set this bit to clear the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
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#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
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#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_CLR_S 2
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/** KEYMNG_STATIC_REG register
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* Key Manager static configuration register
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*/
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#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
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/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
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* Set each bit to choose efuse key instead of key manager deployed key. Each bit
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* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
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* bit 1 for flash_key; bit 0 for ecdsa_key
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*/
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#define KEYMNG_USE_EFUSE_KEY 0x0000001FU
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#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
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#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
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#define KEYMNG_USE_EFUSE_KEY_S 0
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/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
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* The core clock cycle number to sample one rng input data. Please set it bigger than
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* the clock cycle ratio: T_rng/T_km
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*/
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#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
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#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
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#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
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#define KEYMNG_RND_SWITCH_CYCLE_S 5
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/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
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* Set this bit to use software written init key instead of efuse_init_key.
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*/
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#define KEYMNG_USE_SW_INIT_KEY (BIT(10))
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#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
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#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
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#define KEYMNG_USE_SW_INIT_KEY_S 10
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/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
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* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
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* xts-aes-256. 0: use xts-aes-128.
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*/
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#define KEYMNG_FLASH_KEY_LEN (BIT(11))
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#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
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#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U
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#define KEYMNG_FLASH_KEY_LEN_S 11
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/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
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* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
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* xts-aes-256. 0: use xts-aes-128.
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*/
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#define KEYMNG_PSRAM_KEY_LEN (BIT(12))
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#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
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#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U
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#define KEYMNG_PSRAM_KEY_LEN_S 12
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/** KEYMNG_LOCK_REG register
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* Key Manager static configuration locker register
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*/
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#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
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/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
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* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
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* reg_use_efuse_key.
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*/
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#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU
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#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
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#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
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#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
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/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
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* Write 1 to lock reg_rnd_switch_cycle.
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*/
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#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5))
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#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
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#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
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#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5
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/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
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* Write 1 to lock reg_use_sw_init_key.
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*/
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#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6))
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#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
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#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
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#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6
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/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
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* Write 1 to lock reg_flash_key_len.
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*/
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#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7))
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#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
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#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U
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#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7
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/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
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* Write 1 to lock reg_psram_key_len.
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*/
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#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8))
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#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
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#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U
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#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8
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/** KEYMNG_CONF_REG register
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* Key Manager configuration register
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*/
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#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
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/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
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* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
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* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
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*/
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#define KEYMNG_KGEN_MODE 0x00000007U
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#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
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#define KEYMNG_KGEN_MODE_V 0x00000007U
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#define KEYMNG_KGEN_MODE_S 0
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/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
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* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
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* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
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* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
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* ecdsa_key_384_h. Others: reserved.
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*/
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#define KEYMNG_KEY_PURPOSE 0x0000000FU
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#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
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#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
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#define KEYMNG_KEY_PURPOSE_S 3
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/** KEYMNG_START_REG register
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* Key Manager control register
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*/
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#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
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/** KEYMNG_START : WT; bitpos: [0]; default: 0;
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* Write 1 to continue Key Manager operation at LOAD/GAIN state.
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*/
|
||||
#define KEYMNG_START (BIT(0))
|
||||
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
|
||||
#define KEYMNG_START_V 0x00000001U
|
||||
#define KEYMNG_START_S 0
|
||||
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to start Key Manager at IDLE state.
|
||||
*/
|
||||
#define KEYMNG_CONTINUE (BIT(1))
|
||||
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
|
||||
#define KEYMNG_CONTINUE_V 0x00000001U
|
||||
#define KEYMNG_CONTINUE_S 1
|
||||
|
||||
/** KEYMNG_STATE_REG register
|
||||
* Key Manager state register
|
||||
*/
|
||||
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
|
||||
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
|
||||
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
|
||||
*/
|
||||
#define KEYMNG_STATE 0x00000003U
|
||||
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
|
||||
#define KEYMNG_STATE_V 0x00000003U
|
||||
#define KEYMNG_STATE_S 0
|
||||
|
||||
/** KEYMNG_RESULT_REG register
|
||||
* Key Manager operation result register
|
||||
*/
|
||||
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
|
||||
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
|
||||
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
|
||||
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
|
||||
*/
|
||||
#define KEYMNG_PROC_RESULT (BIT(0))
|
||||
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
|
||||
#define KEYMNG_PROC_RESULT_V 0x00000001U
|
||||
#define KEYMNG_PROC_RESULT_S 0
|
||||
|
||||
/** KEYMNG_KEY_VLD_REG register
|
||||
* Key Manager key status register
|
||||
*/
|
||||
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
|
||||
/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0))
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_S 0
|
||||
/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
|
||||
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1))
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_S 1
|
||||
/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
|
||||
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_FLASH_VLD (BIT(2))
|
||||
#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
|
||||
#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_FLASH_VLD_S 2
|
||||
/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
|
||||
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_HMAC_VLD (BIT(3))
|
||||
#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
|
||||
#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_HMAC_VLD_S 3
|
||||
/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
|
||||
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_DS_VLD (BIT(4))
|
||||
#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
|
||||
#define KEYMNG_KEY_DS_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_DS_VLD_S 4
|
||||
/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
|
||||
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_PSRAM_VLD (BIT(5))
|
||||
#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
|
||||
#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_PSRAM_VLD_S 5
|
||||
/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
|
||||
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6))
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_S 6
|
||||
|
||||
/** KEYMNG_HUK_VLD_REG register
|
||||
* Key Manager HUK status register
|
||||
*/
|
||||
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
|
||||
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
|
||||
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
|
||||
*/
|
||||
#define KEYMNG_HUK_VALID (BIT(0))
|
||||
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
|
||||
#define KEYMNG_HUK_VALID_V 0x00000001U
|
||||
#define KEYMNG_HUK_VALID_S 0
|
||||
|
||||
/** KEYMNG_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
|
||||
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
|
||||
* Key Manager version control register.
|
||||
*/
|
||||
#define KEYMNG_DATE 0x0FFFFFFFU
|
||||
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
|
||||
#define KEYMNG_DATE_V 0x0FFFFFFFU
|
||||
#define KEYMNG_DATE_S 0
|
||||
|
||||
/** KEYMNG_ASSIST_INFO_MEM register
|
||||
* The memory that stores assist key info.
|
||||
*/
|
||||
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
|
||||
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
|
||||
|
||||
/** KEYMNG_PUBLIC_INFO_MEM register
|
||||
* The memory that stores public key info.
|
||||
*/
|
||||
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
|
||||
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
|
||||
|
||||
/** KEYMNG_SW_INIT_KEY_MEM register
|
||||
* The memory that stores software written init key.
|
||||
*/
|
||||
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
|
||||
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -15,13 +15,13 @@ extern "C" {
|
||||
* Key Manager clock gate control register
|
||||
*/
|
||||
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
|
||||
/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
|
||||
/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
#define KEYMNG_CLK_EN (BIT(0))
|
||||
#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
|
||||
#define KEYMNG_CLK_EN_V 0x00000001U
|
||||
#define KEYMNG_CLK_EN_S 0
|
||||
#define KEYMNG_REG_CG_FORCE_ON (BIT(0))
|
||||
#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
|
||||
#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U
|
||||
#define KEYMNG_REG_CG_FORCE_ON_S 0
|
||||
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 to force on memory clock gate.
|
||||
*/
|
||||
@@ -138,85 +138,165 @@ extern "C" {
|
||||
* Key Manager static configuration register
|
||||
*/
|
||||
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
|
||||
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
|
||||
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
|
||||
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
|
||||
* bit 1 for flash_key; bit 0 for ecdsa_key
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY 0x0000001FU
|
||||
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
|
||||
#define KEYMNG_USE_EFUSE_KEY_S 0
|
||||
|
||||
/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: Set this bit to choose efuse key instead of key manager deployed key for xts_key.*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_XTS (BIT(1))
|
||||
#define KEYMNG_USE_EFUSE_KEY_XTS_M ((KEYMNG_USE_EFUSE_KEY_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_XTS_S))
|
||||
#define KEYMNG_USE_EFUSE_KEY_XTS_V 0x1
|
||||
#define KEYMNG_USE_EFUSE_KEY_XTS_S 1
|
||||
|
||||
/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa_key.*/
|
||||
/** KEYMNG_USE_EFUSE_KEY_ECDSA : R/W; bitpos:[0]; default: 0;
|
||||
* Set this bit to choose efuse key instead of key manager deployed key for ecdsa.
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_ECDSA (BIT(0))
|
||||
#define KEYMNG_USE_EFUSE_KEY_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S))
|
||||
#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x1
|
||||
#define KEYMNG_USE_EFUSE_KEY_ECDSA_M (KEYMNG_USE_EFUSE_KEY_ECDSA_V << KEYMNG_USE_EFUSE_KEY_ECDSA_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_ECDSA_S 0
|
||||
|
||||
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
|
||||
/** KEYMNG_USE_EFUSE_KEY_FLASH : R/W; bitpos:[1]; default: 0;
|
||||
* Set this bit to choose efuse key instead of key manager deployed key for flash.
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_FLASH (BIT(1))
|
||||
#define KEYMNG_USE_EFUSE_KEY_FLASH_M (KEYMNG_USE_EFUSE_KEY_FLASH_V << KEYMNG_USE_EFUSE_KEY_FLASH_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_FLASH_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_FLASH_S 1
|
||||
|
||||
/** KEYMNG_USE_EFUSE_KEY_HMAC : R/W; bitpos:[0]; default: 0;
|
||||
* Set this bit to choose efuse key instead of key manager deployed key for hmac.
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_HMAC (BIT(2))
|
||||
#define KEYMNG_USE_EFUSE_KEY_HMAC_M (KEYMNG_USE_EFUSE_KEY_HMAC_V << KEYMNG_USE_EFUSE_KEY_HMAC_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_HMAC_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_HMAC_S 2
|
||||
|
||||
/** KEYMNG_USE_EFUSE_KEY_DS : R/W; bitpos:[1]; default: 0;
|
||||
* Set this bit to choose efuse key instead of key manager deployed key for ds.
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_DS (BIT(3))
|
||||
#define KEYMNG_USE_EFUSE_KEY_DS_M (KEYMNG_USE_EFUSE_KEY_DS_V << KEYMNG_USE_EFUSE_KEY_DS_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_DS_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_DS_S 3
|
||||
|
||||
/** KEYMNG_USE_EFUSE_KEY_PSRAM : R/W; bitpos:[1]; default: 0;
|
||||
* Set this bit to choose efuse key instead of key manager deployed key for psram.
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_PSRAM (BIT(4))
|
||||
#define KEYMNG_USE_EFUSE_KEY_PSRAM_M (KEYMNG_USE_EFUSE_KEY_PSRAM_V << KEYMNG_USE_EFUSE_KEY_PSRAM_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_PSRAM_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_PSRAM_S 4
|
||||
|
||||
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
|
||||
* The core clock cycle number to sample one rng input data. Please set it bigger than
|
||||
* the clock cycle ratio: T_rng/T_km
|
||||
*/
|
||||
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_S 4
|
||||
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_S 5
|
||||
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
|
||||
* Set this bit to use software written init key instead of efuse_init_key.
|
||||
*/
|
||||
#define KEYMNG_USE_SW_INIT_KEY (BIT(9))
|
||||
#define KEYMNG_USE_SW_INIT_KEY (BIT(10))
|
||||
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
|
||||
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
|
||||
#define KEYMNG_USE_SW_INIT_KEY_S 9
|
||||
/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
|
||||
* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
|
||||
* xts-aes-128.
|
||||
#define KEYMNG_USE_SW_INIT_KEY_S 10
|
||||
/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
|
||||
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
|
||||
* xts-aes-256. 0: use xts-aes-128.
|
||||
*/
|
||||
#define KEYMNG_XTS_AES_KEY_LEN (BIT(10))
|
||||
#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
|
||||
#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U
|
||||
#define KEYMNG_XTS_AES_KEY_LEN_S 10
|
||||
#define KEYMNG_FLASH_KEY_LEN (BIT(11))
|
||||
#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
|
||||
#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U
|
||||
#define KEYMNG_FLASH_KEY_LEN_S 11
|
||||
/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
|
||||
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
|
||||
* xts-aes-256. 0: use xts-aes-128.
|
||||
*/
|
||||
#define KEYMNG_PSRAM_KEY_LEN (BIT(12))
|
||||
#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
|
||||
#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U
|
||||
#define KEYMNG_PSRAM_KEY_LEN_S 12
|
||||
|
||||
/** KEYMNG_LOCK_REG register
|
||||
* Key Manager static configuration locker register
|
||||
*/
|
||||
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
|
||||
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
|
||||
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
|
||||
* reg_use_efuse_key.
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
|
||||
|
||||
/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ; bitpos:[1] ; default: 1'd0 ; */
|
||||
/* description: Set thus bit to choose efuse key instead of key manager deployed key for xts_key */
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS (BIT(1))
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_M ((KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S))
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V 0x1
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S 1
|
||||
|
||||
/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W ; bitpos:[0] ; default: 1'd0 ; */
|
||||
/* description: Write 1 to lock ecdsa-key */
|
||||
/** KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W1 ;bitpos:[0]; default: 0;
|
||||
* Write 1 to lock reg_use_efuse_key for esdsa
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA (BIT(0))
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S))
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x1
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M (KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V << KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S 0
|
||||
/** KEYMNG_USE_EFUSE_KEY_LOCK_FLASH : R/W1 ;bitpos:[1]; default: 0;
|
||||
* Write 1 to lock reg_use_efuse_key for FLASH
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH (BIT(1))
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_M (KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V << KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S 1
|
||||
/** KEYMNG_USE_EFUSE_KEY_LOCK_HMAC : R/W1 ;bitpos:[0]; default: 0;
|
||||
* Write 1 to lock reg_use_efuse_key for hmac
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC (BIT(2))
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_M (KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V << KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S 2
|
||||
/** KEYMNG_USE_EFUSE_KEY_LOCK_DS : R/W1 ;bitpos:[1]; default: 0;
|
||||
* Write 1 to lock reg_use_efuse_key for ds
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_DS (BIT(3))
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_M (KEYMNG_USE_EFUSE_KEY_LOCK_DS_V << KEYMNG_USE_EFUSE_KEY_LOCK_DS_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_S 3
|
||||
/** KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM : R/W1 ;bitpos:[1]; default: 0;
|
||||
* Write 1 to lock reg_use_efuse_key for PSRAM
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM (BIT(4))
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_M (KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V << KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V 0x00000001U
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S 4
|
||||
|
||||
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
|
||||
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
|
||||
* Write 1 to lock reg_rnd_switch_cycle.
|
||||
*/
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4))
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5))
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4
|
||||
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5
|
||||
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
|
||||
* Write 1 to lock reg_use_sw_init_key.
|
||||
*/
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5))
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6))
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5
|
||||
/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
|
||||
* Write 1 to lock reg_xts_aes_key_len.
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6
|
||||
/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
|
||||
* Write 1 to lock reg_flash_key_len.
|
||||
*/
|
||||
#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6))
|
||||
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
|
||||
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U
|
||||
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6
|
||||
#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7))
|
||||
#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
|
||||
#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U
|
||||
#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7
|
||||
/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
|
||||
* Write 1 to lock reg_psram_key_len.
|
||||
*/
|
||||
#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8))
|
||||
#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
|
||||
#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U
|
||||
#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8
|
||||
|
||||
/** KEYMNG_CONF_REG register
|
||||
* Key Manager configuration register
|
||||
@@ -231,29 +311,16 @@ extern "C" {
|
||||
#define KEYMNG_KGEN_MODE_V 0x00000007U
|
||||
#define KEYMNG_KGEN_MODE_S 0
|
||||
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
|
||||
* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
|
||||
* xts_256_2_key. 4. xts_128_key. others: reserved.
|
||||
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
|
||||
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
|
||||
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
|
||||
* ecdsa_key_384_h. Others: reserved.
|
||||
*/
|
||||
#define KEYMNG_KEY_PURPOSE 0x0000000FU
|
||||
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
|
||||
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
|
||||
#define KEYMNG_KEY_PURPOSE_S 3
|
||||
|
||||
#define KEYMNG_KEY_PURPOSE_ECDSA (BIT(0))
|
||||
#define KEYMNG_KEY_PURPOSE_ECDSA_M (KEYMNG_KEY_PURPOSE_ECDSA_V << KEYMNG_KEY_PURPOSE_ECDSA_S)
|
||||
#define KEYMNG_KEY_PURPOSE_ECDSA_V 0x00000001U
|
||||
#define KEYMNG_KEY_PURPOSE_ECDSA_S 0
|
||||
|
||||
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1 (BIT(1))
|
||||
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_M (KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S)
|
||||
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V 0x00000001U
|
||||
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S 1
|
||||
|
||||
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2 (BIT(2))
|
||||
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_M (KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S)
|
||||
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V 0x00000001U
|
||||
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S 2
|
||||
|
||||
/** KEYMNG_START_REG register
|
||||
* Key Manager control register
|
||||
*/
|
||||
@@ -302,22 +369,62 @@ extern "C" {
|
||||
* Key Manager key status register
|
||||
*/
|
||||
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
|
||||
/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_VLD (BIT(0))
|
||||
#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_VLD_S 0
|
||||
/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
|
||||
* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
|
||||
/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_XTS_VLD (BIT(1))
|
||||
#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
|
||||
#define KEYMNG_KEY_XTS_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_XTS_VLD_S 1
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0))
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_S 0
|
||||
/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
|
||||
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1))
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_S 1
|
||||
/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
|
||||
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_FLASH_VLD (BIT(2))
|
||||
#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
|
||||
#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_FLASH_VLD_S 2
|
||||
/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
|
||||
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_HMAC_VLD (BIT(3))
|
||||
#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
|
||||
#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_HMAC_VLD_S 3
|
||||
/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
|
||||
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_DS_VLD (BIT(4))
|
||||
#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
|
||||
#define KEYMNG_KEY_DS_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_DS_VLD_S 4
|
||||
/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
|
||||
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_PSRAM_VLD (BIT(5))
|
||||
#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
|
||||
#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_PSRAM_VLD_S 5
|
||||
/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
|
||||
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6))
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_S 6
|
||||
|
||||
/** KEYMNG_HUK_VLD_REG register
|
||||
* Key Manager HUK status register
|
||||
@@ -335,7 +442,7 @@ extern "C" {
|
||||
* Version control register
|
||||
*/
|
||||
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
|
||||
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
|
||||
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
|
||||
* Key Manager version control register.
|
||||
*/
|
||||
#define KEYMNG_DATE 0x0FFFFFFFU
|
||||
|
||||
Reference in New Issue
Block a user