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feat(psram): allow PSRAM to enter halfsleep mode during light sleep

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This commit is contained in:
Song Ruo Jing
2026-06-18 16:05:49 +08:00
parent 1ea37f2961
commit 6079c74f99
15 changed files with 291 additions and 26 deletions
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components/esp_hw_support/port/esp32p4/pmu_sleep.c
+25 -13
View File
@@ -40,6 +40,7 @@
#if CONFIG_SPIRAM
#include "hal/ldo_ll.h"
#include "hal/mspi_ll.h"
#include "esp_private/esp_psram_impl.h"
#endif
#if (CONFIG_ESP_REV_MIN_FULL == 300)
@@ -192,7 +193,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
// Get light sleep analog default
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
#if CONFIG_SPIRAM
#if CONFIG_SPIRAM && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
// Adjust analog parameters to keep EXT_LDO PSRAM channel volt outputting during light-sleep.
analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
analog_default.lp_sys[PMU_MODE_LP_SLEEP].analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
@@ -402,11 +403,15 @@ SPM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
// to be written back so that regdma can get the correct link.
// 3. We cannot use the API provided by ROM to invalidate the cache, since it is a function calling that writes data to the stack during
// the return process, which results in dirty cachelines in L1 Cache again.
pmu_sleep_cache_sync_items(SMMU_GID_DEFAULT, CACHE_SYNC_WRITEBACK, CACHE_MAP_L1_DCACHE, 0, 0);
pmu_sleep_cache_sync_items(SMMU_GID_DEFAULT, CACHE_SYNC_WRITEBACK, CACHE_MAP_L1_DCACHE, 0, 0); // No PSRAM dirty data after this time write back
if (!dslp) {
#if CONFIG_SPIRAM
psram_ctrlr_ll_wait_all_transaction_done();
#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED
esp_psram_impl_enter_halfsleep_mode();
#endif
mspi_ll_hold_all_psram_pins();
#endif
s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq();
if (s_mpll_freq_mhz_before_sleep) {
@@ -420,10 +425,10 @@ SPM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
_psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
_psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
}
mspi_ll_hold_all_psram_pins();
#endif
rtc_clk_mpll_disable();
}
pmu_sleep_cache_sync_items(SMMU_GID_DEFAULT, CACHE_SYNC_WRITEBACK, CACHE_MAP_L1_DCACHE, 0, 0); // No L2 MEM dirty data after this time write back
} else {
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
if (efuse_hal_chip_revision() == 300) {
@@ -487,19 +492,26 @@ SPM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
// Wait eFuse memory update done.
while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
if (s_mpll_freq_mhz_before_sleep && !dslp) {
rtc_clk_mpll_enable();
rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep, true);
if (!dslp) {
if (s_mpll_freq_mhz_before_sleep) {
rtc_clk_mpll_enable();
rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep, true);
#if CONFIG_SPIRAM
if (!s_pmu_sleep_regdma_backup_enabled) {
// MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.
// If it's a PD_TOP sleep, psram MSPI core clock will be enabled by REGDMA
_psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, true);
_psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, true);
if (!s_pmu_sleep_regdma_backup_enabled) {
// MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.
// If it's a PD_TOP sleep, psram MSPI core clock will be enabled by REGDMA
_psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, true);
_psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, true);
}
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_MPLL);
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_MPLL);
#endif
}
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_MPLL);
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_MPLL);
#if CONFIG_SPIRAM
mspi_ll_unhold_all_psram_pins();
#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED
esp_psram_impl_exit_halfsleep_mode();
#endif
#endif
}
components/esp_hw_support/port/esp32p4/rtc_time.c
+2 -1
View File
@@ -15,6 +15,7 @@
#include "soc/timer_group_reg.h"
#include "esp_rom_sys.h"
#include "esp_private/periph_ctrl.h"
#include "esp_attr.h"
__attribute__((unused)) static const char *TAG = "rtc_time";
@@ -209,7 +210,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
}
uint64_t rtc_time_get(void)
SPM_IRAM_ATTR uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
}
components/esp_hw_support/sleep_modes.c
+8
View File
@@ -156,6 +156,10 @@
#include "esp_private/sleep_retention.h"
#endif
#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED
#include "esp_private/esp_psram_impl.h"
#endif
// If light sleep time is less than that, don't power down flash
#define FLASH_PD_MIN_SLEEP_TIME_US 2000
@@ -1375,6 +1379,10 @@ static SLEEP_FN_ATTR esp_err_t esp_light_sleep_inner(uint32_t sleep_flags, uint3
esp_rom_delay_us(flash_enable_time_us);
}
#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED
esp_psram_impl_resume_from_halfsleep_mode(s_config.rtc_clk_cal_period);
#endif
#if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
if (sleep_flags & RTC_SLEEP_PD_VDDSDIO) {
/* Cache Resume 2: flash is ready now, we can resume the cache and access flash safely after */